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Commit 51164104 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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modules: reset refactor, to avoid multiple resyncs of same reset signal

parent d8ff8b02
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Showing with 386 additions and 298 deletions
modules/timing/dmtd_phase_meas.vhd
View file @ 51164104
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-02-25
-- Last update: 2011-05-11
-- Last update: 2017-02-20
-- Platform : FPGA-generic
-- Standard : VHDL '93
-------------------------------------------------------------------------------
......@@ -15,7 +15,7 @@
-- increase the accuracy.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2009 - 2010 CERN
-- Copyright (c) 2009 - 2017 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
......@@ -55,8 +55,9 @@ entity dmtd_phase_meas is
g_counter_bits : integer := 14);
port (
-- [clk_sys_i] reset
rst_n_i : in std_logic;
-- resets
rst_sys_n_i : in std_logic;
rst_dmtd_n_i : in std_logic;
-- system clock
clk_sys_i : in std_logic;
......@@ -75,10 +76,8 @@ entity dmtd_phase_meas is
end dmtd_phase_meas;
architecture syn of dmtd_phase_meas is
component dmtd_with_deglitcher
generic (
g_counter_bits : natural);
......@@ -98,9 +97,6 @@ architecture syn of dmtd_phase_meas is
type t_pd_state is (PD_WAIT_TAG, PD_WAIT_A, PD_WAIT_B);
signal rst_n_dmtdclk : std_logic;
signal rst_n_sysclk : std_logic;
signal tag_a : std_logic_vector(g_counter_bits-1 downto 0);
signal tag_b : std_logic_vector(g_counter_bits-1 downto 0);
......@@ -123,26 +119,12 @@ architecture syn of dmtd_phase_meas is
begin -- syn
rst_n_sysclk <= rst_n_i;
-- reset sync for DMTD sampling clock
sync_reset_dmtdclk : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => clk_dmtd_i,
rst_n_i => rst_n_i,
data_i => rst_n_sysclk,
synced_o => rst_n_dmtdclk,
npulse_o => open,
ppulse_o => open);
DMTD_A : dmtd_with_deglitcher
generic map (
g_counter_bits => g_counter_bits)
port map (
rst_n_dmtdclk_i => rst_n_dmtdclk,
rst_n_sysclk_i => rst_n_sysclk,
rst_n_dmtdclk_i => rst_dmtd_n_i,
rst_n_sysclk_i => rst_sys_n_i,
clk_dmtd_i => clk_dmtd_i,
clk_sys_i => clk_sys_i,
clk_in_i => clk_a_i,
......@@ -157,8 +139,8 @@ begin -- syn
generic map (
g_counter_bits => g_counter_bits)
port map (
rst_n_dmtdclk_i => rst_n_dmtdclk,
rst_n_sysclk_i => rst_n_sysclk,
rst_n_dmtdclk_i => rst_dmtd_n_i,
rst_n_sysclk_i => rst_sys_n_i,
clk_dmtd_i => clk_dmtd_i,
clk_sys_i => clk_sys_i,
clk_in_i => clk_b_i,
......@@ -170,10 +152,10 @@ begin -- syn
dbg_dmtdout_o => open);
collect_tags : process (clk_sys_i, rst_n_sysclk)
collect_tags : process (clk_sys_i)
begin -- process
if rising_edge(clk_sys_i) then
if(rst_n_sysclk = '0' or en_i = '0') then
if(rst_sys_n_i = '0' or en_i = '0') then
phase_raw <= (others => '0');
phase_raw_p <= '0';
ph_acq_valid <= '0';
......@@ -243,10 +225,10 @@ begin -- syn
phase_lo <= '1' when phase_raw(phase_raw'high downto phase_raw'high-1) = "00" else '0';
calc_error : process (clk_sys_i, rst_n_sysclk)
calc_error : process (clk_sys_i)
begin -- process calc_error
if rising_edge(clk_sys_i) then
if(rst_n_sysclk = '0' or en_i = '0') then
if(rst_sys_n_i = '0' or en_i = '0') then
acc <= (others => '0');
avg_cnt <= (others => '0');
phase_meas_p_o <= '0';
......
modules/wr_endpoint/endpoint_pkg.vhd
View file @ 51164104
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-04-26
-- Last update: 2017-02-16
-- Last update: 2017-02-20
-- Platform : FPGA-generic
-- Standard : VHDL '93
-------------------------------------------------------------------------------
......@@ -191,7 +191,11 @@ package endpoint_pkg is
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
clk_dmtd_i : in std_logic := '0';
rst_n_i : in std_logic;
rst_sys_n_i : in std_logic;
rst_ref_n_i : in std_logic;
rst_dmtd_n_i : in std_logic;
rst_txclk_n_i : in std_logic;
rst_rxclk_n_i : in std_logic;
pps_csync_p1_i : in std_logic := '0';
pps_valid_i : in std_logic := '1';
phy_rst_o : out std_logic;
......@@ -296,7 +300,11 @@ package endpoint_pkg is
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
clk_dmtd_i : in std_logic;
rst_n_i : in std_logic;
rst_sys_n_i : in std_logic;
rst_ref_n_i : in std_logic;
rst_dmtd_n_i : in std_logic;
rst_txclk_n_i : in std_logic;
rst_rxclk_n_i : in std_logic;
pps_csync_p1_i : in std_logic;
pps_valid_i : in std_logic := '1';
phy_rst_o : out std_logic;
......
modules/wr_endpoint/endpoint_private_pkg.vhd
View file @ 51164104
......@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-11-18
-- Last update: 2017-02-16
-- Last update: 2017-02-20
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -118,7 +118,9 @@ package endpoint_private_pkg is
g_simulation : boolean;
g_16bit : boolean);
port (
rst_n_i : in std_logic;
rst_sys_n_i : in std_logic;
rst_txclk_n_i : in std_logic;
rst_rxclk_n_i : in std_logic;
clk_sys_i : in std_logic;
rxpcs_fab_o : out t_ep_internal_fabric;
rxpcs_fifo_almostfull_i : in std_logic;
......@@ -167,11 +169,13 @@ package endpoint_private_pkg is
component ep_tx_pcs_8bit
port (
rst_n_i : in std_logic;
rst_txclk_n_i : in std_logic;
clk_sys_i : in std_logic;
pcs_fab_i : in t_ep_internal_fabric;
pcs_error_o : out std_logic;
pcs_busy_o : out std_logic;
pcs_dreq_o : out std_logic;
mdio_mcr_reset_i : in std_logic;
mdio_mcr_pdown_i : in std_logic;
mdio_wr_spec_tx_cal_i : in std_logic;
an_tx_en_i : in std_logic;
......@@ -188,11 +192,13 @@ package endpoint_private_pkg is
component ep_tx_pcs_16bit
port (
rst_n_i : in std_logic;
rst_txclk_n_i : in std_logic;
clk_sys_i : in std_logic;
pcs_fab_i : in t_ep_internal_fabric;
pcs_error_o : out std_logic;
pcs_busy_o : out std_logic;
pcs_dreq_o : out std_logic;
mdio_mcr_reset_i : in std_logic;
mdio_mcr_pdown_i : in std_logic;
mdio_wr_spec_tx_cal_i : in std_logic;
an_tx_en_i : in std_logic;
......@@ -214,6 +220,7 @@ package endpoint_private_pkg is
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
rst_rxclk_n_i : in std_logic;
pcs_fifo_almostfull_i : in std_logic;
pcs_busy_o : out std_logic;
pcs_fab_o : out t_ep_internal_fabric;
......@@ -226,6 +233,7 @@ package endpoint_private_pkg is
phy_rx_data_i : in std_logic_vector(7 downto 0);
phy_rx_k_i : in std_logic;
phy_rx_enc_err_i : in std_logic;
mdio_mcr_reset_i : in std_logic;
mdio_mcr_pdown_i : in std_logic;
mdio_wr_spec_cal_crst_i : in std_logic;
mdio_wr_spec_rx_cal_stat_o : out std_logic;
......@@ -246,6 +254,7 @@ package endpoint_private_pkg is
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
rst_rxclk_n_i : in std_logic;
pcs_fifo_almostfull_i : in std_logic;
pcs_busy_o : out std_logic;
pcs_fab_o : out t_ep_internal_fabric;
......@@ -258,6 +267,7 @@ package endpoint_private_pkg is
phy_rx_data_i : in std_logic_vector(15 downto 0);
phy_rx_k_i : in std_logic_vector(1 downto 0);
phy_rx_enc_err_i : in std_logic;
mdio_mcr_reset_i : in std_logic;
mdio_mcr_pdown_i : in std_logic;
mdio_wr_spec_cal_crst_i : in std_logic;
mdio_wr_spec_rx_cal_stat_o : out std_logic;
......
modules/wr_endpoint/ep_1000basex_pcs.vhd
View file @ 51164104
......@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-11-18
-- Last update: 2017-02-16
-- Last update: 2017-02-20
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -68,11 +68,13 @@ entity ep_1000basex_pcs is
port (
---------------------------------------------------------------------------
-- System clock & reset
-- System clock & resets (system + rx/tx)
---------------------------------------------------------------------------
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
rst_sys_n_i : in std_logic;
rst_txclk_n_i : in std_logic;
rst_rxclk_n_i : in std_logic;
clk_sys_i : in std_logic;
---------------------------------------------------------------------------
-- PCS <-> MAC Interface
......@@ -199,6 +201,8 @@ end ep_1000basex_pcs;
architecture rtl of ep_1000basex_pcs is
alias rst_n_i : std_logic is rst_sys_n_i;
signal mdio_mcr_anrestart : std_logic;
signal mdio_mcr_pdown : std_logic;
signal mdio_mcr_pdown_cpu : std_logic;
......@@ -263,11 +267,14 @@ begin -- rtl
rst_n_i => pcs_reset_n,
clk_sys_i => clk_sys_i,
rst_txclk_n_i => rst_txclk_n_i,
pcs_fab_i => txpcs_fab_i,
pcs_error_o => txpcs_error_o,
pcs_busy_o => txpcs_busy_int,
pcs_dreq_o => txpcs_dreq_o,
mdio_mcr_reset_i => mdio_mcr_reset,
mdio_mcr_pdown_i => mdio_mcr_pdown,
mdio_wr_spec_tx_cal_i => mdio_wr_spec_tx_cal,
......@@ -292,6 +299,8 @@ begin -- rtl
clk_sys_i => clk_sys_i,
rst_n_i => pcs_reset_n,
rst_rxclk_n_i => rst_rxclk_n_i,
pcs_busy_o => rxpcs_busy_o,
pcs_fab_o => rxpcs_fab_o,
pcs_fifo_almostfull_i => rxpcs_fifo_almostfull_i,
......@@ -301,6 +310,7 @@ begin -- rtl
timestamp_valid_i => rxpcs_timestamp_valid_i,
timestamp_stb_i => rxpcs_timestamp_stb_i,
mdio_mcr_reset_i => mdio_mcr_reset,
mdio_mcr_pdown_i => mdio_mcr_pdown,
mdio_wr_spec_cal_crst_i => mdio_wr_spec_cal_crst,
mdio_wr_spec_rx_cal_stat_o => mdio_wr_spec_rx_cal_stat,
......@@ -335,11 +345,14 @@ begin -- rtl
rst_n_i => pcs_reset_n,
clk_sys_i => clk_sys_i,
rst_txclk_n_i => rst_txclk_n_i,
pcs_fab_i => txpcs_fab_i,
pcs_error_o => txpcs_error_o,
pcs_busy_o => txpcs_busy_int,
pcs_dreq_o => txpcs_dreq_o,
mdio_mcr_reset_i => mdio_mcr_reset,
mdio_mcr_pdown_i => mdio_mcr_pdown,
mdio_wr_spec_tx_cal_i => mdio_wr_spec_tx_cal,
......@@ -362,6 +375,8 @@ begin -- rtl
clk_sys_i => clk_sys_i,
rst_n_i => pcs_reset_n,
rst_rxclk_n_i => rst_rxclk_n_i,
pcs_busy_o => rxpcs_busy_o,
pcs_fab_o => rxpcs_fab_o,
pcs_fifo_almostfull_i => rxpcs_fifo_almostfull_i,
......@@ -371,6 +386,7 @@ begin -- rtl
timestamp_valid_i => rxpcs_timestamp_valid_i,
timestamp_stb_i => rxpcs_timestamp_stb_i,
mdio_mcr_reset_i => mdio_mcr_reset,
mdio_mcr_pdown_i => mdio_mcr_pdown,
mdio_wr_spec_cal_crst_i => mdio_wr_spec_cal_crst,
mdio_wr_spec_rx_cal_stat_o => mdio_wr_spec_rx_cal_stat,
......@@ -517,7 +533,7 @@ begin -- rtl
-- process: handles the LSTATUS bit in MSR register
-- inputs: sync_lost, synced, lstat_read_notify
-- outputs: mdio_msr_lstatus
p_gen_link_status : process(clk_sys_i, pcs_reset_n)
p_gen_link_status : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if(pcs_reset_n = '0') then
......
modules/wr_endpoint/ep_autonegotiation.vhd
View file @ 51164104
......@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-11-18
-- Last update: 2011-10-18
-- Last update: 2017-02-21
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -126,7 +126,7 @@ begin -- syn
-- process: link timer (counts until MSB of link_timer == 1).
-- inputs: link_timer_restart
-- outputs: link_timer_expired
p_link_timer : process(clk_sys_i, rst_n_i)
p_link_timer : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' or link_timer_restart ='1' then
......@@ -163,7 +163,7 @@ begin -- syn
-- process: main auto-negotiation state machine. More or less compatible with
-- IEEE 802.3.
p_autonegotation_fsm : process(clk_sys_i, rst_n_i)
p_autonegotation_fsm : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
......
modules/wr_endpoint/ep_rx_pcs_16bit.vhd
View file @ 51164104
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2009-06-16
-- Last update: 2012-07-03
-- Last update: 2017-02-20
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -17,7 +17,7 @@
-- It also generates deterministic timestamping pulses for RXed packets.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011 Tomasz Wlostowski / CERN
-- Copyright (c) 2011-2017 Tomasz Wlostowski / CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
......@@ -60,6 +60,9 @@ entity ep_rx_pcs_16bit is
-- reset (refclk2-synchronous)
rst_n_i : in std_logic;
-- reset (phy_rx_clk_i sync)
rst_rxclk_n_i : in std_logic;
pcs_fifo_almostfull_i : in std_logic;
-- RX path busy indicator (active HI).
-- When asserted, the receiver is in the middle of reception of a frame
......@@ -88,6 +91,7 @@ entity ep_rx_pcs_16bit is
-------------------------------------------------------------------------------
-- Receive control regsiter
mdio_mcr_reset_i : in std_logic;
mdio_mcr_pdown_i : in std_logic;
mdio_wr_spec_cal_crst_i : in std_logic;
mdio_wr_spec_rx_cal_stat_o : out std_logic;
......@@ -156,7 +160,6 @@ architecture behavioral of ep_rx_pcs_16bit is
cal_i : in std_logic);
end component;
signal reset_synced_rxclk : std_logic;
signal rst_n_rx : std_logic;
signal rx_state : t_tbif_rx_state;
......@@ -199,6 +202,7 @@ architecture behavioral of ep_rx_pcs_16bit is
-- Misc. signals
signal cal_pattern_cntr : unsigned(c_cal_pattern_counter_bits-1 downto 0);
signal mdio_mcr_reset_synced : std_logic;
signal mdio_mcr_pdown_synced : std_logic;
......@@ -221,25 +225,25 @@ begin
npulse_o => open,
ppulse_o => open);
U_sync_rx_reset : gc_sync_ffs
U_sync_an_rx_enable : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => phy_rx_clk_i,
rst_n_i => '1',
data_i => rst_n_i,
synced_o => reset_synced_rxclk,
rst_n_i => rst_n_rx,
data_i => an_rx_en_i,
synced_o => an_rx_en_synced,
npulse_o => open,
ppulse_o => open);
U_sync_an_rx_enable : gc_sync_ffs
U_sync_mcr_reset : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => phy_rx_clk_i,
rst_n_i => rst_n_rx,
data_i => an_rx_en_i,
synced_o => an_rx_en_synced,
rst_n_i => '1',
data_i => mdio_mcr_reset_i,
synced_o => mdio_mcr_reset_synced,
npulse_o => open,
ppulse_o => open);
......@@ -255,7 +259,7 @@ begin
ppulse_o => open);
rx_sync_enable <= not mdio_mcr_pdown_synced;
rst_n_rx <= reset_synced_rxclk and phy_rdy_i;
rst_n_rx <= rst_rxclk_n_i and not mdio_mcr_reset_synced and phy_rdy_i;
-------------------------------------------------------------------------------
-- 802.3z Link Synchronization State Machine
......@@ -297,7 +301,7 @@ begin
-- reads: phy_rx_data_i, mdio_wr_spec_cal_crst_i
-- writes: mdio_wr_spec_rx_cal_stat_o
--
p_detect_cal : process(phy_rx_clk_i, rst_n_rx)
p_detect_cal : process(phy_rx_clk_i)
begin
if rising_edge(phy_rx_clk_i) then
if rst_n_rx = '0' then
......@@ -334,7 +338,7 @@ begin
-- process postprocesses the raw 8b10b decoder output (phy_rx_data_i, phy_rx_k_i, phy_rx_enc_err_ior)
-- providing 1-bit signals indicating various 8b10b control patterns
p_8b10b_postprocess : process(phy_rx_clk_i, rst_n_rx)
p_8b10b_postprocess : process(phy_rx_clk_i)
begin
if rising_edge(phy_rx_clk_i) then
......@@ -422,7 +426,7 @@ begin
-- writes: almost everything
rx_fsm : process (phy_rx_clk_i, rst_n_rx)
rx_fsm : process (phy_rx_clk_i)
begin
if rising_edge(phy_rx_clk_i) then
-- reset or PCS disabled
......
modules/wr_endpoint/ep_rx_pcs_8bit.vhd
View file @ 51164104
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2009-06-16
-- Last update: 2017-02-02
-- Last update: 2017-02-20
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -17,7 +17,7 @@
-- pulses for RXed packets.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2009 Tomasz Wlostowski / CERN
-- Copyright (c) 2009-2017 Tomasz Wlostowski / CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
......@@ -65,6 +65,9 @@ entity ep_rx_pcs_8bit is
-- reset (refclk2-synchronous)
rst_n_i : in std_logic;
-- reset (phy_rx_clk_i sync)
rst_rxclk_n_i : in std_logic;
pcs_fifo_almostfull_i : in std_logic;
-- RX path busy indicator (active HI).
-- When asserted, the receiver is in the middle of reception of a frame
......@@ -94,6 +97,7 @@ entity ep_rx_pcs_8bit is
-------------------------------------------------------------------------------
-- Receive control regsiter
mdio_mcr_reset_i : in std_logic;
mdio_mcr_pdown_i : in std_logic;
mdio_wr_spec_cal_crst_i : in std_logic;
mdio_wr_spec_rx_cal_stat_o : out std_logic;
......@@ -152,7 +156,6 @@ architecture behavioral of ep_rx_pcs_8bit is
cal_i : in std_logic);
end component;
signal reset_synced_rxclk : std_logic;
signal rst_n_rx : std_logic;
signal rx_state : t_tbif_rx_state;
......@@ -205,6 +208,7 @@ architecture behavioral of ep_rx_pcs_8bit is
-- Misc. signals
signal cal_pattern_cntr : unsigned(c_cal_pattern_counter_bits-1 downto 0);
signal mdio_mcr_reset_synced : std_logic;
signal mdio_mcr_pdown_synced : std_logic;
......@@ -227,25 +231,25 @@ begin
npulse_o => open,
ppulse_o => open);
U_sync_rx_reset : gc_sync_ffs
U_sync_an_rx_enable : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => phy_rx_clk_i,
rst_n_i => '1',
data_i => rst_n_i,
synced_o => reset_synced_rxclk,
rst_n_i => rst_n_rx,
data_i => an_rx_en_i,
synced_o => an_rx_en_synced,
npulse_o => open,
ppulse_o => open);
U_sync_an_rx_enable : gc_sync_ffs
U_sync_mcr_reset : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => phy_rx_clk_i,
rst_n_i => rst_n_rx,
data_i => an_rx_en_i,
synced_o => an_rx_en_synced,
rst_n_i => '1',
data_i => mdio_mcr_reset_i,
synced_o => mdio_mcr_reset_synced,
npulse_o => open,
ppulse_o => open);
......@@ -261,7 +265,7 @@ begin
ppulse_o => open);
rx_sync_enable <= not mdio_mcr_pdown_synced;
rst_n_rx <= reset_synced_rxclk and phy_rdy_i;
rst_n_rx <= rst_rxclk_n_i and not mdio_mcr_reset_synced and phy_rdy_i;
-------------------------------------------------------------------------------
-- 802.3z Link Synchronization State Machine
......@@ -304,7 +308,7 @@ begin
-- reads: phy_rx_data_i, mdio_wr_spec_cal_crst_i
-- writes: mdio_wr_spec_rx_cal_stat_o
--
p_detect_cal : process(phy_rx_clk_i, rst_n_rx)
p_detect_cal : process(phy_rx_clk_i)
begin
if rising_edge(phy_rx_clk_i) then
if rst_n_rx = '0' then
......@@ -359,7 +363,7 @@ begin
-- process postprocesses the raw 8b10b decoder output (phy_rx_data_i, phy_rx_k_i, phy_rx_enc_err_ior)
-- providing 1-bit signals indicating various 8b10b control patterns
p_8b10b_postprocess : process(phy_rx_clk_i, rst_n_rx)
p_8b10b_postprocess : process(phy_rx_clk_i)
begin
if rising_edge(phy_rx_clk_i) then
......@@ -458,7 +462,7 @@ begin
-- reads: almost everything
-- writes: almost everything
rx_fsm : process (phy_rx_clk_i, rst_n_rx)
rx_fsm : process (phy_rx_clk_i)
begin
if rising_edge(phy_rx_clk_i) then
-- reset or PCS disabled
......
modules/wr_endpoint/ep_tx_pcs_16bit.vhd
View file @ 51164104
......@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT section
-- Created : 2009-06-16
-- Last update: 2017-02-02
-- Last update: 2017-02-20
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -21,7 +21,7 @@
-- exchange between these clock domains is done using an async FIFO.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011 CERN / BE-CO-HT
-- Copyright (c) 2011-2017 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
......@@ -65,6 +65,9 @@ entity ep_tx_pcs_16bit is
-- system clock (faster than reference)
clk_sys_i : in std_logic;
-- reset (phy_tx_clk_i sync)
rst_txclk_n_i : in std_logic;
-------------------------------------------------------------------------------
-- TX Framer inteface
-------------------------------------------------------------------------------
......@@ -85,6 +88,7 @@ entity ep_tx_pcs_16bit is
-- WB controller control signals
-------------------------------------------------------------------------------
mdio_mcr_reset_i : in std_logic;
-- Transmit Control Register, EN_PCS field
mdio_mcr_pdown_i : in std_logic;
-- Transmit Control Register, TX_CAL field
......@@ -144,10 +148,11 @@ architecture behavioral of ep_tx_pcs_16bit is
signal fifo_read_int : std_logic;
signal fifo_fab : t_ep_internal_fabric;
signal tx_busy : std_logic;
signal tx_error : std_logic;
signal reset_synced_txclk : std_logic;
signal tx_busy : std_logic;
signal tx_error : std_logic;
signal rst_n_tx : std_logic;
signal mdio_mcr_reset_synced : std_logic;
signal mdio_mcr_pdown_synced : std_logic;
signal an_tx_en_synced : std_logic;
......@@ -167,15 +172,6 @@ architecture behavioral of ep_tx_pcs_16bit is
--
begin
U_sync_an_tx_en : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => phy_tx_clk_i,
rst_n_i => rst_n_i,
data_i => an_tx_en_i,
synced_o => an_tx_en_synced);
U_sync_pcs_busy_o : gc_sync_ffs
generic map (
g_sync_edge => "positive")
......@@ -194,14 +190,25 @@ begin
data_i => tx_error,
ppulse_o => pcs_error_o);
U_sync_tx_reset : gc_sync_ffs
U_sync_an_tx_en : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => phy_tx_clk_i,
rst_n_i => rst_n_i,
data_i => an_tx_en_i,
synced_o => an_tx_en_synced);
U_sync_mcr_reset : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => phy_tx_clk_i,
rst_n_i => '1',
data_i => rst_n_i,
synced_o => reset_synced_txclk);
data_i => mdio_mcr_reset_i,
synced_o => mdio_mcr_reset_synced,
npulse_o => open,
ppulse_o => open);
U_sync_power_down : gc_sync_ffs
generic map (
......@@ -215,6 +222,8 @@ begin
phy_tx_data_o <= tx_odata_reg;
phy_tx_k_o <= tx_is_k;
rst_n_tx <= rst_txclk_n_i and not mdio_mcr_reset_synced;
-------------------------------------------------------------------------------
-- Clock alignment FIFO
-------------------------------------------------------------------------------
......@@ -314,7 +323,7 @@ begin
if rising_edge(phy_tx_clk_i) then
-- The PCS is reset or disabled
if(reset_synced_txclk = '0' or mdio_mcr_pdown_synced = '1') then
if(rst_n_tx = '0' or mdio_mcr_pdown_synced = '1') then
tx_state <= TX_COMMA_IDLE;
timestamp_trigger_p_a_o <= '0';
fifo_rd <= '0';
......
modules/wr_endpoint/ep_tx_pcs_8bit.vhd
View file @ 51164104
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT section
-- Created : 2009-06-16
-- Last update: 2017-02-03
-- Last update: 2017-02-20
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -23,22 +23,22 @@
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2009 Tomasz Wlostowski / CERN
-- Copyright (c) 2009-2017 Tomasz Wlostowski / CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
......@@ -72,9 +72,12 @@ entity ep_tx_pcs_8bit is
-- 62.5 MHz clock (refclk/2)
clk_sys_i : in std_logic;
-- reset (phy_tx_clk_i sync)
rst_txclk_n_i : in std_logic;
-------------------------------------------------------------------------------
-- TX Framer inteface
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- TX Fabric input
pcs_fab_i : in t_ep_internal_fabric;
......@@ -92,6 +95,7 @@ entity ep_tx_pcs_8bit is
-- WB controller control signals
-------------------------------------------------------------------------------
mdio_mcr_reset_i : in std_logic;
-- Transmit Control Register, EN_PCS field
mdio_mcr_pdown_i : in std_logic;
-- Transmit Control Register, TX_CAL field
......@@ -104,7 +108,7 @@ entity ep_tx_pcs_8bit is
-- Timestamp strobe
timestamp_trigger_p_a_o : out std_logic;
-- RMON events
-- RMON events
rmon_tx_underrun : out std_logic;
-------------------------------------------------------------------------------
......@@ -150,10 +154,11 @@ architecture behavioral of ep_tx_pcs_8bit is
signal tx_rdreq_toggle : std_logic;
signal tx_odd_length : std_logic;
signal tx_busy : std_logic;
signal tx_error : std_logic;
signal reset_synced_txclk : std_logic;
signal tx_busy : std_logic;
signal tx_error : std_logic;
signal rst_n_tx : std_logic;
signal mdio_mcr_reset_synced : std_logic;
signal mdio_mcr_pdown_synced : std_logic;
signal an_tx_en_synced : std_logic;
......@@ -177,39 +182,43 @@ begin
data_i => tx_error,
ppulse_o => pcs_error_o);
U_sync_tx_reset : gc_sync_ffs
U_sync_an_tx_en : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => phy_tx_clk_i,
rst_n_i => '1',
data_i => rst_n_i,
synced_o => reset_synced_txclk);
data_i => an_tx_en_i,
synced_o => an_tx_en_synced);
U_sync_power_down : gc_sync_ffs
U_sync_mcr_reset : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => phy_tx_clk_i,
rst_n_i => '1',
data_i => mdio_mcr_pdown_i,
synced_o => mdio_mcr_pdown_synced);
U_sync_tx_en : gc_sync_ffs
data_i => mdio_mcr_reset_i,
synced_o => mdio_mcr_reset_synced,
npulse_o => open,
ppulse_o => open);
U_sync_power_down : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => phy_tx_clk_i,
rst_n_i => '1',
data_i => an_tx_en_i,
synced_o => an_tx_en_synced);
data_i => mdio_mcr_pdown_i,
synced_o => mdio_mcr_pdown_synced);
phy_tx_data_o <= tx_odata_reg;
phy_tx_k_o <= tx_is_k;
rst_n_tx <= rst_txclk_n_i and not mdio_mcr_reset_synced;
-------------------------------------------------------------------------------
-- Clock alignment FIFO
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
fifo_clear_n <= '0' when (rst_n_i = '0') or (mdio_mcr_pdown_synced = '1') else '1';
......@@ -254,11 +263,11 @@ begin
p_tx_fsm : process (phy_tx_clk_i)
begin
if rising_edge(phy_tx_clk_i) then
-- The PCS is reset or disabled
if(reset_synced_txclk = '0' or mdio_mcr_pdown_synced = '1') then
if(rst_n_tx = '0' or mdio_mcr_pdown_synced = '1') then
tx_state <= TX_COMMA;
timestamp_trigger_p_a_o <= '0';
fifo_rd <= '0';
......@@ -271,14 +280,14 @@ begin
tx_odd_length <= '0';
tx_rdreq_toggle <= '0';
rmon_tx_underrun <= '0';
else
case tx_state is
-------------------------------------------------------------------------------
-- State COMMA: sends K28.5 comma character (first byte of /I/ sequence)
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
when TX_COMMA =>
tx_is_k <= '1';
tx_odata_reg <= c_K28_5;
......@@ -354,7 +363,7 @@ begin
-------------------------------------------------------------------------------
-- States: CR1, CR2, CR3, CR4: send the /C/ Configuration code set
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
when TX_CR1 =>
tx_is_k <= '1';
......@@ -411,7 +420,7 @@ begin
-------------------------------------------------------------------------------
-- State SFD: outputs the start-of-frame delimeter (last byte of the preamble)
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
when TX_SFD =>
tx_odata_reg <= c_preamble_sfd;
......@@ -455,7 +464,7 @@ begin
-------------------------------------------------------------------------------
-- State EPD: send End-of-frame delimeter
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
when TX_EPD =>
timestamp_trigger_p_a_o <= '0';
......@@ -479,7 +488,7 @@ begin
-------------------------------------------------------------------------------
-- State GEN_ERROR: entered when an error occured. Just terminates the frame.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
when TX_GEN_ERROR =>
tx_state <= TX_EPD;
......@@ -503,5 +512,3 @@ begin
pcs_dreq_o <= not fifo_almost_full;
end behavioral;
modules/wr_endpoint/wr_endpoint.vhd
View file @ 51164104
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-04-26
-- Last update: 2017-02-16
-- Last update: 2017-02-20
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -91,8 +91,12 @@ entity wr_endpoint is
-- DMTD offset clock for phase tracking - used only if g_with_dmtd == true
clk_dmtd_i : in std_logic;
-- sync reset (clk_sys_i domain), active LO
rst_n_i : in std_logic;
-- resets for various clock domains
rst_sys_n_i : in std_logic;
rst_ref_n_i : in std_logic;
rst_dmtd_n_i : in std_logic;
rst_txclk_n_i : in std_logic;
rst_rxclk_n_i : in std_logic;
-- PPS input (1 clk_ref_i cycle HI) for synchronizing timestamp counter
pps_csync_p1_i : in std_logic;
......@@ -312,7 +316,8 @@ architecture syn of wr_endpoint is
g_deglitcher_threshold : integer;
g_counter_bits : integer);
port (
rst_n_i : in std_logic;
rst_sys_n_i : in std_logic;
rst_dmtd_n_i : in std_logic;
clk_sys_i : in std_logic;
clk_a_i : in std_logic;
clk_b_i : in std_logic;
......@@ -396,7 +401,6 @@ architecture syn of wr_endpoint is
signal src_in : t_wrf_source_in;
signal src_out : t_wrf_source_out;
signal rst_n_rxsync, rst_n_sys, rst_n_ref : std_logic;
signal rst_n_rx : std_logic;
signal wb_in : t_wishbone_slave_in;
......@@ -453,26 +457,7 @@ architecture syn of wr_endpoint is
begin
-----------------------------------------------------------------------------
-- Reset signal synchronization
-----------------------------------------------------------------------------
U_Sync_Rst_RX : gc_sync_ffs
port map (
clk_i => phy_rx_clk_i,
rst_n_i => '1',
data_i => rst_n_i,
synced_o => rst_n_rxsync);
U_Sync_Rst_REF : gc_sync_ffs
port map (
clk_i => clk_ref_i,
rst_n_i => '1',
data_i => rst_n_i,
synced_o => rst_n_ref);
rst_n_sys <= rst_n_i;
rst_n_rx <= rst_n_rxsync and phy_rdy_i;
rst_n_rx <= rst_rxclk_n_i and phy_rdy_i;
-------------------------------------------------------------------------------
-- 1000Base-X PCS
......@@ -485,8 +470,10 @@ begin
g_simulation => g_simulation,
g_16bit => g_pcs_16bit)
port map (
rst_n_i => rst_n_i,
clk_sys_i => clk_sys_i,
rst_sys_n_i => rst_sys_n_i,
rst_rxclk_n_i => rst_rxclk_n_i,
rst_txclk_n_i => rst_txclk_n_i,
clk_sys_i => clk_sys_i,
rxpcs_fab_o => rxpcs_fab,
rxpcs_busy_o => rxpcs_busy,
......@@ -558,7 +545,7 @@ begin
g_use_new_crc => g_use_new_txcrc)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
rst_n_i => rst_sys_n_i,
pcs_error_i => txpcs_error,
pcs_busy_i => txpcs_busy,
pcs_fab_o => txpcs_fab,
......@@ -619,7 +606,7 @@ begin
clk_sys_i => clk_sys_i,
clk_rx_i => phy_rx_clk_i,
rst_n_sys_i => rst_n_sys,
rst_n_sys_i => rst_sys_n_i,
rst_n_rx_i => rst_n_rx,
pcs_fab_i => rxpath_fab,
......@@ -707,9 +694,9 @@ begin
clk_ref_i => clk_ref_i,
clk_rx_i => phy_rx_clk_i,
clk_sys_i => clk_sys_i,
rst_n_rx_i => rst_n_rxsync,
rst_n_sys_i => rst_n_sys,
rst_n_ref_i => rst_n_ref,
rst_n_rx_i => rst_rxclk_n_i,
rst_n_sys_i => rst_sys_n_i,
rst_n_ref_i => rst_ref_n_i,
pps_csync_p1_i => pps_csync_p1_i,
pps_valid_i => pps_valid_i,
......@@ -743,7 +730,7 @@ begin
g_slave_granularity => g_address_granularity)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_sys,
rst_n_i => rst_sys_n_i,
sl_adr_i => extended_ADDR,
sl_dat_i => wb_dat_i,
sl_sel_i => wb_sel_i,
......@@ -758,7 +745,7 @@ begin
U_WB_SLAVE : ep_wishbone_controller
port map (
rst_n_i => rst_n_sys,
rst_n_i => rst_sys_n_i,
clk_sys_i => clk_sys_i,
wb_adr_i => wb_in.adr(4 downto 0),
wb_dat_i => wb_in.dat,
......@@ -789,7 +776,7 @@ begin
begin
if rising_edge(clk_sys_i) then
if(rst_n_i = '0') or
if(rst_sys_n_i = '0') or
(regs_fromwb.dsr_lact_o = '1' and regs_fromwb.dsr_lact_load_o = '1') then
regs_towb_ep.dsr_lact_i <= '0';
else
......@@ -831,7 +818,9 @@ begin
clk_a_i => phy_ref_clk_i,
clk_b_i => phy_rx_clk_i,
clk_dmtd_i => clk_dmtd_i,
rst_n_i => rst_n_i,
rst_sys_n_i => rst_sys_n_i,
rst_dmtd_n_i => rst_dmtd_n_i,
en_i => r_dmcr_en,
navg_i => r_dmcr_n_avg,
......@@ -846,7 +835,7 @@ begin
p_dmtd_update : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
if rst_sys_n_i = '0' then
validity_cntr <= (others => '0');
regs_towb_ep.dmsr_ps_rdy_i <= '0';
else
......@@ -892,7 +881,7 @@ begin
g_blink_period_log2 => 22)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
rst_n_i => rst_sys_n_i,
dvalid_tx_i => dvalid_tx,
dvalid_rx_i => dvalid_rx,
link_ok_i => link_ok,
......@@ -915,7 +904,7 @@ begin
p_ep_ctrl : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
if rst_sys_n_i = '0' then
ep_ctrl <= '1';
else
ep_ctrl <= not link_kill_i;
......@@ -960,7 +949,7 @@ begin
g_sync_edge => "negative")
port map (
clk_i => clk_sys_i,
rst_n_i => rst_n_i,
rst_n_i => rst_sys_n_i,
data_i => txpcs_timestamp_trigger_p_a,
synced_o => open,
npulse_o => open,
......@@ -971,7 +960,7 @@ begin
g_sync_edge => "negative")
port map (
clk_i => clk_sys_i,
rst_n_i => rst_n_i,
rst_n_i => rst_sys_n_i,
data_i => rxpcs_timestamp_trigger_p_a,
synced_o => open,
npulse_o => open,
......
modules/wr_endpoint/xwr_endpoint.vhd
View file @ 51164104
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-04-26
-- Last update: 2017-02-16
-- Last update: 2017-02-20
-- Platform : FPGA-generic
-- Standard : VHDL '93
-------------------------------------------------------------------------------
......@@ -81,8 +81,12 @@ entity xwr_endpoint is
clk_dmtd_i : in std_logic := '0';
-- sync reset (clk_sys_i domain), active LO
rst_n_i : in std_logic;
-- resets for various clock domains
rst_sys_n_i : in std_logic;
rst_ref_n_i : in std_logic;
rst_dmtd_n_i : in std_logic;
rst_txclk_n_i : in std_logic;
rst_rxclk_n_i : in std_logic;
-- PPS input (1 clk_ref_i cycle HI) for synchronizing timestamp counter
pps_csync_p1_i : in std_logic := '0';
......@@ -317,7 +321,11 @@ begin
clk_ref_i => clk_ref_i,
clk_sys_i => clk_sys_i,
clk_dmtd_i => clk_dmtd_i,
rst_n_i => rst_n_i,
rst_sys_n_i => rst_sys_n_i,
rst_ref_n_i => rst_ref_n_i,
rst_dmtd_n_i => rst_dmtd_n_i,
rst_txclk_n_i => rst_txclk_n_i,
rst_rxclk_n_i => rst_rxclk_n_i,
pps_csync_p1_i => pps_csync_p1_i,
pps_valid_i => pps_valid_i,
......
modules/wr_pps_gen/wr_pps_gen.vhd
View file @ 51164104
......@@ -4,15 +4,15 @@
-------------------------------------------------------------------------------
-- File : wrsw_pps_gen.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Company : CERN (BE-CO-HT)
-- Created : 2010-09-02
-- Last update: 2017-02-13
-- Last update: 2017-02-20
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2010 Tomasz Wlostowski
-- Copyright (c) 2010-2017 CERN
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
......@@ -39,11 +39,10 @@ entity wr_pps_gen is
g_with_ext_clock_input : boolean := false
);
port (
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
clk_ext_i : in std_logic := '0';
rst_n_i : in std_logic;
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
rst_ref_n_i : in std_logic;
rst_sys_n_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
......@@ -79,6 +78,8 @@ end wr_pps_gen;
architecture behavioral of wr_pps_gen is
alias rst_n_i : std_logic is rst_sys_n_i;
constant c_PERIOD : integer := g_ref_clock_rate;
component pps_gen_wb is
......@@ -163,8 +164,6 @@ architecture behavioral of wr_pps_gen is
signal adj_nsec : unsigned(27 downto 0);
signal adj_utc : unsigned(39 downto 0);
signal rst_synced_refclk : std_logic;
signal adjust_in_progress_nsec : std_logic;
signal adjust_in_progress_utc : std_logic;
......@@ -219,17 +218,6 @@ begin -- behavioral
sl_stall_o => wb_stall_o);
U_Sync_reset_refclk : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => clk_ref_i,
rst_n_i => '1',
data_i => rst_n_i,
synced_o => rst_synced_refclk,
npulse_o => open,
ppulse_o => open);
U_Sync_pps_refclk : gc_sync_ffs
generic map (
g_sync_edge => "positive")
......@@ -277,7 +265,7 @@ begin -- behavioral
p_external_sync : process(clk_ref_i)
begin
if falling_edge(clk_ref_i) then
if(rst_synced_refclk = '0') then
if(rst_ref_n_i = '0') then
sync_in_progress <= '0';
ppsg_escr_sync_in <= '0';
else
......@@ -301,10 +289,10 @@ begin -- behavioral
end generate gen_with_external_clock_input;
-- Nanosecond counter. Counts from 0 to c_PERIOD-1 every clk_ref_i cycle.
p_count_nsec : process(clk_ref_i, rst_synced_refclk)
p_count_nsec : process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
if rst_synced_refclk = '0' or ppsg_cr_cnt_rst = '1' then
if rst_ref_n_i = '0' or ppsg_cr_cnt_rst = '1' then
cntr_nsec <= (others => '0');
ns_overflow <= '0';
ns_overflow_adv <= '0';
......@@ -361,7 +349,7 @@ begin -- behavioral
p_drive_pps_valid : process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
if rst_synced_refclk = '0' or ppsg_cr_cnt_rst = '1' then
if rst_ref_n_i = '0' or ppsg_cr_cnt_rst = '1' then
pps_valid_int <= '0';
ns_overflow_2nd <= '0';
else
......@@ -381,10 +369,10 @@ begin -- behavioral
end if;
end process;
p_count_utc : process(clk_ref_i, rst_synced_refclk)
p_count_utc : process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
if rst_synced_refclk = '0' or ppsg_cr_cnt_rst = '1' then
if rst_ref_n_i = '0' or ppsg_cr_cnt_rst = '1' then
cntr_utc <= (others => '0');
adjust_in_progress_utc <= '0';
elsif(ppsg_cr_cnt_en = '1') then
......@@ -412,10 +400,10 @@ begin -- behavioral
pps_csync_o <= ns_overflow;
-- generates variable-width PPS pulses for PPS external output
p_gen_pps_out : process(clk_ref_i, rst_synced_refclk)
p_gen_pps_out : process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
if rst_synced_refclk = '0' then
if rst_ref_n_i = '0' then
pps_out_int <= '0';
pps_led_o <= '0';
width_cntr <= (others => '0');
......@@ -440,10 +428,10 @@ begin -- behavioral
end process;
process(clk_ref_i, rst_synced_refclk)
process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
if rst_synced_refclk = '0' then
if rst_ref_n_i = '0' then
pps_out_o <= '0';
else
pps_out_o <= pps_out_int;
......
modules/wr_pps_gen/xwr_pps_gen.vhd
View file @ 51164104
......@@ -4,15 +4,15 @@
-------------------------------------------------------------------------------
-- File : xwb_pps_gen.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Company : CERN (BE-CO-HT)
-- Created : 2010-09-02
-- Last update: 2017-02-13
-- Last update: 2017-02-20
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2010 Tomasz Wlostowski
-- Copyright (c) 2010-2017 CERN
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
......@@ -38,10 +38,10 @@ entity xwr_pps_gen is
g_with_ext_clock_input : boolean := FALSE
);
port (
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
clk_ext_i : in std_logic := '0';
rst_n_i : in std_logic;
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
rst_ref_n_i : in std_logic;
rst_sys_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
......@@ -77,8 +77,8 @@ architecture behavioral of xwr_pps_gen is
port (
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
clk_ext_i : in std_logic;
rst_n_i : in std_logic;
rst_ref_n_i : in std_logic;
rst_sys_n_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
......@@ -114,8 +114,8 @@ begin -- behavioral
port map(
clk_ref_i => clk_ref_i,
clk_sys_i => clk_sys_i,
clk_ext_i => clk_ext_i,
rst_n_i => rst_n_i,
rst_ref_n_i => rst_ref_n_i,
rst_sys_n_i => rst_sys_n_i,
wb_adr_i => slave_i.adr(4 downto 0),
wb_dat_i => slave_i.dat,
wb_dat_o => slave_o.dat,
......
modules/wr_softpll_ng/spll_aligner.vhd
View file @ 51164104
......@@ -16,7 +16,9 @@ entity spll_aligner is
clk_in_i : in std_logic;
clk_ref_i : in std_logic;
rst_n_sys_i : in std_logic;
rst_n_sys_i : in std_logic;
rst_n_ref_i : in std_logic;
rst_n_ext_i : in std_logic;
pps_ext_a_i : in std_logic;
pps_csync_p1_i : in std_logic;
......@@ -38,29 +40,14 @@ architecture rtl of spll_aligner is
signal cnt_ref_div : unsigned(g_counter_width-1 downto 0);
signal pps_ext_p, pps_ext_d0 : std_logic;
signal rst_n_in, rst_n_ref : std_logic;
signal ref_div_p : std_logic;
signal sample_ready_p : std_logic;
begin
U_Reset_IN : gc_sync_ffs
port map (
clk_i => clk_in_i,
rst_n_i => '1',
data_i => rst_n_sys_i,
synced_o => rst_n_in);
U_Reset_REF : gc_sync_ffs
port map (
clk_i => clk_ref_i,
rst_n_i => '1',
data_i => rst_n_sys_i,
synced_o => rst_n_ref);
p_ref_counter : process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
if pps_csync_p1_i = '1' or rst_n_ref = '0' then
if pps_csync_p1_i = '1' or rst_n_ref_i = '0' then
cnt_ref_bin <= to_unsigned(0, g_counter_width);
elsif(cnt_ref_bin = g_ref_clock_rate - 1) then
cnt_ref_bin <= (others => '0');
......@@ -73,7 +60,7 @@ begin
p_samplerate_divider : process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
if pps_csync_p1_i = '1' or rst_n_ref = '0' then
if pps_csync_p1_i = '1' or rst_n_ref_i = '0' then
ref_div_p <= '0';
cnt_ref_div <= to_unsigned(0, g_counter_width);
elsif (cnt_ref_div = c_div_ticks - 2) then
......@@ -101,7 +88,7 @@ begin
p_in_counter : process(clk_in_i)
begin
if rising_edge(clk_in_i) then
if pps_ext_p = '1' or rst_n_in = '0' then
if pps_ext_p = '1' or rst_n_ext_i = '0' then
cnt_in_bin <= to_unsigned(2, g_counter_width);
elsif(cnt_in_bin = g_in_clock_rate - 1) then
cnt_in_bin <= (others => '0');
......@@ -134,7 +121,7 @@ begin
U_sync_sampling : gc_pulse_synchronizer2
port map (
clk_in_i => clk_ref_i,
rst_in_n_i => rst_n_ref,
rst_in_n_i => rst_n_ref_i,
clk_out_i => clk_sys_i,
rst_out_n_i => rst_n_sys_i,
d_p_i => ref_div_p,
......
modules/wr_softpll_ng/wr_softpll_ng.vhd
View file @ 51164104
......@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-29
-- Last update: 2017-02-03
-- Last update: 2017-02-20
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -90,8 +90,11 @@ entity wr_softpll_ng is
);
port(
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
rst_sys_n_i : in std_logic;
rst_ref_n_i : in std_logic;
rst_ext_n_i : in std_logic;
rst_dmtd_n_i : in std_logic;
-- Reference inputs (i.e. the RX clocks recovered by the PHYs)
clk_ref_i : in std_logic_vector(g_num_ref_inputs-1 downto 0);
......@@ -157,6 +160,8 @@ end wr_softpll_ng;
architecture rtl of wr_softpll_ng is
alias rst_n_i : std_logic is rst_sys_n_i;
constant c_log2_replication : integer := 2;
constant c_use_multi_dmtd : boolean := false;
......@@ -221,6 +226,8 @@ architecture rtl of wr_softpll_ng is
clk_in_i : in std_logic;
clk_ref_i : in std_logic;
rst_n_sys_i : in std_logic;
rst_n_ref_i : in std_logic;
rst_n_ext_i : in std_logic;
pps_ext_a_i : in std_logic;
pps_csync_p1_i : in std_logic;
sample_cref_o : out std_logic_vector(g_counter_width-1 downto 0);
......@@ -387,23 +394,13 @@ begin -- rtl
gen_ref_dmtds : for i in 0 to g_num_ref_inputs-1 generate
U_sync_rst_dmtd_ref : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => clk_dmtd_i,
rst_n_i => '1',
data_i => rst_n_i,
synced_o => rst_n_dmtd_ref_clk(i));
DMTD_REF : dmtd_with_deglitcher
generic map (
g_counter_bits => g_tag_bits,
g_divide_input_by_2 => g_divide_input_by_2,
g_reverse => g_reverse_dmtds)
g_reverse => g_reverse_dmtds)
port map (
rst_n_dmtdclk_i => rst_n_dmtd_ref_clk(i),
rst_n_dmtdclk_i => rst_dmtd_n_i,
rst_n_sysclk_i => rst_n_i,
clk_dmtd_i => clk_dmtd_i,
......@@ -429,23 +426,13 @@ begin -- rtl
gen_feedback_dmtds : for i in 0 to g_num_outputs-1 generate
U_sync_rst_dmtd_fb : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => clk_dmtd_i,
rst_n_i => '1',
data_i => rst_n_i,
synced_o => rst_n_dmtd_fb_clk(i));
DMTD_FB : dmtd_with_deglitcher
generic map (
g_counter_bits => g_tag_bits,
g_divide_input_by_2 => g_divide_input_by_2,
g_reverse => g_reverse_dmtds)
g_reverse => g_reverse_dmtds)
port map (
rst_n_dmtdclk_i => rst_n_dmtd_fb_clk(i),
rst_n_dmtdclk_i => rst_dmtd_n_i,
rst_n_sysclk_i => rst_n_i,
clk_dmtd_i => clk_dmtd_i,
......@@ -484,9 +471,9 @@ begin -- rtl
generic map (
g_counter_bits => g_tag_bits,
g_divide_input_by_2 => g_divide_input_by_2,
g_reverse => g_reverse_dmtds)
g_reverse => g_reverse_dmtds)
port map (
rst_n_dmtdclk_i => rst_n_i, -- FIXME!
rst_n_dmtdclk_i => rst_dmtd_n_i,
rst_n_sysclk_i => rst_n_i,
clk_dmtd_i => clk_dmtd_i,
clk_dmtd_en_i => '1',
......@@ -519,6 +506,8 @@ begin -- rtl
clk_in_i => clk_ext_i,
clk_ref_i => clk_fb_i(0),
rst_n_sys_i => rst_n_i,
rst_n_ref_i => rst_ref_n_i,
rst_n_ext_i => rst_ext_n_i,
pps_ext_a_i => pps_ext_a_i,
pps_csync_p1_i => pps_csync_p1_i,
sample_cref_o => aligner_sample_cref(g_num_outputs),
......
modules/wr_softpll_ng/xwr_softpll_ng.vhd
View file @ 51164104
......@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-29
-- Last update: 2017-02-02
-- Last update: 2017-02-20
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -15,7 +15,7 @@
-- Struct'ized version of wr_softpll_ng.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012-2013 CERN
-- Copyright (c) 2012-2017 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
......@@ -83,9 +83,11 @@ entity xwr_softpll_ng is
);
port(
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
rst_sys_n_i : in std_logic;
rst_ref_n_i : in std_logic;
rst_ext_n_i : in std_logic;
rst_dmtd_n_i : in std_logic;
-- Reference inputs (i.e. the RX clocks recovered by the PHYs)
clk_ref_i : in std_logic_vector(g_num_ref_inputs-1 downto 0);
......@@ -148,7 +150,10 @@ architecture wrapper of xwr_softpll_ng is
g_address_granularity : t_wishbone_address_granularity);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
rst_sys_n_i : in std_logic;
rst_ref_n_i : in std_logic;
rst_ext_n_i : in std_logic;
rst_dmtd_n_i : in std_logic;
clk_ref_i : in std_logic_vector(g_num_ref_inputs-1 downto 0);
clk_fb_i : in std_logic_vector(g_num_outputs-1 downto 0);
clk_dmtd_i : in std_logic;
......@@ -199,7 +204,10 @@ begin -- behavioral
)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
rst_sys_n_i => rst_sys_n_i,
rst_ref_n_i => rst_ref_n_i,
rst_ext_n_i => rst_ext_n_i,
rst_dmtd_n_i => rst_dmtd_n_i,
clk_ref_i => clk_ref_i,
clk_fb_i => clk_fb_i,
clk_dmtd_i => clk_dmtd_i,
......
modules/wrc_core/wr_core.vhd
View file @ 51164104
......@@ -5,7 +5,7 @@
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-02-02
-- Last update: 2017-02-13
-- Last update: 2017-02-21
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -23,7 +23,7 @@
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011, 2012 Elproma Elektronika
-- Copyright (c) 2012, 2013 CERN
-- Copyright (c) 2012, 2017 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
......@@ -334,9 +334,21 @@ architecture struct of wr_core is
end if;
end function;
-----------------------------------------------------------------------------
--Local resets for peripheral
-----------------------------------------------------------------------------
signal rst_wrc_n : std_logic;
signal rst_net_n : std_logic;
-----------------------------------------------------------------------------
--Local resets (resynced)
-----------------------------------------------------------------------------
signal rst_net_resync_ref_n : std_logic;
signal rst_net_resync_ext_n : std_logic;
signal rst_net_resync_dmtd_n : std_logic;
signal rst_net_resync_rxclk_n : std_logic;
signal rst_net_resync_txclk_n : std_logic;
-----------------------------------------------------------------------------
--PPS generator
-----------------------------------------------------------------------------
......@@ -351,6 +363,7 @@ architecture struct of wr_core is
--Timing system
-----------------------------------------------------------------------------
signal phy_rx_clk : std_logic;
signal phy_tx_clk : std_logic;
signal spll_wb_in : t_wishbone_slave_in;
signal spll_wb_out : t_wishbone_slave_out;
......@@ -501,8 +514,76 @@ architecture struct of wr_core is
--signal TRIG3 : std_logic_vector(31 downto 0);
begin
-----------------------------------------------------------------------------
-- PHY TX/RX clock selection based on generics
-----------------------------------------------------------------------------
GEN_16BIT_PHY_IF: if g_pcs_16bit and g_records_for_phy generate
phy_rx_clk <= phy16_i.rx_clk;
phy_tx_clk <= phy16_i.ref_clk;
end generate;
GEN_8BIT_PHY_IF: if not g_pcs_16bit and g_records_for_phy generate
phy_rx_clk <= phy8_i.rx_clk;
phy_tx_clk <= phy8_i.ref_clk;
end generate;
GEN_STD_PHY_IF: if not g_records_for_phy generate
phy_rx_clk <= phy_rx_rbclk_i;
phy_tx_clk <= phy_ref_clk_i;
end generate;
-----------------------------------------------------------------------------
-- Reset resync and distribution
-----------------------------------------------------------------------------
rst_aux_n_o <= rst_net_n;
U_Sync_reset_refclk : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => clk_ref_i,
rst_n_i => '1',
data_i => rst_net_n,
synced_o => rst_net_resync_ref_n);
U_sync_reset_dmtd : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => clk_dmtd_i,
rst_n_i => '1',
data_i => rst_net_n,
synced_o => rst_net_resync_dmtd_n);
U_sync_reset_ext : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => clk_ext_i,
rst_n_i => '1',
data_i => rst_net_n,
synced_o => rst_net_resync_ext_n);
U_sync_reset_rxclk : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => phy_rx_clk,
rst_n_i => '1',
data_i => rst_net_n,
synced_o => rst_net_resync_rxclk_n);
U_sync_reset_txclk : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => phy_tx_clk,
rst_n_i => '1',
data_i => rst_net_n,
synced_o => rst_net_resync_txclk_n);
-----------------------------------------------------------------------------
-- PPS generator
-----------------------------------------------------------------------------
......@@ -516,9 +597,9 @@ begin
port map(
clk_ref_i => clk_ref_i,
clk_sys_i => clk_sys_i,
clk_ext_i => clk_ext_i,
rst_n_i => rst_net_n,
rst_sys_n_i => rst_net_n,
rst_ref_n_i => rst_net_resync_ref_n,
slave_i => ppsg_wb_in,
slave_o => ppsg_wb_out,
......@@ -542,18 +623,6 @@ begin
-----------------------------------------------------------------------------
-- Software PLL
-----------------------------------------------------------------------------
GEN_16BIT_PHY_IF: if g_pcs_16bit and g_records_for_phy generate
phy_rx_clk <= phy16_i.rx_clk;
end generate;
GEN_8BIT_PHY_IF: if not g_pcs_16bit and g_records_for_phy generate
phy_rx_clk <= phy8_i.rx_clk;
end generate;
GEN_STD_PHY_IF: if not g_records_for_phy generate
phy_rx_clk <= phy_rx_rbclk_i;
end generate;
U_SOFTPLL : xwr_softpll_ng
generic map(
g_with_ext_clock_input => g_with_external_clock_input,
......@@ -568,8 +637,11 @@ begin
g_ref_clock_rate => f_refclk_rate(g_pcs_16bit),
g_ext_clock_rate => 10000000)
port map(
clk_sys_i => clk_sys_i,
rst_n_i => rst_net_n,
clk_sys_i => clk_sys_i,
rst_sys_n_i => rst_net_n,
rst_ref_n_i => rst_net_resync_ref_n,
rst_ext_n_i => rst_net_resync_ext_n,
rst_dmtd_n_i => rst_net_resync_dmtd_n,
-- Reference inputs (i.e. the RX clocks recovered by the PHYs)
clk_ref_i(0) => phy_rx_clk,
......@@ -659,7 +731,11 @@ begin
clk_ref_i => clk_ref_i,
clk_sys_i => clk_sys_i,
clk_dmtd_i => clk_dmtd_i,
rst_n_i => rst_net_n,
rst_sys_n_i => rst_net_n,
rst_ref_n_i => rst_net_resync_ref_n,
rst_dmtd_n_i => rst_net_resync_dmtd_n,
rst_txclk_n_i => rst_net_resync_txclk_n,
rst_rxclk_n_i => rst_net_resync_rxclk_n,
pps_csync_p1_i => s_pps_csync,
pps_valid_i => pps_valid,
......
modules/wrc_core/wrcore_pkg.vhd
View file @ 51164104
......@@ -45,8 +45,8 @@ package wrcore_pkg is
port (
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
clk_ext_i : in std_logic := '0';
rst_n_i : in std_logic;
rst_ref_n_i : in std_logic;
rst_sys_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
link_ok_i : in std_logic;
......@@ -270,7 +270,10 @@ package wrcore_pkg is
g_address_granularity : t_wishbone_address_granularity);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
rst_sys_n_i : in std_logic;
rst_ref_n_i : in std_logic;
rst_ext_n_i : in std_logic;
rst_dmtd_n_i : in std_logic;
clk_ref_i : in std_logic_vector(g_num_ref_inputs-1 downto 0);
clk_fb_i : in std_logic_vector(g_num_outputs-1 downto 0);
clk_dmtd_i : in std_logic;
......
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