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White Rabbit core collection
Commit 522c6cbd authored by Peter Jansweijer's avatar Peter Jansweijer Committed by Grzegorz Daniluk
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clbv3 reference design files 

updates kintex7 phy name to reflect new peter_xilinx_phys convention
add clbv3 reference design files
last commit also needs artix7 support in xwrc_platform_xilinx.vhd
added BullsEye connections
CLBv3: moved dmtd div2 and buffer into xwrc_platform_xilinx.vhd
CLBv3: implementation files (including bmm)
CLBv3: Clean up

Conflicts:
	platform/xilinx/xwrc_platform_xilinx.vhd
parent d2f24245
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Showing with 3340 additions and 8 deletions
board/clbv3/Manifest.py 0 → 100644
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files = [
"wr_clbv3_pkg.vhd",
"xwrc_board_clbv3.vhd",
"wrc_board_clbv3.vhd",
]
modules = {
"local" : [
"../common",
]
}
board/clbv3/wr_clbv3_pkg.vhd 0 → 100644
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board/clbv3/wrc_board_clbv3.vhd 0 → 100644
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board/clbv3/xwrc_board_clbv3.vhd 0 → 100644
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platform/xilinx/wr_xilinx_pkg.vhd
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......@@ -21,6 +21,7 @@ package wr_xilinx_pkg is
clk_125m_gtp_n_i : in std_logic;
clk_20m_vcxo_i : in std_logic := '0';
clk_125m_pllref_i : in std_logic := '0';
clk_125m_dmtd_i : in std_logic := '0';
clk_62m5_dmtd_i : in std_logic := '0';
clk_dmtd_locked_i : in std_logic := '1';
clk_62m5_sys_i : in std_logic := '0';
......
platform/xilinx/xwrc_platform_xilinx.vhd
View file @ 522c6cbd
......@@ -85,8 +85,10 @@ entity xwrc_platform_xilinx is
---------------------------------------------------------------------------
-- 20MHz VCXO clock
clk_20m_vcxo_i : in std_logic := '0';
-- 125 MHz PLL reference
-- 125.000 MHz PLL reference
clk_125m_pllref_i : in std_logic := '0';
-- 124.992 MHz DMTD reference (CLBv3 reference design)
clk_125m_dmtd_i : in std_logic := '0';
---------------------------------------------------------------------------
-- Clock inputs from custom PLLs (g_use_default_plls = FALSE)
---------------------------------------------------------------------------
......@@ -151,7 +153,7 @@ begin -- architecture rtl
-----------------------------------------------------------------------------
-- Check for unsupported features and/or misconfiguration
-----------------------------------------------------------------------------
gen_unknown_fpga : if (g_fpga_family /= "spartan6" and g_fpga_family /= "kintex7") generate
gen_unknown_fpga : if (g_fpga_family /= "spartan6" and g_fpga_family /= "kintex7" and g_fpga_family /= "artix7") generate
assert FALSE
report "Xilinx FPGA family [" & g_fpga_family & "] is not supported"
severity ERROR;
......@@ -579,7 +581,7 @@ begin -- architecture rtl
signal clk_sys_out : std_logic;
signal clk_sys_fb : std_logic;
signal pll_sys_locked : std_logic;
-- signal clk_dmtd : std_logic;
signal clk_dmtd : std_logic := '0'; -- initialize for simulation
-- signal clk_dmtd_fb : std_logic;
-- signal pll_dmtd_locked : std_logic;
-- signal clk_20m_vcxo_buf : std_logic;
......@@ -701,11 +703,20 @@ begin -- architecture rtl
-- O => clk_20m_vcxo_buf,
-- I => clk_20m_vcxo_i);
--
-- -- DMTD PLL output clock buffer
-- cmp_clk_dmtd_buf_o : BUFG
-- port map (
-- O => clk_62m5_dmtd_o,
-- I => clk_dmtd);
-- DMTD Div2 (124.9920 MHz -> 62,496 MHz)
process(clk_125m_dmtd_i)
begin
if rising_edge(clk_125m_dmtd_i) then
clk_dmtd <= not clk_dmtd;
end if;
end process;
-- DMTD PLL output clock buffer
cmp_clk_dmtd_buf_o : BUFG
port map (
O => clk_62m5_dmtd_o,
I => clk_dmtd);
-- External 10MHz reference PLL for Artix7
gen_artix7_ext_ref_pll : if (g_with_external_clock_input = TRUE) generate
......
syn/clbv3_ref_design/Manifest.py 0 → 100644
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target = "xilinx"
action = "synthesis"
syn_device = "xc7a200t"
syn_grade = "-2"
syn_package = "fbg484"
syn_top = "clbv3_wr_ref_top"
syn_project = "clbv3_wr_ref.xise"
syn_tool = "ise"
modules = { "local" : "../../top/clbv3_ref_design/"}
syn/clbv3_ref_design/clbv3_wr_ref.xise.xise 0 → 100644
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top/clbv3_ref_design/Manifest.py 0 → 100644
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fetchto = "../../ip_cores"
files = [
"clbv3_wr_ref_top.vhd",
"clbv3_wr_ref_top.ucf",
"clbv3_wr_ref_top.bmm",
]
modules = {
"local" : [
"../../",
"../../board/clbv3",
],
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git",
"git://ohwr.org/hdl-core-lib/etherbone-core.git",
],
}
top/clbv3_ref_design/clbv3_wr_ref_top.bmm 0 → 100644
View file @ 522c6cbd
/* FILE : clbv3_wr_ref_top.bmm
* Define a BRAM map for the LM32 memory.
* Run ISE Translate -> "Floorplan Area/IO/Logic (PlanAhead)" once (without this BMM file
* attached to the ISE Project) to find out that there are 16 ramloops and each RAMB36E1
* Note: *THE RAMLOOP ORDER WITHIN A BUS_BLOCK IS VERY IMPORTANT!!!*
* Define ramloop 15 downto 0 and databits 31 downto 0 !!! Otherwise the memory
* content will be swapped and the program fails to execute. Aperently the ramloop
* number and bit definitions are not read by data2mem.
*
*
* Address space LM32 memory
* g_dpram_size = 90112/4 = 22528
* This size is in 32 bit words => byte size = 4 * 22528 = 90112 bytes
*
* ATTENTION PARITY!
* Although the memory is implemented in RAMB36E1 the address same MUST be defined as
* RAMB32 (insetad of RAMB36) since we are NOT using parity! If the address space is
* defined as RAMB36 then data2mem is expecting an extra nibble for each 32 bit instruction
* in the ".elf" file and since this nibble is not provided, the ramblocks will be filled
* such that a nibble shift is accumulating in the data.
* Note that this can be examined using the command
* "data2mem -bm clbv3_wr_ref_top_bd.bmm -bt clbv3_wr_ref_top_elf.bit -d > dump.txt"
*
* ATTENTION Xilinx Synthesis
* XST implements the 22K * 32 bit as:
* 22 blocks of 1K * 32 bits
*
****************************************************************************************/
ADDRESS_SPACE lm32_wrpc_memory COMBINED [0x00000000:0x0001FFFF]
ADDRESS_RANGE RAMB32
BUS_BLOCK
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram38 [31];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram37 [30];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram36 [29];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram35 [28];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram34 [27];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram33 [26];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram32 [25];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram31 [24];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram28 [23];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram27 [22];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram26 [21];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram25 [20];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram24 [19];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram23 [18];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram22 [17];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram21 [16];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram18 [15];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram17 [14];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram16 [13];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram15 [12];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram14 [11];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram13 [10];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram12 [9];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram11 [8];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram08 [7];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram07 [6];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram06 [5];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram05 [4];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram04 [3];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram03 [2];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram02 [1];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram01 [0];
END_BUS_BLOCK;
END_ADDRESS_RANGE;
END_ADDRESS_SPACE;
\ No newline at end of file
top/clbv3_ref_design/clbv3_wr_ref_top.ucf 0 → 100644
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top/clbv3_ref_design/clbv3_wr_ref_top.vhd 0 → 100644
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