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White Rabbit core collection
Commit 56003f97 authored by li hongming's avatar li hongming Committed by Grzegorz Daniluk
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Add 10MHz output through ext_clk pin.

parent ec8b53e5
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Showing with 281 additions and 7 deletions
board/cute/wr_cute_pkg.vhd
View file @ 56003f97
......@@ -81,6 +81,7 @@ package wr_cute_pkg is
pps_ext_i : in std_logic := '0';
clk_sys_62m5_o : out std_logic;
clk_ref_125m_o : out std_logic;
clk_500m_o : out std_logic;
rst_sys_62m5_n_o : out std_logic;
rst_ref_125m_n_o : out std_logic;
plldac_sclk_o : out std_logic;
......@@ -114,9 +115,9 @@ package wr_cute_pkg is
sfp1_tx_fault_i : in std_logic := '0';
sfp1_tx_disable_o : out std_logic;
sfp1_los_i : in std_logic := '0';
eeprom_sda_i : in std_logic;
eeprom_sda_i : in std_logic := '1';
eeprom_sda_o : out std_logic;
eeprom_scl_i : in std_logic;
eeprom_scl_i : in std_logic := '1';
eeprom_scl_o : out std_logic;
onewire_i : in std_logic;
onewire_oen_o : out std_logic;
......@@ -125,7 +126,7 @@ package wr_cute_pkg is
flash_sclk_o : out std_logic;
flash_ncs_o : out std_logic;
flash_mosi_o : out std_logic;
flash_miso_i : in std_logic;
flash_miso_i : in std_logic := '1';
wb_slave_o : out t_wishbone_slave_out;
wb_slave_i : in t_wishbone_slave_in := cc_dummy_slave_in;
aux_master_o : out t_wishbone_master_out;
......@@ -173,6 +174,7 @@ package wr_cute_pkg is
pps_p_o : out std_logic;
pps_led_o : out std_logic;
pps_csync_o : out std_logic;
pll_locked_o : out std_logic;
link_ok_o : out std_logic);
end component xwrc_board_cute;
......
board/cute/xwrc_board_cute.vhd
View file @ 56003f97
......@@ -111,6 +111,8 @@ entity xwrc_board_cute is
clk_sys_62m5_o : out std_logic;
-- 125MHz ref clock output
clk_ref_125m_o : out std_logic;
-- 500MHz clock output
clk_500m_o : out std_logic;
-- active low reset outputs, synchronous to 62m5 and 125m clocks
rst_sys_62m5_n_o : out std_logic;
rst_ref_125m_n_o : out std_logic;
......@@ -274,6 +276,7 @@ entity xwrc_board_cute is
pps_p_o : out std_logic;
pps_led_o : out std_logic;
pps_csync_o: out std_logic;
pll_locked_o : out std_logic;
-- Link ok indication
link_ok_o : out std_logic
);
......@@ -317,6 +320,7 @@ architecture struct of xwrc_board_cute is
signal clk_125m_gtp_n : std_logic;
signal clk_pll_62m5 : std_logic;
signal clk_pll_125m : std_logic;
signal clk_pll_500m : std_logic;
signal clk_pll_dmtd : std_logic;
signal pll_locked : std_logic;
signal clk_10m_ext : std_logic;
......@@ -415,6 +419,7 @@ begin -- architecture struct
sfp_tx_disable_o => sfp_tx_disable_out,
clk_62m5_sys_o => clk_pll_62m5,
clk_125m_ref_o => clk_pll_125m,
clk_500m_o => clk_pll_500m,
clk_62m5_dmtd_o => clk_pll_dmtd,
pll_locked_o => pll_locked,
clk_10m_ext_o => clk_10m_ext,
......@@ -427,6 +432,7 @@ begin -- architecture struct
clk_sys_62m5_o <= clk_pll_62m5;
clk_ref_125m_o <= clk_pll_125m;
clk_500m_o <= clk_pll_500m;
-----------------------------------------------------------------------------
-- SFP0/1 selection
......@@ -665,6 +671,7 @@ begin -- architecture struct
tm_time_valid_o <= tm_time_valid;
pps_valid_o <= tm_time_valid;
pll_locked_o <= pll_locked;
onewire_oen_o <= onewire_en(0);
onewire_in(0) <= onewire_i;
......
modules/timing/Manifest.py
View file @ 56003f97
......@@ -3,5 +3,6 @@ files = ["dmtd_phase_meas.vhd",
"multi_dmtd_with_deglitcher.vhd",
"hpll_period_detect.vhd",
"pulse_gen.vhd",
"oserdes_4_to_1",
"pulse_stamper.vhd" ]
modules/timing/oserdes_4_to_1.vhd 0 → 100644
View file @ 56003f97
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity oserdes_4_to_1 is
generic
(-- width of the data for the system
sys_w : integer := 1;
-- width of the data for the device
dev_w : integer := 4);
port
(
-- from the device out to the system
data_out_from_device : in std_logic_vector(dev_w-1 downto 0);
data_out_to_pins : out std_logic_vector(sys_w-1 downto 0);
-- input, output delay control signals
delay_reset : in std_logic; -- active high synchronous reset for input delay
-- clock and reset signals
clk_in : in std_logic;
pll_locked : in std_logic;
clk_div_in : in std_logic;
io_reset : in std_logic); -- reset signal for io circuit
end oserdes_4_to_1;
architecture xilinx of oserdes_4_to_1 is
constant num_serial_bits : integer := dev_w/sys_w;
signal ioclk : std_logic;
type serdarr is array (0 to 3) of std_logic_vector(sys_w-1 downto 0);
-- array to use intermediately from the serdes to the internal
-- devices. bus "0" is the leftmost bus
-- * fills in from higher order
signal oserdes_d : serdarr := (( others => (others => '0')));
signal serdesstrobe : std_logic;
-- delay ctrl
signal data_out_to_pins_predelay : std_logic_vector(sys_w-1 downto 0);
signal data_delay : std_logic_vector(sys_w-1 downto 0);
type loadarr is array (0 to 15) of std_logic_vector(4 downto 0);
signal intap : loadarr := (( others => (others => '0')));
signal outtap : loadarr := (( others => (others => '0')));
begin
bufpll_inst : bufpll
generic map (
divide => 4, -- divclk divider (1-8)
enable_sync => true -- enable synchrnonization between pll and gclk (true/false)
)
port map (
ioclk => ioclk, -- 1-bit output: output i/o clock
lock => open, -- 1-bit output: synchronized lock output
serdesstrobe => serdesstrobe, -- 1-bit output: output serdes strobe (connect to iserdes2/oserdes2)
gclk => clk_div_in, -- 1-bit input: bufg clock input
locked => pll_locked, -- 1-bit input: locked input from pll
pllin => clk_in -- 1-bit input: clock input from pll
);
-- we have multiple bits- step over every bit, instantiating the required elements
pins: for pin_count in 0 to sys_w-1 generate
begin
data_out_to_pins(pin_count) <= data_delay(pin_count);
iodelay2_inst : iodelay2
generic map (
counter_wraparound => "wraparound", -- "stay_at_limit" or "wraparound"
data_rate => "sdr", -- "sdr" or "ddr"
delay_src => "odatain", -- "io", "odatain" or "idatain"
idelay2_value => 0, -- delay value when idelay_mode="pci" (0-255)
idelay_mode => "normal", -- "normal" or "pci"
idelay_type => "default", -- "fixed", "default", "variable_from_zero", "variable_from_half_max"
-- or "diff_phase_detector"
idelay_value => 0, -- amount of taps for fixed input delay (0-255)
odelay_value => 33, -- amount of taps fixed output delay (0-255)
serdes_mode => "none", -- "none", "master" or "slave"
sim_tapdelay_value => 75 -- per tap delay used for simulation in ps
)
port map (
busy => open, -- 1-bit output: busy output after cal
dataout => open, -- 1-bit output: delayed data output to iserdes/input register
dataout2 => open, -- 1-bit output: delayed data output to general fpga fabric
dout => data_delay(pin_count), -- 1-bit output: delayed data output
tout => open, -- 1-bit output: delayed 3-state output
cal => '0', -- 1-bit input: initiate calibration input
ce => '0', -- 1-bit input: enable inc input
clk => clk_div_in, -- 1-bit input: clock input
idatain => '0', -- 1-bit input: data input (connect to top-level port or i/o buffer)
inc => '0', -- 1-bit input: increment / decrement input
ioclk0 => ioclk, -- 1-bit input: input from the i/o clock network
ioclk1 => '0', -- 1-bit input: input from the i/o clock network
odatain => data_out_to_pins_predelay(pin_count), -- 1-bit input: output data input from output register or oserdes2.
rst => delay_reset, -- 1-bit input: reset to zero or 1/2 of total delay period
t => '0' -- 1-bit input: 3-state input signal
);
-- instantiate the serdes primitive
-- declare the oserdes
oserdes2_inst : oserdes2
generic map (
bypass_gclk_ff => false, -- bypass clkdiv syncronization registers (true/false)
data_rate_oq => "sdr", -- output data rate ("sdr" or "ddr")
data_rate_ot => "sdr", -- 3-state data rate ("sdr" or "ddr")
data_width => 4, -- parallel data width (2-8)
output_mode => "single_ended", -- "single_ended" or "differential"
serdes_mode => "none", -- "none", "master" or "slave"
train_pattern => 0 -- training pattern (0-15)
)
port map (
oq => data_out_to_pins_predelay(pin_count), -- 1-bit output: data output to pad or iodelay2
shiftout1 => open, -- 1-bit output: cascade data output
shiftout2 => open, -- 1-bit output: cascade 3-state output
shiftout3 => open, -- 1-bit output: cascade differential data output
shiftout4 => open, -- 1-bit output: cascade differential 3-state output
tq => open, -- 1-bit output: 3-state output to pad or iodelay2
clk0 => ioclk, -- 1-bit input: i/o clock input
clk1 => '0', -- 1-bit input: secondary i/o clock input
clkdiv => clk_div_in, -- 1-bit input: logic domain clock input
-- d1 - d4: 1-bit (each) input: parallel data inputs
d1 => oserdes_d(3)(pin_count),
d2 => oserdes_d(2)(pin_count),
d3 => oserdes_d(1)(pin_count),
d4 => oserdes_d(0)(pin_count),
ioce => serdesstrobe, -- 1-bit input: data strobe input
oce => '1', -- 1-bit input: clock enable input
rst => io_reset, -- 1-bit input: asynchrnous reset input
shiftin1 => '1', -- 1-bit input: cascade data input
shiftin2 => '1', -- 1-bit input: cascade 3-state input
shiftin3 => '1', -- 1-bit input: cascade differential data input
shiftin4 => '1', -- 1-bit input: cascade differential 3-state input
-- t1 - t4: 1-bit (each) input: 3-state control inputs
t1 => '0',
t2 => '0',
t3 => '0',
t4 => '0',
tce => '0', -- 1-bit input: 3-state clock enable input
train => '0' -- 1-bit input: training pattern enable input
);
out_slices: for slice_count in 0 to num_serial_bits-1 generate begin
-- this places the first data in time on the right
oserdes_d(4-slice_count-1)(pin_count) <=
data_out_from_device(slice_count);
-- to place the first data in time on the left, use the
-- following code, instead
-- oserdes_d(slice_count) <=
-- data_out_from_device(slice_count);
end generate out_slices;
end generate pins;
end xilinx;
syn/cute_ref_design/cute_wr_ref.xise
View file @ 56003f97
......@@ -1345,6 +1345,10 @@
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="336"/>
</file>
<file xil_pn:name="../../modules/timing/oserdes_4_to_1.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="390"/>
<association xil_pn:name="Implementation" xil_pn:seqID="166"/>
</file>
</files>
<bindings/>
......
top/cute_ref_design/cute_wr_ref_top.ucf
View file @ 56003f97
......@@ -111,7 +111,7 @@ net "plldac_sclk" loc = c2;net "plldac_sclk" iostandard = lvcmos33;
net "plldac_sync_n" loc = d1;net "plldac_sync_n" iostandard = lvcmos33;
net "plldac_load_n" loc = d2;net "plldac_load_n" iostandard = lvcmos33;
#net "ext_clk" loc = f2;net "ext_clk" iostandard = lvcmos33;
net "ext_clk" loc = f2;net "ext_clk" iostandard = lvcmos33;
net "sfp1_led" loc = g3;net "sfp1_led" iostandard = lvcmos33;
net "sfp0_led" loc = k4;net "sfp0_led" iostandard = lvcmos33;
net "sfp0_los" loc = g1;net "sfp0_los" iostandard = lvcmos33;
......
top/cute_ref_design/cute_wr_ref_top.vhd
View file @ 56003f97
......@@ -150,7 +150,7 @@ entity cute_wr_ref_top is
-- user interface
sfp0_led : out std_logic;
sfp1_led : out std_logic;
--ext_clk : out std_logic;
ext_clk : out std_logic;
usr_button : in std_logic;
usr_led1 : out std_logic;
usr_led2 : out std_logic;
......@@ -159,10 +159,40 @@ entity cute_wr_ref_top is
end cute_wr_ref_top;
architecture rtl of cute_wr_ref_top is
component oserdes_4_to_1 is
generic(
sys_w : integer := 1;
dev_w : integer := 4);
port(
data_out_from_device : in std_logic_vector(dev_w-1 downto 0);
data_out_to_pins : out std_logic_vector(sys_w-1 downto 0);
delay_reset : in std_logic;
clk_in : in std_logic;
pll_locked : in std_logic;
clk_div_in : in std_logic;
io_reset : in std_logic);
end component;
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
-- ext 10M clock output
constant c_DATA_W : integer := 4; -- parallel data width going to serdes
constant c_HALF : integer := 25;-- default high/low width for 10MHz
signal rst_oserdes : std_logic;
signal pll_locked : std_logic;
signal sd_out : std_logic_vector(0 downto 0);
signal sd_data : std_logic_vector(c_DATA_W-1 downto 0);
signal aux_half_high: unsigned(15 downto 0);
signal aux_half_low : unsigned(15 downto 0);
signal aux_shift : unsigned(15 downto 0);
signal pps_valid_d : std_logic;
signal clk_realign : std_logic;
signal new_freq : std_logic;
-- I2C EEPROM
signal eeprom_scl_o : std_logic;
......@@ -185,7 +215,10 @@ architecture rtl of cute_wr_ref_top is
signal sfp1_sda_o : std_logic;
signal pps : std_logic;
signal pps_p1 : std_logic;
signal pps_csync : std_logic;
attribute maxdelay : string;
attribute maxdelay of pps_csync : signal is "500 ps";
signal pps_valid : std_logic;
signal tm_tai : std_logic_vector(39 downto 0);
signal tm_tai_valid : std_logic;
-- Wishbone buse(s) from masters attached to crossbar
......@@ -198,6 +231,7 @@ architecture rtl of cute_wr_ref_top is
-- Not needed now, but useful if application cores are added
signal clk_sys_62m5 : std_logic;
signal clk_ref_125m : std_logic;
signal clk_500m : std_logic;
signal rst_sys_62m5_n : std_logic;
signal rst_ref_125m_n : std_logic;
......@@ -223,6 +257,7 @@ begin
clk_125m_gtp1_n_i => sfp1_ref_clk_n,
clk_sys_62m5_o => clk_sys_62m5,
clk_ref_125m_o => clk_ref_125m,
clk_500m_o => clk_500m,
rst_sys_62m5_n_o => rst_sys_62m5_n,
rst_ref_125m_n_o => rst_ref_125m_n,
......@@ -290,7 +325,9 @@ begin
led_link_o => sfp1_led,
pps_p_o => pps_out,
pps_led_o => usr_led1,
pps_csync_o => pps_p1,
pps_valid_o => pps_valid,
pps_csync_o => pps_csync,
pll_locked_o => pll_locked,
link_ok_o => usr_led2);
cnx_slave_in <= cnx_master_out;
......@@ -316,4 +353,63 @@ begin
one_wire <= '0' when onewire_oen_o = '1' else 'Z';
onewire_i <= one_wire;
aux_half_high <= to_unsigned(c_HALF, aux_half_high'length);
aux_half_low <= to_unsigned(c_HALF, aux_half_low'length);
aux_shift <= to_unsigned(11, aux_half_low'length);
new_freq <= '0';
rst_oserdes <= not pll_locked;
ext_clk <= sd_out(0);
process(clk_ref_125m)
begin
if rising_edge(clk_ref_125m) then
if(rst_ref_125m_n = '0' or pll_locked = '0') then -- if new_freq or pll lost lock,
pps_valid_d <= '0';
elsif(pps_csync = '1') then
pps_valid_d <= pps_valid;
end if;
end if;
end process;
clk_realign <= (not pps_valid_d) and pps_valid and pps_csync;
process(clk_ref_125m)
variable rest : integer range 0 to 65535;
variable v_bit : std_logic;
begin
if rising_edge(clk_ref_125m) then
if (rst_ref_125m_n='0' or pll_locked='0' or clk_realign='1') then
rest := to_integer(aux_half_high - aux_shift);
v_bit := '1';
else
for i in 0 to c_DATA_W-1 loop
if(rest /= 0) then
sd_data(i) <= v_bit;
rest := rest - 1;
elsif(v_bit = '1') then
sd_data(i) <= '0';
v_bit := '0';
rest := to_integer(aux_half_low-1); -- because here we already wrote first bit
-- from this group
elsif(v_bit = '0') then
sd_data(i) <= '1';
v_bit := '1';
rest := to_integer(aux_half_high-1);
end if;
end loop;
end if;
end if;
end process;
U_10MHZ_SERDES: oserdes_4_to_1
generic map(
dev_w => c_DATA_W)
port map(
data_out_from_device => sd_data,
data_out_to_pins => sd_out,
delay_reset => '0',
clk_in => clk_500m,
pll_locked => pll_locked,
clk_div_in => clk_ref_125m,
io_reset => rst_oserdes);
end rtl;
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