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White Rabbit core collection
Commit 56dab112 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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modules/wr_endpoint: area optimizations in ep_rx_crc_size_check

parent b995d923
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Showing with 169 additions and 36 deletions
modules/wr_endpoint/Manifest.py
View file @ 56dab112
......@@ -29,6 +29,7 @@ files = [ "endpoint_private_pkg.vhd",
"ep_sync_detect_16bit.vhd",
"ep_wishbone_controller.vhd",
"ep_registers_pkg.vhd",
"ep_crc32_pkg.vhd",
"endpoint_pkg.vhd",
"wr_endpoint.vhd",
"xwr_endpoint.vhd"
......
modules/wr_endpoint/ep_crc32_pkg.vhd 0 → 100644
View file @ 56dab112
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modules/wr_endpoint/ep_rx_crc_size_check.vhd
View file @ 56dab112
......@@ -7,11 +7,16 @@ use work.gencores_pkg.all; -- for gc_crc_gen
use work.endpoint_private_pkg.all;
use work.wr_fabric_pkg.all;
use work.ep_wbgen2_pkg.all;
use work.ep_crc32_pkg.all;
-- 1st deframing pipeline stage - CRC/PCS error/Size checker
entity ep_rx_crc_size_check is
port(clk_sys_i : in std_logic;
generic
(
g_use_new_crc : boolean := true);
port(
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
snk_fab_i : in t_ep_internal_fabric;
......@@ -52,7 +57,11 @@ architecture behavioral of ep_rx_crc_size_check is
signal crc_gen_enable : std_logic;
signal crc_gen_reset : std_logic;
signal crc_match : std_logic;
signal crc_match, crc_match2 : std_logic;
signal crc_cur : std_logic_vector(31 downto 0);
signal crc_in_data : std_logic_vector(15 downto 0);
signal crc_last_is_odd : std_logic;
signal byte_cntr : unsigned(13 downto 0);
signal is_runt : std_logic;
......@@ -68,13 +77,16 @@ architecture behavioral of ep_rx_crc_size_check is
signal q_bytesel : std_logic;
signal q_dvalid_in : std_logic;
signal q_dvalid_out : std_logic;
signal q_dreq_out: std_logic;
signal q_dreq_out : std_logic;
signal dvalid_mask : std_logic_vector(1 downto 0);
begin -- behavioral
crc_gen_reset <= snk_fab_i.sof or (not rst_n_i);
crc_gen_enable <= '1' when (snk_fab_i.addr = c_WRF_DATA and snk_fab_i.dvalid = '1') else '0';
gen_old_crc : if(g_use_new_crc = false) generate
U_rx_crc_generator : gc_crc_gen
generic map (
g_polynomial => x"04C11DB7",
......@@ -93,6 +105,29 @@ begin -- behavioral
data_i => snk_fab_i.data(15 downto 0),
match_o => crc_match,
crc_o => open);
end generate gen_old_crc;
gen_new_crc : if(g_use_new_crc = true) generate
crc_in_data(15 downto 8) <= snk_fab_i.data(15 downto 8);
crc_in_data(7 downto 0) <= x"00" when snk_fab_i.bytesel = '1' else snk_fab_i.data(7 downto 0);
p_check_crc : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if crc_gen_reset = '1' then
crc_cur <= c_CRC32_INIT_VALUE;
elsif(crc_gen_enable = '1') then
crc_cur <= f_update_crc32_d16(crc_cur, crc_in_data);
crc_last_is_odd <= snk_fab_i.bytesel;
end if;
end if;
end process;
crc_match <= '1' when (crc_last_is_odd = '0' and crc_cur = c_CRC32_RESIDUE_FULL)
or (crc_last_is_odd = '1' and crc_cur = c_CRC32_RESIDUE_HALF) else '0';
end generate gen_new_crc;
q_in(15 downto 0) <= snk_fab_i.data;
q_in(17 downto 16) <= snk_fab_i.addr;
......@@ -139,7 +174,7 @@ begin -- behavioral
end if;
end if;
if(byte_cntr = to_unsigned(c_MIN_FRAME_SIZE - 2, byte_cntr'length) and snk_fab_i.dvalid= '1' and snk_fab_i.bytesel = '0') then
if(byte_cntr = to_unsigned(c_MIN_FRAME_SIZE - 2, byte_cntr'length) and snk_fab_i.dvalid = '1' and snk_fab_i.bytesel = '0') then
is_runt <= '0';
end if;
......
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