Initial commit

changed pci_rst_n to perst_n, linked to wrc.bin linked to wrc.bin linked to wrc.bin corrected .bram file corrected .bram file corrected .bram file

Initial commit
changed pci_rst_n to perst_n, linked to wrc.bin linked to wrc.bin linked to wrc.bin corrected .bram file corrected .bram file corrected .bram file
67892968 · Pascal Bos · f5f7f210 · 67892968 · 67892968 · 67892968
Commit 67892968 authored Feb 07, 2020 by Pascal Bos
8 changed files
--- a/board/spec7/wr_spec7_pkg.vhd
+++ b/board/spec7/wr_spec7_pkg.vhd
@@ -110,6 +110,8 @@ package wr_spec7_pkg is
      onewire_oen_o        : out std_logic;
      uart_rxd_i           : in  std_logic;
      uart_txd_o           : out std_logic;
+      wb_slave_i           : in  t_wishbone_slave_in := cc_dummy_slave_in;
+      wb_slave_o           : out t_wishbone_slave_out;
      wrf_src_o            : out t_wrf_source_out;
      wrf_src_i            : in  t_wrf_source_in                                  := c_dummy_src_in;
      wrf_snk_o            : out t_wrf_sink_out;
@@ -152,6 +154,152 @@ package wr_spec7_pkg is
      link_ok_o            : out std_logic);
  end component xwrc_board_spec7;

+  type t_axis_32 is record
+    data  : std_logic_vector(31 DOWNTO 0);
+    last  : std_logic;
+    valid : std_logic;
+    ready : std_logic;
+    keep  : std_logic_vector(31/8 DOWNTO 0);
+  end record t_axis_32;
+  
+  type t_axis_64 is record
+    data  : std_logic_vector(63 DOWNTO 0);
+    last  : std_logic;
+    valid : std_logic;
+    ready : std_logic;
+    keep  : std_logic_vector(63/8 DOWNTO 0);
+  end record t_axis_64;
+  
+  -- AXI4-Lite interface, master output ports, 32 bits
+  type t_axi4_lite_master_out_32 is record
+    ARVALID : std_logic;
+    AWVALID : std_logic;
+    BREADY  : std_logic;
+    RREADY  : std_logic;
+    WLAST   : std_logic;
+    WVALID  : std_logic;
+    ARADDR  : std_logic_vector (31 downto 0);
+    AWADDR  : std_logic_vector (31 downto 0);
+    WDATA   : std_logic_vector (31 downto 0);
+    WSTRB   : std_logic_vector (3 downto 0);
+  end record;
+  subtype t_axi4_lite_slave_in_32 is t_axi4_lite_master_out_32;
+  
+  -- AXI4-Lite interface, master input ports, 32 bits
+  type t_axi4_lite_master_in_32 is record
+    ARREADY : std_logic;
+    AWREADY : std_logic;
+    BVALID  : std_logic;
+    RLAST   : std_logic;
+    RVALID  : std_logic;
+    WREADY  : std_logic;
+    BRESP   : std_logic_vector (1 downto 0);
+    RRESP   : std_logic_vector (1 downto 0);
+    RDATA   : std_logic_vector (31 downto 0);
+  end record;
+  subtype t_axi4_lite_slave_out_32 is t_axi4_lite_master_in_32;
+
+  COMPONENT xdma_0
+  PORT (
+    sys_clk : IN STD_LOGIC;
+    sys_rst_n : IN STD_LOGIC;
+    user_lnk_up : OUT STD_LOGIC;
+    pci_exp_txp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    pci_exp_txn : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    pci_exp_rxp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+    pci_exp_rxn : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+    axi_aclk : OUT STD_LOGIC;
+    axi_aresetn : OUT STD_LOGIC;
+    usr_irq_req : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    usr_irq_ack : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    m_axil_awaddr   : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    m_axil_awprot   : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+    m_axil_awvalid  : OUT STD_LOGIC;
+    m_axil_awready  : IN STD_LOGIC;
+    m_axil_wdata    : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    m_axil_wstrb    : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+    m_axil_wvalid   : OUT STD_LOGIC;
+    m_axil_wready   : IN STD_LOGIC;
+    m_axil_bvalid   : IN STD_LOGIC;
+    m_axil_bresp    : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+    m_axil_bready   : OUT STD_LOGIC;
+    m_axil_araddr   : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    m_axil_arprot   : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+    m_axil_arvalid  : OUT STD_LOGIC;
+    m_axil_arready  : IN STD_LOGIC;
+    m_axil_rdata    : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    m_axil_rresp    : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+    m_axil_rvalid   : IN STD_LOGIC;
+    m_axil_rready   : OUT STD_LOGIC;
+    s_axis_c2h_tdata_0 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
+    s_axis_c2h_tlast_0 : IN STD_LOGIC;
+    s_axis_c2h_tvalid_0 : IN STD_LOGIC;
+    s_axis_c2h_tready_0 : OUT STD_LOGIC;
+    s_axis_c2h_tkeep_0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    m_axis_h2c_tdata_0 : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
+    m_axis_h2c_tlast_0 : OUT STD_LOGIC;
+    m_axis_h2c_tvalid_0 : OUT STD_LOGIC;
+    m_axis_h2c_tready_0 : IN STD_LOGIC;
+    m_axis_h2c_tkeep_0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+  );
+  END COMPONENT;
+  component Pcie_wrapper is
+  port (
+    aclk1_0 : in STD_LOGIC;
+    pcie_clk : in STD_LOGIC;
+    pcie_rst_n : in STD_LOGIC;
+    user_lnk_up_0 : out STD_LOGIC;
+    usr_irq_ack_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
+    usr_irq_req_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    M00_AXI_0_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M00_AXI_0_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
+    M00_AXI_0_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
+    M00_AXI_0_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    M00_AXI_0_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
+    M00_AXI_0_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
+    M00_AXI_0_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
+    M00_AXI_0_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
+    M00_AXI_0_awvalid : out STD_LOGIC;
+    M00_AXI_0_awready : in STD_LOGIC;
+    M00_AXI_0_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M00_AXI_0_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
+    M00_AXI_0_wlast : out STD_LOGIC;
+    M00_AXI_0_wvalid : out STD_LOGIC;
+    M00_AXI_0_wready : in STD_LOGIC;
+    M00_AXI_0_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    M00_AXI_0_bvalid : in STD_LOGIC;
+    M00_AXI_0_bready : out STD_LOGIC;
+    M00_AXI_0_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M00_AXI_0_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
+    M00_AXI_0_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
+    M00_AXI_0_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    M00_AXI_0_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
+    M00_AXI_0_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
+    M00_AXI_0_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
+    M00_AXI_0_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
+    M00_AXI_0_arvalid : out STD_LOGIC;
+    M00_AXI_0_arready : in STD_LOGIC;
+    M00_AXI_0_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    M00_AXI_0_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    M00_AXI_0_rlast : in STD_LOGIC;
+    M00_AXI_0_rvalid : in STD_LOGIC;
+    M00_AXI_0_rready : out STD_LOGIC;
+    pcie_mgt_0_rxn : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    pcie_mgt_0_rxp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    pcie_mgt_0_txn : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    pcie_mgt_0_txp : out STD_LOGIC_VECTOR ( 1 downto 0 )
+  );
+  end component Pcie_wrapper;
+  component xwb_axi4lite_bridge is
+    port (
+    clk_sys_i    : in std_logic;
+    rst_n_i      : in std_logic;
+    axi4_slave_i : in  t_axi4_lite_slave_in_32;
+    axi4_slave_o : out t_axi4_lite_slave_out_32;
+    wb_master_o  : out t_wishbone_master_out;
+    wb_master_i  : in  t_wishbone_master_in
+    );
+  end component;

 --  component wrc_board_spec7 is
 --    generic (

--- a/board/spec7/xwrc_board_spec7.vhd
+++ b/board/spec7/xwrc_board_spec7.vhd
@@ -175,9 +175,10 @@ entity xwrc_board_spec7 is
    ---------------------------------------------------------------------------

    ---------------------------------------------------------------------------
-    -- No External WB interface
+    --External WB interface
    ---------------------------------------------------------------------------
-
+    wb_slave_i : in  t_wishbone_slave_in := cc_dummy_slave_in;
+    wb_slave_o : out t_wishbone_slave_out;
    ---------------------------------------------------------------------------
    -- WR fabric interface (when g_fabric_iface = "plainfbrc")
    ---------------------------------------------------------------------------
@@ -358,6 +359,7 @@ begin  -- architecture struct
  -- The AD9516 on the SPEC7 needs to be initialized before it outputs 
  -- clk_125m_gtx_p/n_i (which is 

+
  cmp_bufgmux: BUFGMUX
    port map (
      O  => clk_sys_62m5,
@@ -529,6 +531,8 @@ begin  -- architecture struct
      owr_pwren_o          => open,
      owr_en_o             => onewire_en,
      owr_i                => onewire_in,
+      wb_slave_i           => wb_slave_i,
+      wb_slave_o           => wb_slave_o,
      wrf_src_o            => wrf_src_o,
      wrf_src_i            => wrf_src_i,
      wrf_snk_o            => wrf_snk_o,

--- a/platform/xilinx/Manifest.py
+++ b/platform/xilinx/Manifest.py
 files = [ "wr_xilinx_pkg.vhd", "xwrc_platform_xilinx.vhd" ]
-modules = {"local" : ["wr_gtp_phy", "chipscope"]}
+modules = {"local" : ["wr_gtp_phy", "chipscope", "wr_pcie"]}
--- a/platform/xilinx/wr_pcie/Manifest.py
+++ b/platform/xilinx/wr_pcie/Manifest.py
+files = [ "Pcie.tcl", "wb_axi4lite_bridge.vhd" ]
--- a/platform/xilinx/wr_pcie/Pcie.tcl
+++ b/platform/xilinx/wr_pcie/Pcie.tcl
--- a/platform/xilinx/wr_pcie/wb_axi4lite_bridge.vhd
+++ b/platform/xilinx/wr_pcie/wb_axi4lite_bridge.vhd
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.wishbone_pkg.all;
+use work.axi4_pkg.all;
+
+entity xwb_axi4lite_bridge is
+  port (
+    clk_sys_i    : in std_logic;
+    rst_n_i      : in std_logic;
+    axi4_slave_i : in  t_axi4_lite_slave_in_32;
+    axi4_slave_o : out t_axi4_lite_slave_out_32;
+    wb_master_o  : buffer t_wishbone_master_out;
+    wb_master_i  : in  t_wishbone_master_in
+  );
+end entity xwb_axi4lite_bridge;
+
+architecture rtl of xwb_axi4lite_bridge is
+  type state_type is (IDLE, SR_SEND_ADDR, SR_GET_DATA, SR_SEND_DATA, SW_GET_DATA, SW_GET_ADDR, SW_SEND, SW_RESP);
+  signal prs, nxt : state_type;
+  begin 
+
+  --state register for the Moore state machine, also has a timeout counter. 
+state_register : process(clk_sys_i,rst_n_i) is  
+  variable count : unsigned(10 downto 0);
+begin
+  if rst_n_i = '0' then
+    prs <= IDLE; 
+    count := (others => '0');
+  elsif rising_edge(clk_sys_i) then
+    if prs /= IDLE then
+      count := count + 1;
+    else 
+      count := (others => '0');
+    end if;
+    if count > 100 then   
+      prs <= IDLE;
+    else
+      prs <= nxt;
+    end if;
+  end if;
+end process state_register;    
+
+--next state decoder for the Moore state machine.
+next_state_decoder : process(prs, wb_master_i, axi4_slave_i) is
+begin
+  case prs is
+  when IDLE =>
+    if axi4_slave_i.awvalid = '1' and axi4_slave_i.wvalid = '1'then
+      nxt <= SW_SEND;
+    elsif axi4_slave_i.awvalid = '0' and axi4_slave_i.wvalid = '1' then
+      nxt <= SW_GET_ADDR;
+    elsif axi4_slave_i.awvalid = '1' and axi4_slave_i.wvalid = '0' then
+      nxt <= SW_GET_DATA;
+    elsif axi4_slave_i.arvalid = '1' then
+      nxt <= SR_SEND_ADDR;
+    else  
+      nxt <= IDLE;
+    end if;
+  when SW_GET_ADDR =>
+    if axi4_slave_i.awvalid = '1' then
+      nxt <= SW_SEND; 
+    else
+      nxt <= SW_GET_ADDR;
+    end if;
+  when SW_GET_DATA => 
+    if axi4_slave_i.wvalid = '1' then
+      nxt <= SW_SEND; 
+    else
+      nxt <= SW_GET_DATA;
+    end if;
+  when SW_SEND => 
+    if wb_master_i.ack = '1' or wb_master_i.stall = '0' then
+      nxt <= SW_RESP; 
+    else
+      nxt <= SW_SEND;
+    end if;
+  when SR_SEND_ADDR =>
+    if wb_master_i.stall = '0' then
+      nxt <= SR_GET_DATA;
+    else 
+      nxt <= SR_SEND_ADDR;
+    end if;
+  when SR_GET_DATA => 
+    if wb_master_i.ack = '1' then
+      nxt <= SR_SEND_DATA;
+    else 
+      nxt <= SR_GET_DATA;
+    end if;
+  when SR_SEND_DATA =>
+    if axi4_slave_i.rready = '1' then
+      nxt <= IDLE;
+    else
+      nxt <= SR_SEND_DATA;
+    end if;
+  when SW_RESP => 
+    if axi4_slave_i.bready = '1' then
+      nxt <= IDLE;
+    else
+      nxt <= SW_RESP;
+    end if;
+  end case;
+end process next_state_decoder; 
+
+--manages the Wishbone addres signal, sources it from the axi-read or write channel depending on the command. 
+addr_register : process(clk_sys_i, rst_n_i) is 
+begin
+  if rst_n_i = '0' then
+    wb_master_o.adr <= (others => '0');
+  elsif rising_edge(clk_sys_i) then
+    if axi4_slave_i.awvalid = '1' then
+      wb_master_o.adr <= axi4_slave_i.awaddr;
+    elsif prs = SW_RESP then
+      wb_master_o.adr <= (others => '0');
+    elsif axi4_slave_i.arvalid = '1' then
+      wb_master_o.adr <= axi4_slave_i.araddr;
+    elsif prs = SR_SEND_DATA then
+      wb_master_o.adr <= (others => '0');
+    end if;
+  end if;
+end process addr_register;
+
+--manages the two data registers, one for reading (and byte-validation) the other for writing.
+data_register : process(clk_sys_i, rst_n_i) is 
+begin
+  if rst_n_i = '0' then
+    wb_master_o.dat <= (others => '0');
+    wb_master_o.sel <= (others => '0');
+    axi4_slave_o.rdata <= (others => '0');
+  elsif rising_edge(clk_sys_i) then
+    if axi4_slave_i.wvalid = '1' then
+      wb_master_o.dat <= axi4_slave_i.wdata;
+      wb_master_o.sel <= axi4_slave_i.wstrb;
+    elsif prs = SW_RESP then
+      wb_master_o.dat <= (others => '0');
+      wb_master_o.sel <= (others => '0');
+    end if;
+    if prs = SR_GET_DATA and wb_master_i.ack = '1' then
+      axi4_slave_o.rdata <= wb_master_i.dat;
+    elsif prs = IDLE then
+      axi4_slave_o.rdata <= (others => '0');
+    end if;
+  end if;
+end process data_register;
+
+--roughly convers wishbone error messages to axi-error mesages. 
+error_register : process(clk_sys_i, rst_n_i) is 
+begin
+  if rst_n_i = '0' then
+    axi4_slave_o.bresp <= "10";
+    axi4_slave_o.rresp <= "10";
+  elsif rising_edge(clk_sys_i) then
+    if prs = SW_SEND and wb_master_i.ack = '1' then
+      axi4_slave_o.bresp <= wb_master_i.err & '0';
+      axi4_slave_o.rresp <= "00";
+    elsif prs = SW_SEND and wb_master_i.ack = '1' then
+      axi4_slave_o.bresp <= "00";
+      axi4_slave_o.rresp <= wb_master_i.err & '0';
+    elsif prs = IDLE then
+      axi4_slave_o.bresp <= "00";
+      axi4_slave_o.rresp <= "00";
+    end if; 
+  end if;
+end process error_register;
+
+--AXI READ RELATED SIGNALS
+axi4_slave_o.arready  <= '1'    when rst_n_i = '1' and prs = IDLE else '0'; 
+axi4_slave_o.rvalid   <= '1'    when prs = SR_SEND_DATA else '0';
+axi4_slave_o.rlast    <= '1'    when prs = SR_SEND_DATA else '0';
+--AXI WRITE RELATED SIGNALS
+axi4_slave_o.awready <= '1' when rst_n_i = '1' and (prs = IDLE or prs = SW_GET_ADDR) else '0';
+axi4_slave_o.wready <= '1'  when rst_n_i = '1' and (prs = IDLE or prs = SW_GET_DATA) else '0';
+axi4_slave_o.bvalid <= '1'  when prs = SW_RESP else '0';
+--WISHBONE RELATED SIGNALS
+wb_master_o.we  <= '1'    when prs = SW_SEND else '0';
+wb_master_o.cyc <= '1'    when prs = SR_SEND_ADDR or prs = SR_GET_DATA or prs = SW_SEND else '0';
+wb_master_o.stb <= '1'    when prs = SR_SEND_ADDR or prs = SW_SEND else '0';
+
+end architecture rtl;
\ No newline at end of file
--- a/top/spec7_write_design/spec7_write_top.vhd
+++ b/top/spec7_write_design/spec7_write_top.vhd
@@ -180,7 +180,19 @@ entity spec7_write_top is
    -- EEPROM    (24AA64       Addr 1010.000x) and
    -- Unique ID (24AA025EU48, Addr 1010.001x).
    scl_b : inout std_logic;
-    sda_b : inout std_logic
+    sda_b : inout std_logic;
+    
+    ---------------------------------------------------------------------------
+    -- PCIe interface
+    ---------------------------------------------------------------------------
+    
+    pci_clk_n : in  std_logic;
+    pci_clk_p : in  std_logic;
+    perst_n   : in  std_logic;
+    rxn       : in  std_logic_vector(1 downto 0);
+    rxp       : in  std_logic_vector(1 downto 0);
+    txn       : out std_logic_vector(1 downto 0);
+    txp       : out std_logic_vector(1 downto 0)

  );
 end entity spec7_write_top;
@@ -254,6 +266,19 @@ architecture top of spec7_write_top is
  -- DIO Mezzanine
  signal dio_in  : std_logic_vector(4 downto 0);
  signal dio_out : std_logic_vector(4 downto 0);
+  
+  --Axi4
+  signal m_axil_i :  t_axi4_lite_master_in_32;
+  signal m_axil_o :  t_axi4_lite_master_out_32;
+  signal axi_h2c_fifo_64, axi_c2h_fifo_64 : t_axis_64;
+  
+  --Wishbone
+  signal wb_master_i : t_wishbone_master_in; 
+  signal wb_master_o : t_wishbone_master_out;
+
+  --PCIe 
+  signal pci_clk : std_logic;
+

  component pll_62m5_500m is
    port (
@@ -281,6 +306,71 @@ begin  -- architecture top
  wdog_n_o    <= '1';
  -- prsnt_m2c_l_i isn't used but must be defined as input.

+pci_clk_buf : IBUFDS_GTE2
+  port map(
+    I  => pci_clk_p,
+    IB => pci_clk_n,
+    O  => pci_clk,
+    ODIV2 => open,
+    CEB => '0'
+  ); 
+Pcie: Pcie_wrapper
+  port map (
+    M00_AXI_0_araddr  => m_axil_o.araddr,
+    M00_AXI_0_arburst => open,
+    M00_AXI_0_arcache => open,
+    M00_AXI_0_arlen   => open,
+    M00_AXI_0_arlock  => open,
+    M00_AXI_0_arprot  => open,
+    M00_AXI_0_arqos   => open,
+    M00_AXI_0_arready => m_axil_i.arready,
+    M00_AXI_0_arsize  => open,
+    M00_AXI_0_arvalid => m_axil_o.arvalid,
+    M00_AXI_0_awaddr  => m_axil_o.awaddr,
+    M00_AXI_0_awburst => open,
+    M00_AXI_0_awcache => open,
+    M00_AXI_0_awlen   => open,
+    M00_AXI_0_awlock  => open,
+    M00_AXI_0_awprot  => open,
+    M00_AXI_0_awqos   => open,
+    M00_AXI_0_awready => m_axil_i.awready,
+    M00_AXI_0_awsize  => open,
+    M00_AXI_0_awvalid => m_axil_o.awvalid,
+    M00_AXI_0_bready  => m_axil_o.bready,
+    M00_AXI_0_bresp   => m_axil_i.bresp,
+    M00_AXI_0_bvalid  => m_axil_i.bvalid,
+    M00_AXI_0_rdata   => m_axil_i.rdata,
+    M00_AXI_0_rlast   => m_axil_i.rlast,
+    M00_AXI_0_rready  => m_axil_o.rready,
+    M00_AXI_0_rresp   => m_axil_i.rresp,
+    M00_AXI_0_rvalid  => m_axil_i.rvalid,
+    M00_AXI_0_wdata   => m_axil_o.wdata,
+    M00_AXI_0_wlast   => m_axil_o.wlast,
+    M00_AXI_0_wready  => m_axil_i.wready,
+    M00_AXI_0_wstrb   => m_axil_o.wstrb,
+    M00_AXI_0_wvalid  => m_axil_o.wvalid,
+    aclk1_0           => clk_sys_62m5,
+    pcie_mgt_0_rxn    => rxn,
+    pcie_mgt_0_rxp    => rxp,
+    pcie_mgt_0_txn    => txn,
+    pcie_mgt_0_txp    => txp,
+    pcie_clk          => pci_clk,
+    pcie_rst_n        => perst_n,
+    user_lnk_up_0     => open,
+    usr_irq_ack_0     => open,
+    usr_irq_req_0     => "0"
+  );
+
+AXI2WB : xwb_axi4lite_bridge 
+  port map(
+    clk_sys_i => clk_sys_62m5,
+    rst_n_i   => reset_n_i,
+                
+    axi4_slave_i => m_axil_o,
+    axi4_slave_o => m_axil_i,
+    wb_master_o  => wb_master_o,
+    wb_master_i  => wb_master_i  
+  );
  -----------------------------------------------------------------------------
  -- The WR PTP core board package (WB Slave + WB Master)
  -----------------------------------------------------------------------------
@@ -303,7 +393,6 @@ begin  -- architecture top
      clk_ref_62m5_o      => clk_ref_62m5,
      rst_sys_62m5_n_o    => rst_sys_62m5_n,
      rst_ref_62m5_n_o    => rst_ref_62m5_n,
-
      dac_refclk_cs_n_o   => dac_refclk_cs_n_o,
      dac_refclk_sclk_o   => dac_refclk_sclk_o,
      dac_refclk_din_o    => dac_refclk_din_o,
@@ -345,6 +434,9 @@ begin  -- architecture top
      -- Uart
      uart_rxd_i          => uart_rxd_i,
      uart_txd_o          => uart_txd_o,
+      -- Wishbone
+      wb_slave_i          => wb_master_o,
+      wb_slave_o          => wb_master_i,
      
      abscal_txts_o       => wrc_abscal_txts_out,
      abscal_rxts_o       => open,

--- a/top/spec7_write_design/spec7_write_top.xdc
+++ b/top/spec7_write_design/spec7_write_top.xdc
@@ -94,6 +94,27 @@ set_property IOSTANDARD LVCMOS18 [get_ports pll_refsel_o]
 set_property PACKAGE_PIN A12 [get_ports pll_lock_i]
 set_property IOSTANDARD LVCMOS18 [get_ports pll_lock_i]

+#   ---------------------------------------------------------------------------
+#   -- PCIe 
+#   ---------------------------------------------------------------------------
+# Bank 112 (GTX2)
+set_property PACKAGE_PIN AB3 [get_ports {rxn[0]}]
+set_property PACKAGE_PIN AB4 [get_ports {rxp[0]}]
+set_property PACKAGE_PIN AA1 [get_ports {txn[0]}]
+set_property PACKAGE_PIN AA2 [get_ports {txp[0]}]
+
+set_property PACKAGE_PIN Y3 [get_ports {rxn[1]}]
+set_property PACKAGE_PIN Y4 [get_ports {rxp[1]}]
+set_property PACKAGE_PIN W1 [get_ports {txn[1]}]
+set_property PACKAGE_PIN W2 [get_ports {txp[1]}]
+
+set_property PACKAGE_PIN R6 [get_ports pci_clk_p]
+set_property PACKAGE_PIN R5 [get_ports pci_clk_n]
+create_clock -period 10.000 -name pci_clk_p [get_ports pci_clk_p]
+
+set_property PACKAGE_PIN D13 [get_ports perst_n]
+set_property IOSTANDARD LVCMOS18 [get_ports perst_n]
+
 #   ---------------------------------------------------------------------------
 #   -- SFP I/O for transceiver
 #   ---------------------------------------------------------------------------
@@ -123,14 +144,6 @@ set_property IOSTANDARD LVCMOS18 [get_ports sfp_tx_disable_o]
 set_property PACKAGE_PIN K13 [get_ports sfp_los_i]
 set_property IOSTANDARD LVCMOS18 [get_ports sfp_los_i]

-#   ---------------------------------------------------------------------------
-#   -- PCIe PERST#
-#   ---------------------------------------------------------------------------
-
-# Bank 35 (HP) VCCO - 1.8 V
-#set_property PACKAGE_PIN D13 [get_ports perst_n]
-#set_property IOSTANDARD LVCMOS18 [get_ports perst_n]
-
 #   ---------------------------------------------------------------------------
 #   -- UART
 #   ---------------------------------------------------------------------------