wrc_board_fasec_ip: update tcl and component after phys were reorganized

69517138 · Grzegorz Daniluk · 115886be · 69517138 · 69517138
Commit 69517138 authored Dec 13, 2017 by Grzegorz Daniluk
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Showing with 128 additions and 217 deletions

component.xml board/fasec/component.xml +64 -39

wrc_board_fasec_ip.tcl syn/wrc_board_fasec_ip/wrc_board_fasec_ip.tcl +64 -178

No files found.
--- a/board/fasec/component.xml
+++ b/board/fasec/component.xml
@@ -3,7 +3,7 @@
  <spirit:vendor>CERN</spirit:vendor>
  <spirit:library>white_rabbit</spirit:library>
  <spirit:name>wrc_board_fasec</spirit:name>
-  <spirit:version>4.1</spirit:version>
+  <spirit:version>4.2</spirit:version>
  <spirit:busInterfaces>
    <spirit:busInterface>
      <spirit:name>s00_axi</spirit:name>
@@ -485,7 +485,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>0649a5f4</spirit:value>
+            <spirit:value>1f7cf57a</spirit:value>
          </spirit:parameter>
        </spirit:parameters>
      </spirit:view>
@@ -501,7 +501,7 @@
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>3365b256</spirit:value>
+            <spirit:value>9505b84d</spirit:value>
          </spirit:parameter>
        </spirit:parameters>
      </spirit:view>
@@ -1947,10 +1947,6 @@
        <spirit:name>modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
-      <spirit:file>
-        <spirit:name>modules/wrc_core/xwr_syscon_wb.vhd</spirit:name>
-        <spirit:fileType>vhdlSource</spirit:fileType>
-      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_streamers/streamers_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
@@ -1971,6 +1967,10 @@
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
+      <spirit:file>
+        <spirit:name>platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper_gtrxreset_seq.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
@@ -2076,35 +2076,35 @@
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
-        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd</spirit:name>
+        <spirit:name>platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper_gt.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
-        <spirit:name>ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd</spirit:name>
+        <spirit:name>platform/xilinx/wr_gtp_phy/spartan6/whiterabbitgtp_wrapper_tile_spartan6.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
-        <spirit:name>ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd</spirit:name>
+        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
-        <spirit:name>platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd</spirit:name>
+        <spirit:name>ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
-        <spirit:name>modules/wrc_core/wr_core.vhd</spirit:name>
+        <spirit:name>ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
-        <spirit:name>ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd</spirit:name>
+        <spirit:name>modules/wrc_core/wr_core.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
-        <spirit:name>ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd</spirit:name>
+        <spirit:name>ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
-        <spirit:name>platform/xilinx/wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd</spirit:name>
+        <spirit:name>ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
@@ -2128,7 +2128,15 @@
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
-        <spirit:name>platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd</spirit:name>
+        <spirit:name>platform/xilinx/wr_gtp_phy/spartan6/gtp_phase_align.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>platform/xilinx/wr_gtp_phy/family7-gtx/whiterabbit_gtxe2_channel_wrapper_gt.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
@@ -2152,11 +2160,15 @@
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
-        <spirit:name>platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd</spirit:name>
+        <spirit:name>platform/xilinx/wr_gtp_phy/family7-gtp/wr_gtp_phy_family7.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>platform/xilinx/wr_gtp_phy/family7-gtx/wr_gtx_phy_family7.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
-        <spirit:name>platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd</spirit:name>
+        <spirit:name>platform/xilinx/wr_gtp_phy/spartan6/wr_gtp_phy_spartan6.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
@@ -2635,10 +2647,6 @@
        <spirit:name>modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
-      <spirit:file>
-        <spirit:name>modules/wrc_core/xwr_syscon_wb.vhd</spirit:name>
-        <spirit:fileType>vhdlSource</spirit:fileType>
-      </spirit:file>
      <spirit:file>
        <spirit:name>modules/wr_streamers/streamers_pkg.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
@@ -2659,6 +2667,10 @@
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
+      <spirit:file>
+        <spirit:name>platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper_gtrxreset_seq.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+      </spirit:file>
      <spirit:file>
        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
@@ -2764,35 +2776,35 @@
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
-        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd</spirit:name>
+        <spirit:name>platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper_gt.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
-        <spirit:name>ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd</spirit:name>
+        <spirit:name>platform/xilinx/wr_gtp_phy/spartan6/whiterabbitgtp_wrapper_tile_spartan6.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
-        <spirit:name>ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd</spirit:name>
+        <spirit:name>ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
-        <spirit:name>platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd</spirit:name>
+        <spirit:name>ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
-        <spirit:name>modules/wrc_core/wr_core.vhd</spirit:name>
+        <spirit:name>ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
-        <spirit:name>ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd</spirit:name>
+        <spirit:name>modules/wrc_core/wr_core.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
-        <spirit:name>ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd</spirit:name>
+        <spirit:name>ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
-        <spirit:name>platform/xilinx/wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd</spirit:name>
+        <spirit:name>ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
@@ -2816,7 +2828,15 @@
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
-        <spirit:name>platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd</spirit:name>
+        <spirit:name>platform/xilinx/wr_gtp_phy/spartan6/gtp_phase_align.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>platform/xilinx/wr_gtp_phy/family7-gtx/whiterabbit_gtxe2_channel_wrapper_gt.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
@@ -2840,11 +2860,15 @@
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
-        <spirit:name>platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd</spirit:name>
+        <spirit:name>platform/xilinx/wr_gtp_phy/family7-gtp/wr_gtp_phy_family7.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>platform/xilinx/wr_gtp_phy/family7-gtx/wr_gtx_phy_family7.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
-        <spirit:name>platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd</spirit:name>
+        <spirit:name>platform/xilinx/wr_gtp_phy/spartan6/wr_gtp_phy_spartan6.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
      <spirit:file>
@@ -2926,7 +2950,7 @@
      </spirit:file>
    </spirit:fileSet>
  </spirit:fileSets>
-  <spirit:description>wrc_board_fasec_v4_1</spirit:description>
+  <spirit:description>wrc_board_fasec_v4_2</spirit:description>
  <spirit:parameters>
    <spirit:parameter>
      <spirit:name>g_simulation</spirit:name>
@@ -2989,25 +3013,26 @@
        <xilinx:taxonomy>/Communication_&amp;_Networking/Ethernet</xilinx:taxonomy>
        <xilinx:taxonomy>/Communication_&amp;_Networking/Networking</xilinx:taxonomy>
      </xilinx:taxonomies>
-      <xilinx:displayName>wrc_board_fasec_v4_1</xilinx:displayName>
+      <xilinx:displayName>wrc_board_fasec_v4_2</xilinx:displayName>
      <xilinx:definitionSource>package_project</xilinx:definitionSource>
      <xilinx:vendorDisplayName>CERN BE-CO-HT</xilinx:vendorDisplayName>
      <xilinx:vendorURL>https://www.ohwr.org/projects/wr-cores/wiki/wrpc_core</xilinx:vendorURL>
-      <xilinx:coreRevision>4</xilinx:coreRevision>
+      <xilinx:coreRevision>6</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2017-11-30T13:45:28Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2017-12-13T15:47:09Z</xilinx:coreCreationDateTime>
      <xilinx:tags>
        <xilinx:tag xilinx:name="user.org:user:wrc_board_fasec:1.0_ARCHIVE_LOCATION">/home/greg/wr/wr-cores</xilinx:tag>
        <xilinx:tag xilinx:name="CERN:user:wrc_board_fasec:1.0_ARCHIVE_LOCATION">/home/greg/wr/wr-cores</xilinx:tag>
        <xilinx:tag xilinx:name="CERN:white_rabbit:wrc_board_fasec:1.0_ARCHIVE_LOCATION">/home/greg/wr/wr-cores</xilinx:tag>
        <xilinx:tag xilinx:name="CERN:white_rabbit:wrc_board_fasec:4.1_ARCHIVE_LOCATION">/home/greg/wr/wr-cores</xilinx:tag>
+        <xilinx:tag xilinx:name="CERN:white_rabbit:wrc_board_fasec:4.2_ARCHIVE_LOCATION">/home/greg/wr/wr-cores</xilinx:tag>
      </xilinx:tags>
    </xilinx:coreExtensions>
    <xilinx:packagingInfo>
      <xilinx:xilinxVersion>2016.4</xilinx:xilinxVersion>
      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="8250889b"/>
      <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="115d9c61"/>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="5a92504c"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="e4064f8e"/>
-      <xilinx:checksum xilinx:scope="ports" xilinx:value="6a9e6a93"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="bd589f87"/>
      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="c3b40ce5"/>
      <xilinx:checksum xilinx:scope="parameters" xilinx:value="5460d5ef"/>
    </xilinx:packagingInfo>

--- a/syn/wrc_board_fasec_ip/wrc_board_fasec_ip.tcl
+++ b/syn/wrc_board_fasec_ip/wrc_board_fasec_ip.tcl
@@ -3,7 +3,7 @@
 #
 # wrc_board_fasec_ip.tcl: Tcl script for re-creating project 'wrc_board_fasec_ip'
 #
-# Generated by Vivado on Thu Aug 17 18:27:57 CEST 2017
+# Generated by Vivado on Wed Dec 13 16:35:51 CET 2017
 # IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
 #
 # This file contains the Vivado Tcl commands for re-creating the project to the state*
@@ -104,7 +104,6 @@
 #    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_tx_path.vhd"
 #    "/home/greg/wr/wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd"
 #    "/home/greg/wr/wr-cores/modules/wr_endpoint/ep_rx_path.vhd"
-#    "/home/greg/wr/wr-cores/modules/wrc_core/wrc_syscon_wb.vhd"
 #    "/home/greg/wr/wr-cores/modules/wrc_core/wrc_diags_wb.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v"
 #    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd"
@@ -117,6 +116,7 @@
 #    "/home/greg/wr/wr-cores/modules/wr_pps_gen/pps_gen_wb.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v"
 #    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v"
+#    "/home/greg/wr/wr-cores/modules/wrc_core/wrc_syscon_wb.vhd"
 #    "/home/greg/wr/wr-cores/modules/wr_pps_gen/wr_pps_gen.vhd"
 #    "/home/greg/wr/wr-cores/modules/wr_endpoint/wr_endpoint.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd"
@@ -124,13 +124,13 @@
 #    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd"
 #    "/home/greg/wr/wr-cores/modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd"
-#    "/home/greg/wr/wr-cores/modules/wrc_core/xwr_syscon_wb.vhd"
 #    "/home/greg/wr/wr-cores/modules/wr_streamers/streamers_pkg.vhd"
 #    "/home/greg/wr/wr-cores/modules/wrc_core/xwrc_diags_wb.vhd"
 #    "/home/greg/wr/wr-cores/modules/wr_softpll_ng/wr_softpll_ng.vhd"
 #    "/home/greg/wr/wr-cores/modules/wr_mini_nic/wr_mini_nic.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v"
+#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper_gtrxreset_seq.vhd"
 #    "/home/greg/wr/wr-cores/modules/wr_streamers/xtx_streamers_stats.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd"
 #    "/home/greg/wr/wr-cores/modules/wr_streamers/escape_detector.vhd"
@@ -157,32 +157,35 @@
 #    "/home/greg/wr/wr-cores/modules/wr_streamers/streamers_priv_pkg.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd"
+#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper_gt.vhd"
+#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/spartan6/whiterabbitgtp_wrapper_tile_spartan6.vhd"
+#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd"
+#    "/home/greg/wr/wr-cores/modules/wr_tbi_phy/disparity_gen_pkg.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd"
-#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd"
 #    "/home/greg/wr/wr-cores/modules/wrc_core/wr_core.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd"
-#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd"
 #    "/home/greg/wr/wr-cores/modules/wr_streamers/xrtx_streamers_stats.vhd"
-#    "/home/greg/wr/wr-cores/modules/wr_tbi_phy/disparity_gen_pkg.vhd"
 #    "/home/greg/wr/wr-cores/modules/wr_streamers/xtx_streamer.vhd"
 #    "/home/greg/wr/wr-cores/modules/wr_streamers/wr_streamers_wb.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd"
-#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_tx.vhd"
-#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd"
 #    "/home/greg/wr/wr-cores/modules/wr_streamers/xrx_streamer.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/axi4_pkg.vhd"
+#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/spartan6/gtp_phase_align.vhd"
+#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/family7-gtx/whiterabbit_gtxe2_channel_wrapper_gt.vhd"
+#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper.vhd"
 #    "/home/greg/wr/wr-cores/platform/xilinx/wr_xilinx_pkg.vhd"
-#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd"
-#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd"
 #    "/home/greg/wr/wr-cores/modules/wrc_core/xwr_core.vhd"
 #    "/home/greg/wr/wr-cores/modules/wr_dacs/spec_serial_dac.vhd"
 #    "/home/greg/wr/wr-cores/board/common/wr_board_pkg.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_ethernet_slave.vhd"
 #    "/home/greg/wr/wr-cores/modules/wr_streamers/xwr_streamers.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd"
+#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/family7-gtp/wr_gtp_phy_family7.vhd"
+#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/family7-gtx/wr_gtx_phy_family7.vhd"
+#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/spartan6/wr_gtp_phy_spartan6.vhd"
 #    "/home/greg/wr/wr-cores/modules/wr_dacs/spec_serial_dac_arb.vhd"
 #    "/home/greg/wr/wr-cores/board/common/xwrc_board_common.vhd"
 #    "/home/greg/wr/wr-cores/board/fasec/wr_fasec_pkg.vhd"
@@ -191,7 +194,6 @@
 #    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd"
 #    "/home/greg/wr/wr-cores/board/fasec/xwrc_board_fasec.vhd"
 #    "/home/greg/wr/wr-cores/board/fasec/wrc_board_fasec.vhd"
-#    "/home/greg/wr/wr-cores/ip_cores/vme64x-core/hdl/vme64x-core/rtl/xvme64x_core_pkg.vhd"
 #    "/home/greg/wr/wr-cores/modules/wr_eca/eca_free.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_fifos.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd"
@@ -201,13 +203,10 @@
 #    "/home/greg/wr/wr-cores/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd"
 #    "/home/greg/wr/wr-cores/modules/wr_eca/eca_ac_wbm_auto.vhd"
-#    "/home/greg/wr/wr-cores/ip_cores/vme64x-core/hdl/vme64x-core/rtl/xvme64x_core.vhd"
-#    "/home/greg/wr/wr-cores/ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_bus.vhd"
 #    "/home/greg/wr/wr-cores/modules/wr_eca/eca_wb_event.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_raw_slave.vhd"
-#    "/home/greg/wr/wr-cores/ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Am_Match.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/common/gc_async_signals_input_stage.vhd"
 #    "/home/greg/wr/wr-cores/modules/wr_tlu/tlu.vhd"
@@ -218,7 +217,6 @@
 #    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd"
-#    "/home/greg/wr/wr-cores/ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CRAM.vhd"
 #    "/home/greg/wr/wr-cores/modules/wr_eca/eca_queue.vhd"
 #    "/home/greg/wr/wr-cores/modules/wr_eca/eca_auto_pkg.vhd"
 #    "/home/greg/wr/wr-cores/modules/fabric/xwrf_loopback/lbk_wishbone_controller.vhd"
@@ -228,7 +226,6 @@
 #    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/common/gc_moving_average.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_master_core/eb_commit_len_fifo.vhd"
 #    "/home/greg/wr/wr-cores/modules/wr_eca/eca_tag_channel.vhd"
-#    "/home/greg/wr/wr-cores/ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CSR_pack.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/common/gc_serial_dac.vhd"
 #    "/home/greg/wr/wr-cores/modules/wr_si57x_interface/xwr_si57x_interface.vhd"
 #    "/home/greg/wr/wr-cores/modules/wr_tbi_phy/dec_8b10b.vhd"
@@ -245,13 +242,11 @@
 #    "/home/greg/wr/wr-cores/modules/fabric/xwrf_loopback/lbk_pkg.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_pkg.vhd"
-#    "/home/greg/wr/wr-cores/ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CR_pack.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v"
 #    "/home/greg/wr/wr-cores/modules/wr_eca/eca_ac_wbm_auto_pkg.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd"
 #    "/home/greg/wr/wr-cores/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd"
-#    "/home/greg/wr/wr-cores/ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Funct_Match.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_master_core/eb_master_top.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd"
@@ -262,10 +257,8 @@
 #    "/home/greg/wr/wr-cores/ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd"
 #    "/home/greg/wr/wr-cores/modules/wr_softpll_ng/spll_period_detect.vhd"
 #    "/home/greg/wr/wr-cores/modules/wr_eca/eca_ac_wbm.vhd"
-#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_virtex6.vhd"
 #    "/home/greg/wr/wr-cores/modules/timing/pulse_gen.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd"
-#    "/home/greg/wr/wr-cores/ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/common/gc_single_reset_gen.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd"
 #    "/home/greg/wr/wr-cores/modules/wr_eca/eca_search.vhd"
@@ -289,12 +282,9 @@
 #    "/home/greg/wr/wr-cores/modules/fabric/xwrf_reg.vhd"
 #    "/home/greg/wr/wr-cores/modules/wr_si57x_interface/si570_if_wb.vhd"
 #    "/home/greg/wr/wr-cores/modules/wr_eca/eca_adder.vhd"
-#    "/home/greg/wr/wr-cores/ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_SharedComps.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd"
 #    "/home/greg/wr/wr-cores/modules/wr_eca/eca_piso_fifo.vhd"
-#    "/home/greg/wr/wr-cores/modules/wrc_core/wrc_dpram.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd"
-#    "/home/greg/wr/wr-cores/ip_cores/vme64x-core/hdl/vme64x-core/rtl/vme64x_pack.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/gn4124-core/hdl/spec/ip_cores/l2p_fifo.ngc"
 #    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd"
 #    "/home/greg/wr/wr-cores/modules/wr_eca/eca_tlu_auto.vhd"
@@ -302,10 +292,8 @@
 #    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/common/gc_glitch_filt.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/common/gc_word_packer.vhd"
-#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtx_wrapper_gtx.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/common/gc_i2c_slave.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd"
-#    "/home/greg/wr/wr-cores/ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Init.vhd"
 #    "/home/greg/wr/wr-cores/modules/wr_eca/eca_sdp.vhd"
 #    "/home/greg/wr/wr-cores/modules/wr_eca/eca_data.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_crossbar/wb_skidpad.vhd"
@@ -321,7 +309,6 @@
 #    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd"
 #    "/home/greg/wr/wr-cores/modules/wr_eca/eca_walker.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wbgenplus/wbgenplus_pkg.vhd"
-#    "/home/greg/wr/wr-cores/ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Wb_master.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd"
 #    "/home/greg/wr/wr-cores/modules/wr_eca/eca_tlu_fsm.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_master_core/eb_record_gen.vhd"
@@ -332,27 +319,22 @@
 #    "/home/greg/wr/wr-cores/modules/wr_eca/eca_offset.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd"
-#    "/home/greg/wr/wr-cores/ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME64xCore_Top.vhd"
-#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/gtx_reset.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd"
 #    "/home/greg/wr/wr-cores/modules/wr_eca/eca_scan.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd"
 #    "/home/greg/wr/wr-cores/modules/wr_eca/eca_scubus_channel.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v"
 #    "/home/greg/wr/wr-cores/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd"
-#    "/home/greg/wr/wr-cores/ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Access_Decode.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd"
 #    "/home/greg/wr/wr-cores/modules/wr_eca/eca_rmw.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd"
-#    "/home/greg/wr/wr-cores/ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_IRQ_Controller.vhd"
 #    "/home/greg/wr/wr-cores/modules/wr_eca/eca_tlu_auto_pkg.vhd"
 #    "/home/greg/wr/wr-cores/modules/wr_tbi_phy/wr_tbi_phy.vhd"
 #    "/home/greg/wr/wr-cores/platform/xilinx/chipscope/chipscope_ila.ngc"
 #    "/home/greg/wr/wr-cores/modules/wr_eca/eca_queue_auto_pkg.vhd"
 #    "/home/greg/wr/wr-cores/modules/timing/hpll_period_detect.vhd"
-#    "/home/greg/wr/wr-cores/platform/xilinx/wr_gtp_phy/gtp_phase_align_virtex6.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v"
 #    "/home/greg/wr/wr-cores/ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_decode32.vhd"
@@ -363,7 +345,6 @@
 #    "/home/greg/wr/wr-cores/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd"
-#    "/home/greg/wr/wr-cores/ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_swapper.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd"
 #    "/home/greg/wr/wr-cores/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd"
 #    "/home/greg/wr/wr-cores/modules/wr_eca/eca_tdp.vhd"
@@ -547,7 +528,6 @@ set files [list \
 "[file normalize "$origin_dir/../../modules/wr_endpoint/ep_tx_path.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_mini_nic/minic_wb_slave.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_endpoint/ep_rx_path.vhd"]"\
- "[file normalize "$origin_dir/../../modules/wrc_core/wrc_syscon_wb.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wrc_core/wrc_diags_wb.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v"]"\
 "[file normalize "$origin_dir/../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd"]"\
@@ -560,6 +540,7 @@ set files [list \
 "[file normalize "$origin_dir/../../modules/wr_pps_gen/pps_gen_wb.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v"]"\
+ "[file normalize "$origin_dir/../../modules/wrc_core/wrc_syscon_wb.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_pps_gen/wr_pps_gen.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_endpoint/wr_endpoint.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd"]"\
@@ -567,13 +548,13 @@ set files [list \
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd"]"\
- "[file normalize "$origin_dir/../../modules/wrc_core/xwr_syscon_wb.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_streamers/streamers_pkg.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wrc_core/xwrc_diags_wb.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_softpll_ng/wr_softpll_ng.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_mini_nic/wr_mini_nic.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v"]"\
+ "[file normalize "$origin_dir/../../platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper_gtrxreset_seq.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_streamers/xtx_streamers_stats.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_streamers/escape_detector.vhd"]"\
@@ -600,32 +581,35 @@ set files [list \
 "[file normalize "$origin_dir/../../modules/wr_streamers/streamers_priv_pkg.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd"]"\
+ "[file normalize "$origin_dir/../../platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper_gt.vhd"]"\
+ "[file normalize "$origin_dir/../../platform/xilinx/wr_gtp_phy/spartan6/whiterabbitgtp_wrapper_tile_spartan6.vhd"]"\
+ "[file normalize "$origin_dir/../../platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd"]"\
+ "[file normalize "$origin_dir/../../modules/wr_tbi_phy/disparity_gen_pkg.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd"]"\
- "[file normalize "$origin_dir/../../platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wrc_core/wr_core.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd"]"\
- "[file normalize "$origin_dir/../../platform/xilinx/wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_streamers/xrtx_streamers_stats.vhd"]"\
- "[file normalize "$origin_dir/../../modules/wr_tbi_phy/disparity_gen_pkg.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_streamers/xtx_streamer.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_streamers/wr_streamers_wb.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd"]"\
- "[file normalize "$origin_dir/../../platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_tx.vhd"]"\
- "[file normalize "$origin_dir/../../platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_streamers/xrx_streamer.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/axi4_pkg.vhd"]"\
+ "[file normalize "$origin_dir/../../platform/xilinx/wr_gtp_phy/spartan6/gtp_phase_align.vhd"]"\
+ "[file normalize "$origin_dir/../../platform/xilinx/wr_gtp_phy/family7-gtx/whiterabbit_gtxe2_channel_wrapper_gt.vhd"]"\
+ "[file normalize "$origin_dir/../../platform/xilinx/wr_gtp_phy/family7-gtp/whiterabbit_gtpe2_channel_wrapper.vhd"]"\
 "[file normalize "$origin_dir/../../platform/xilinx/wr_xilinx_pkg.vhd"]"\
- "[file normalize "$origin_dir/../../platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd"]"\
- "[file normalize "$origin_dir/../../platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wrc_core/xwr_core.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_dacs/spec_serial_dac.vhd"]"\
 "[file normalize "$origin_dir/../../board/common/wr_board_pkg.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_ethernet_slave.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_streamers/xwr_streamers.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd"]"\
+ "[file normalize "$origin_dir/../../platform/xilinx/wr_gtp_phy/family7-gtp/wr_gtp_phy_family7.vhd"]"\
+ "[file normalize "$origin_dir/../../platform/xilinx/wr_gtp_phy/family7-gtx/wr_gtx_phy_family7.vhd"]"\
+ "[file normalize "$origin_dir/../../platform/xilinx/wr_gtp_phy/spartan6/wr_gtp_phy_spartan6.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_dacs/spec_serial_dac_arb.vhd"]"\
 "[file normalize "$origin_dir/../../board/common/xwrc_board_common.vhd"]"\
 "[file normalize "$origin_dir/../../board/fasec/wr_fasec_pkg.vhd"]"\
@@ -634,7 +618,6 @@ set files [list \
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd"]"\
 "[file normalize "$origin_dir/../../board/fasec/xwrc_board_fasec.vhd"]"\
 "[file normalize "$origin_dir/../../board/fasec/wrc_board_fasec.vhd"]"\
- "[file normalize "$origin_dir/../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/xvme64x_core_pkg.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_eca/eca_free.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_fifos.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd"]"\
@@ -644,13 +627,10 @@ set files [list \
 "[file normalize "$origin_dir/../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_eca/eca_ac_wbm_auto.vhd"]"\
- "[file normalize "$origin_dir/../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/xvme64x_core.vhd"]"\
- "[file normalize "$origin_dir/../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_bus.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_eca/eca_wb_event.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_raw_slave.vhd"]"\
- "[file normalize "$origin_dir/../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Am_Match.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/common/gc_async_signals_input_stage.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_tlu/tlu.vhd"]"\
@@ -661,7 +641,6 @@ set files [list \
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd"]"\
- "[file normalize "$origin_dir/../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CRAM.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_eca/eca_queue.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_eca/eca_auto_pkg.vhd"]"\
 "[file normalize "$origin_dir/../../modules/fabric/xwrf_loopback/lbk_wishbone_controller.vhd"]"\
@@ -671,7 +650,6 @@ set files [list \
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/common/gc_moving_average.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/etherbone-core/hdl/eb_master_core/eb_commit_len_fifo.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_eca/eca_tag_channel.vhd"]"\
- "[file normalize "$origin_dir/../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CSR_pack.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_si57x_interface/xwr_si57x_interface.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_tbi_phy/dec_8b10b.vhd"]"\
@@ -688,13 +666,11 @@ set files [list \
 "[file normalize "$origin_dir/../../modules/fabric/xwrf_loopback/lbk_pkg.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_pkg.vhd"]"\
- "[file normalize "$origin_dir/../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CR_pack.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v"]"\
 "[file normalize "$origin_dir/../../modules/wr_eca/eca_ac_wbm_auto_pkg.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd"]"\
- "[file normalize "$origin_dir/../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Funct_Match.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_top.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd"]"\
@@ -705,10 +681,8 @@ set files [list \
 "[file normalize "$origin_dir/../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_softpll_ng/spll_period_detect.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_eca/eca_ac_wbm.vhd"]"\
- "[file normalize "$origin_dir/../../platform/xilinx/wr_gtp_phy/wr_gtx_phy_virtex6.vhd"]"\
 "[file normalize "$origin_dir/../../modules/timing/pulse_gen.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd"]"\
- "[file normalize "$origin_dir/../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/common/gc_single_reset_gen.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_eca/eca_search.vhd"]"\
@@ -732,12 +706,9 @@ set files [list \
 "[file normalize "$origin_dir/../../modules/fabric/xwrf_reg.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_si57x_interface/si570_if_wb.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_eca/eca_adder.vhd"]"\
- "[file normalize "$origin_dir/../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_SharedComps.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_eca/eca_piso_fifo.vhd"]"\
- "[file normalize "$origin_dir/../../modules/wrc_core/wrc_dpram.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd"]"\
- "[file normalize "$origin_dir/../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/vme64x_pack.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/gn4124-core/hdl/spec/ip_cores/l2p_fifo.ngc"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_eca/eca_tlu_auto.vhd"]"\
@@ -745,10 +716,8 @@ set files [list \
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/common/gc_word_packer.vhd"]"\
- "[file normalize "$origin_dir/../../platform/xilinx/wr_gtp_phy/whiterabbitgtx_wrapper_gtx.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd"]"\
- "[file normalize "$origin_dir/../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Init.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_eca/eca_sdp.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_eca/eca_data.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_crossbar/wb_skidpad.vhd"]"\
@@ -764,7 +733,6 @@ set files [list \
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_eca/eca_walker.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wbgenplus/wbgenplus_pkg.vhd"]"\
- "[file normalize "$origin_dir/../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Wb_master.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_eca/eca_tlu_fsm.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/etherbone-core/hdl/eb_master_core/eb_record_gen.vhd"]"\
@@ -775,27 +743,22 @@ set files [list \
 "[file normalize "$origin_dir/../../modules/wr_eca/eca_offset.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd"]"\
- "[file normalize "$origin_dir/../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME64xCore_Top.vhd"]"\
- "[file normalize "$origin_dir/../../platform/xilinx/wr_gtp_phy/gtx_reset.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_eca/eca_scan.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_eca/eca_scubus_channel.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v"]"\
 "[file normalize "$origin_dir/../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd"]"\
- "[file normalize "$origin_dir/../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Access_Decode.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_eca/eca_rmw.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd"]"\
- "[file normalize "$origin_dir/../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_IRQ_Controller.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_eca/eca_tlu_auto_pkg.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_tbi_phy/wr_tbi_phy.vhd"]"\
 "[file normalize "$origin_dir/../../platform/xilinx/chipscope/chipscope_ila.ngc"]"\
 "[file normalize "$origin_dir/../../modules/wr_eca/eca_queue_auto_pkg.vhd"]"\
 "[file normalize "$origin_dir/../../modules/timing/hpll_period_detect.vhd"]"\
- "[file normalize "$origin_dir/../../platform/xilinx/wr_gtp_phy/gtp_phase_align_virtex6.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v"]"\
 "[file normalize "$origin_dir/../../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_decode32.vhd"]"\
@@ -806,7 +769,6 @@ set files [list \
 "[file normalize "$origin_dir/../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd"]"\
- "[file normalize "$origin_dir/../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_swapper.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd"]"\
 "[file normalize "$origin_dir/../../modules/wr_eca/eca_tdp.vhd"]"\
@@ -1128,10 +1090,6 @@ set file "wr_endpoint/ep_rx_path.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
-set file "wrc_core/wrc_syscon_wb.vhd"
-set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
-set_property "file_type" "VHDL" $file_obj
 set file "wrc_core/wrc_diags_wb.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
@@ -1164,6 +1122,10 @@ set file "wr_pps_gen/pps_gen_wb.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
+set file "wrc_core/wrc_syscon_wb.vhd"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property "file_type" "VHDL" $file_obj
 set file "wr_pps_gen/wr_pps_gen.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
@@ -1192,10 +1154,6 @@ set file "wr_streamers/wr_streamers_wbgen2_pkg.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
-set file "wrc_core/xwr_syscon_wb.vhd"
-set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
-set_property "file_type" "VHDL" $file_obj
 set file "wr_streamers/streamers_pkg.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
@@ -1216,6 +1174,10 @@ set file "wb_onewire_master/xwb_onewire_master.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
+set file "family7-gtp/whiterabbit_gtpe2_channel_wrapper_gtrxreset_seq.vhd"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property "file_type" "VHDL" $file_obj
 set file "wr_streamers/xtx_streamers_stats.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
@@ -1320,55 +1282,55 @@ set file "wb_crossbar/xwb_sdb_crossbar.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
-set file "eb_slave_core/eb_stream_widen.vhd"
+set file "family7-gtp/whiterabbit_gtpe2_channel_wrapper_gt.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
-set file "eb_slave_core/eb_eth_rx.vhd"
+set file "spartan6/whiterabbitgtp_wrapper_tile_spartan6.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
-set file "wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd"
+set file "wr_gtp_phy/gtp_bitslide.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
-set file "wrc_core/wr_core.vhd"
+set file "wr_tbi_phy/disparity_gen_pkg.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
-set file "eb_slave_core/eb_slave_top.vhd"
+set file "eb_slave_core/eb_stream_widen.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
-set file "eb_slave_core/eb_stream_narrow.vhd"
+set file "eb_slave_core/eb_eth_rx.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
-set file "wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd"
+set file "wrc_core/wr_core.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
-set file "wr_streamers/xrtx_streamers_stats.vhd"
+set file "eb_slave_core/eb_slave_top.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
-set file "wr_tbi_phy/disparity_gen_pkg.vhd"
+set file "eb_slave_core/eb_stream_narrow.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
-set file "wr_streamers/xtx_streamer.vhd"
+set file "wr_streamers/xrtx_streamers_stats.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
-set file "wr_streamers/wr_streamers_wb.vhd"
+set file "wr_streamers/xtx_streamer.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
-set file "eb_slave_core/etherbone_pkg.vhd"
+set file "wr_streamers/wr_streamers_wb.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
-set file "wr_gtp_phy/gtp_phase_align.vhd"
+set file "eb_slave_core/etherbone_pkg.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
@@ -1376,27 +1338,27 @@ set file "eb_slave_core/eb_eth_tx.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
-set file "wr_gtp_phy/gtp_bitslide.vhd"
+set file "wr_streamers/xrx_streamer.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
-set file "wr_streamers/xrx_streamer.vhd"
+set file "wb_axi4lite_bridge/axi4_pkg.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
-set file "wb_axi4lite_bridge/axi4_pkg.vhd"
+set file "spartan6/gtp_phase_align.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
-set file "xilinx/wr_xilinx_pkg.vhd"
+set file "family7-gtx/whiterabbit_gtxe2_channel_wrapper_gt.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
-set file "wr_gtp_phy/wr_gtx_phy_kintex7.vhd"
+set file "family7-gtp/whiterabbit_gtpe2_channel_wrapper.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
-set file "wr_gtp_phy/wr_gtp_phy_spartan6.vhd"
+set file "xilinx/wr_xilinx_pkg.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
@@ -1424,6 +1386,18 @@ set file "wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
+set file "family7-gtp/wr_gtp_phy_family7.vhd"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property "file_type" "VHDL" $file_obj
+set file "family7-gtx/wr_gtx_phy_family7.vhd"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property "file_type" "VHDL" $file_obj
+set file "spartan6/wr_gtp_phy_spartan6.vhd"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property "file_type" "VHDL" $file_obj
 set file "wr_dacs/spec_serial_dac_arb.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
@@ -1456,10 +1430,6 @@ set file "fasec/wrc_board_fasec.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
-set file "rtl/xvme64x_core_pkg.vhd"
-set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
-set_property "file_type" "VHDL" $file_obj
 set file "wr_eca/eca_free.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
@@ -1496,14 +1466,6 @@ set file "wr_eca/eca_ac_wbm_auto.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
-set file "rtl/xvme64x_core.vhd"
-set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
-set_property "file_type" "VHDL" $file_obj
-set file "rtl/VME_bus.vhd"
-set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
-set_property "file_type" "VHDL" $file_obj
 set file "wr_eca/eca_wb_event.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
@@ -1520,10 +1482,6 @@ set file "eb_slave_core/eb_raw_slave.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
-set file "rtl/VME_Am_Match.vhd"
-set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
-set_property "file_type" "VHDL" $file_obj
 set file "wb_i2c_master/wb_i2c_master.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
@@ -1564,10 +1522,6 @@ set file "wb_dma/xwb_dma.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
-set file "rtl/VME_CRAM.vhd"
-set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
-set_property "file_type" "VHDL" $file_obj
 set file "wr_eca/eca_queue.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
@@ -1604,10 +1558,6 @@ set file "wr_eca/eca_tag_channel.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
-set file "rtl/VME_CSR_pack.vhd"
-set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
-set_property "file_type" "VHDL" $file_obj
 set file "common/gc_serial_dac.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
@@ -1672,10 +1622,6 @@ set file "eb_usb_core/ez_usb_pkg.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
-set file "rtl/VME_CR_pack.vhd"
-set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
-set_property "file_type" "VHDL" $file_obj
 set file "wr_eca/eca_ac_wbm_auto_pkg.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
@@ -1692,10 +1638,6 @@ set file "wb_irq/wb_irq_lm32.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
-set file "rtl/VME_Funct_Match.vhd"
-set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
-set_property "file_type" "VHDL" $file_obj
 set file "wb_xil_multiboot/multiboot_fsm.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
@@ -1736,10 +1678,6 @@ set file "wr_eca/eca_ac_wbm.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
-set file "wr_gtp_phy/wr_gtx_phy_virtex6.vhd"
-set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
-set_property "file_type" "VHDL" $file_obj
 set file "timing/pulse_gen.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
@@ -1748,10 +1686,6 @@ set file "spartan6/gn4124_core.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
-set file "rtl/VME_CR_CSR_Space.vhd"
-set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
-set_property "file_type" "VHDL" $file_obj
 set file "common/gc_single_reset_gen.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
@@ -1844,10 +1778,6 @@ set file "wr_eca/eca_adder.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
-set file "rtl/VME_SharedComps.vhd"
-set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
-set_property "file_type" "VHDL" $file_obj
 set file "wb_irq/wb_irq_pkg.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
@@ -1856,18 +1786,10 @@ set file "wr_eca/eca_piso_fifo.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
-set file "wrc_core/wrc_dpram.vhd"
-set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
-set_property "file_type" "VHDL" $file_obj
 set file "wb_xilinx_fpga_loader/xloader_registers_pkg.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
-set file "rtl/vme64x_pack.vhd"
-set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
-set_property "file_type" "VHDL" $file_obj
 set file "ip_cores/l2p_fifo.ngc"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "NGC" $file_obj
@@ -1896,10 +1818,6 @@ set file "common/gc_word_packer.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
-set file "wr_gtp_phy/whiterabbitgtx_wrapper_gtx.vhd"
-set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
-set_property "file_type" "VHDL" $file_obj
 set file "common/gc_i2c_slave.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
@@ -1908,10 +1826,6 @@ set file "wb_vic/wb_slave_vic.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
-set file "rtl/VME_Init.vhd"
-set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
-set_property "file_type" "VHDL" $file_obj
 set file "wr_eca/eca_sdp.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
@@ -1968,10 +1882,6 @@ set file "wbgenplus/wbgenplus_pkg.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
-set file "rtl/VME_Wb_master.vhd"
-set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
-set_property "file_type" "VHDL" $file_obj
 set file "spartan6/p2l_des.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
@@ -2012,14 +1922,6 @@ set file "wb_simple_pwm/simple_pwm_wb.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
-set file "rtl/VME64xCore_Top.vhd"
-set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
-set_property "file_type" "VHDL" $file_obj
-set file "wr_gtp_phy/gtx_reset.vhd"
-set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
-set_property "file_type" "VHDL" $file_obj
 set file "wb_async_bridge/wb_async_bridge.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
@@ -2040,10 +1942,6 @@ set file "spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
-set file "rtl/VME_Access_Decode.vhd"
-set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
-set_property "file_type" "VHDL" $file_obj
 set file "wb_irq/irqm_core.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
@@ -2064,10 +1962,6 @@ set file "wb_spi/wb_spi.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
-set file "rtl/VME_IRQ_Controller.vhd"
-set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
-set_property "file_type" "VHDL" $file_obj
 set file "wr_eca/eca_tlu_auto_pkg.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
@@ -2088,10 +1982,6 @@ set file "timing/hpll_period_detect.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
-set file "wr_gtp_phy/gtp_phase_align_virtex6.vhd"
-set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
-set_property "file_type" "VHDL" $file_obj
 set file "wb_spi_flash/wb_spi_flash.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
@@ -2128,10 +2018,6 @@ set file "spartan6/serdes_1_to_n_data_s2_se.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj
-set file "rtl/VME_swapper.vhd"
-set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
-set_property "file_type" "VHDL" $file_obj
 set file "wb_vic/wb_vic.vhd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property "file_type" "VHDL" $file_obj