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White Rabbit core collection
Commits
69cc4cc3
Commit
69cc4cc3
authored
Dec 18, 2017
by
Grzegorz Daniluk
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project files and Makefiles for WRPC v4.2
parent
598aeff3
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5 changed files
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1365 additions
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1457 deletions
+1365
-1457
Makefile
syn/spec_ref_design/Makefile
+253
-267
spec_wr_ref.xise
syn/spec_ref_design/spec_wr_ref.xise
+329
-371
Makefile
syn/svec_ref_design/Makefile
+256
-270
svec_wr_ref.xise
syn/svec_ref_design/svec_wr_ref.xise
+331
-373
vfchd_wr_ref.qsf
syn/vfchd_ref_design/vfchd_wr_ref.qsf
+196
-176
No files found.
syn/spec_ref_design/Makefile
View file @
69cc4cc3
...
...
@@ -60,352 +60,338 @@ endif
CWD
:=
$(
shell
pwd
)
FILES
:=
../../modules/wr_pps_gen/wr_pps_gen.vhd
\
../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/xvme64x_core_pkg.vhd
\
../../modules/wr_dacs/spec_serial_dac_arb.vhd
\
../../modules/wr_endpoint/ep_wishbone_controller.vhd
\
../../modules/wr_eca/eca_free.vhd
\
../../modules/wr_endpoint/ep_rtu_header_extract.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd
\
../../modules/wr_si57x_interface/xwr_si57x_interface.vhd
\
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_wbm_fifo.vhd
\
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd
\
../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_fifos.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd
\
../../modules/wr_softpll_ng/spll_aligner.vhd
\
../../modules/wr_eca/eca_msi.vhd
\
../../modules/wr_endpoint/wr_endpoint.vhd
\
run.tcl
\
../../modules/wr_tlu/tlu_fsm.vhd
\
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd
\
../../modules/wr_eca/eca_ac_wbm_auto.vhd
\
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd
\
../../board/spec/xwrc_board_spec.vhd
\
spec_wr_ref.xise
\
../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd
\
../../modules/timing/dmtd_phase_meas.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd
\
../../platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd
\
../../ip_cores/vme64x-core/hdl/rtl/vme_user_csr.vhd
\
../../modules/wr_endpoint/ep_sync_detect.vhd
\
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_commit_fifo.vhd
\
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd
\
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd
\
../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_slave_wrapper.vhd
\
../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd
\
../../modules/fabric/xwrf_loopback/wrf_loopback.vhd
\
../../modules/wr_endpoint/ep_tx_inject_ctrl.vhd
\
../../modules/wr_endpoint/ep_wishbone_controller.vhd
\
../../modules/wr_endpoint/endpoint_pkg.vhd
\
../../modules/timing/dmtd_with_deglitcher.vhd
\
../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/xvme64x_core.vhd
\
../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_bus.vhd
\
../../modules/wr_eca/eca_wb_event.vhd
\
../../modules/wrc_core/wrcore_pkg.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd
\
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_raw_slave.vhd
\
../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Am_Match.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd
\
../../ip_cores/general-cores/modules/common/gc_async_signals_input_stage.vhd
\
../../modules/wr_tlu/tlu.vhd
\
../../modules/wr_softpll_ng/spll_wb_slave.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd
\
../../modules/wr_streamers/rx_streamer.vhd
\
../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd
\
../../modules/wr_endpoint/ep_rx_status_reg_insert.vhd
\
../../modules/wr_streamers/xtx_streamers_stats.vhd
\
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd
\
../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd
\
../../modules/wr_endpoint/ep_registers_pkg.vhd
\
../../modules/wr_endpoint/ep_autonegotiation.vhd
\
../../board/common/xwrc_board_common.vhd
\
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd
\
../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd
\
../../modules/wr_endpoint/ep_tx_crc_inserter.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v
\
../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CRAM.vhd
\
../../modules/wr_streamers/escape_detector.vhd
\
../../modules/wr_endpoint/ep_ts_counter.vhd
\
../../modules/wr_eca/eca_queue.vhd
\
../../modules/wr_eca/eca_auto_pkg.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd
\
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_pass_fifo.vhd
\
../../modules/wr_mini_nic/wr_mini_nic.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd
\
../../ip_cores/etherbone-core/hdl/eb_master_core/eb_framer.vhd
\
../../ip_cores/general-cores/modules/common/gc_sync_register.vhd
\
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd
\
../../ip_cores/general-cores/modules/common/gc_moving_average.vhd
\
../../ip_cores/etherbone-core/hdl/eb_master_core/eb_commit_len_fifo.vhd
\
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd
\
../../modules/wr_eca/eca_tag_channel.vhd
\
../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CSR_pack.vhd
\
../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd
\
../../top/spec_ref_design/spec_wr_ref_top.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd
\
../../modules/wr_endpoint/ep_leds_controller.vhd
\
../../modules/wr_endpoint/ep_packet_filter.vhd
\
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd
\
../../modules/wr_si57x_interface/xwr_si57x_interface.vhd
\
../../modules/wr_tbi_phy/dec_8b10b.vhd
\
../../modules/wr_tbi_phy/enc_8b10b.vhd
\
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/pulse_sync_rtl.vhd
\
../../modules/wrc_core/wrc_syscon_pkg.vhd
\
../../modules/wr_eca/eca_tlu_fsm.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd
\
../../ip_cores/etherbone-core/hdl/eb_master_core/eb_record_gen.vhd
\
../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_wb_if.vhd
\
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_split.vhd
\
../../platform/xilinx/chipscope/chipscope_icon.ngc
\
../../platform/xilinx/wr_gtp_phy/spartan6/whiterabbitgtp_wrapper_tile_spartan6.vhd
\
../../modules/wr_eca/eca_free.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd
\
../../modules/wr_endpoint/ep_rtu_header_extract.vhd
\
../../ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd
\
../../modules/wr_endpoint/ep_tx_path.vhd
\
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd
\
../../modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd
\
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd
\
../../modules/wr_endpoint/ep_tx_pcs_16bit.vhd
\
../../modules/wrc_core/wrc_periph.vhd
\
../../modules/wr_eca/eca_pkg.vhd
\
../../ip_cores/vme64x-core/hdl/rtl/vme_irq_controller.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd
\
../../board/spec/wr_spec_pkg.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd
\
../../modules/wr_endpoint/ep_rx_oob_insert.vhd
\
../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd
\
../../ip_cores/general-cores/modules/common/gc_moving_average.vhd
\
../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd
\
../../modules/wr_eca/eca_msi.vhd
\
../../modules/wrc_core/wr_core.vhd
\
../../ip_cores/general-cores/modules/common/gc_reset.vhd
\
../../modules/timing/multi_dmtd_with_deglitcher.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v
\
../../modules/wr_mini_nic/xwr_mini_nic.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd
\
../../modules/wr_endpoint/ep_tx_header_processor.vhd
\
../../ip_cores/general-cores/modules/common/gencores_pkg.vhd
\
../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb.vhd
\
../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_eth_tx.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd
\
../../modules/wr_eca/eca_channel.vhd
\
../../modules/wr_eca/wr_eca.vhd
\
run.tcl
\
../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
\
../../modules/wr_eca/eca_offset.vhd
\
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd
\
../../modules/wr_endpoint/ep_crc32_pkg.vhd
\
../../modules/wr_endpoint/ep_rx_pcs_8bit.vhd
\
../../modules/wr_softpll_ng/spll_wbgen2_pkg.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd
\
../../modules/wr_eca/eca_wb_event.vhd
\
../../modules/wr_tlu/tlu_fsm.vhd
\
../../ip_cores/vme64x-core/hdl/rtl/vme64x_pkg.vhd
\
../../modules/fabric/xwrf_loopback/lbk_pkg.vhd
\
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd
\
../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd
\
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd
\
../../modules/wr_dacs/spec_serial_dac_arb.vhd
\
../../modules/wr_streamers/xrx_streamers_stats.vhd
\
../../ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd
\
../../modules/wr_eca/eca_auto.vhd
\
../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd
\
../../modules/wr_endpoint/ep_rx_crc_size_check.vhd
\
../../platform/xilinx/wr_gtp_phy/spartan6/wr_gtp_phy_spartan6.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd
\
../../modules/wr_tlu/tlu_pkg.vhd
\
../../modules/wr_eca/eca_ac_wbm_auto.vhd
\
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd
\
../../modules/wr_softpll_ng/xwr_softpll_ng.vhd
\
../../board/spec/xwrc_board_spec.vhd
\
../../modules/wr_eca/eca_tlu.vhd
\
../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_pkg.vhd
\
../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_fifos.vhd
\
../../modules/wr_mini_nic/minic_wb_slave.vhd
\
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd
\
../../platform/xilinx/wr_xilinx_pkg.vhd
\
../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CR_pack.vhd
\
../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd
\
../../modules/fabric/wr_fabric_pkg.vhd
\
../../modules/wr_eca/eca_sdp.vhd
\
../../modules/wr_eca/eca_scan.vhd
\
../../modules/wr_streamers/xrtx_streamers_stats.vhd
\
../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd
\
../../modules/wr_endpoint/ep_rx_path.vhd
\
../../modules/wr_streamers/dropping_buffer.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v
\
../../modules/fabric/xwrf_reg.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v
\
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd
\
../../modules/wr_eca/eca_ac_wbm_auto_pkg.vhd
\
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd
\
../../modules/timing/dmtd_phase_meas.vhd
\
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/pulse_sync_rtl.vhd
\
../../modules/wr_endpoint/ep_rx_pcs_16bit.vhd
\
../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd
\
../../modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd
\
../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Funct_Match.vhd
\
../../modules/fabric/xwb_fabric_sink.vhd
\
../../modules/wr_endpoint/ep_rx_wb_master.vhd
\
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd
\
../../platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd
\
../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_top.vhd
\
../../modules/wrc_core/wrc_syscon_wb.vhd
\
../../modules/wr_endpoint/ep_tx_pcs_8bit.vhd
\
../../modules/wr_endpoint/ep_tx_vlan_unit.vhd
\
../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd
\
../../modules/wrc_core/wrc_diags_wb.vhd
\
../../modules/wr_pps_gen/xwr_pps_gen.vhd
\
../../modules/wr_softpll_ng/spll_wbgen2_pkg.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd
\
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_wbm_fifo.vhd
\
../../modules/wr_eca/eca.vhd
\
../../modules/wr_endpoint/endpoint_private_pkg.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v
\
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_register_link.vhd
\
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd
\
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd
\
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd
\
../../platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd
\
../../modules/wr_softpll_ng/spll_period_detect.vhd
\
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd
\
../../modules/wr_eca/eca_ac_wbm.vhd
\
../../platform/xilinx/wr_gtp_phy/wr_gtx_phy_virtex6.vhd
\
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd
\
../../modules/wr_endpoint/ep_clock_alignment_fifo.vhd
\
../../modules/timing/pulse_gen.vhd
\
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd
\
../../ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd
\
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd
\
../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd
\
../../modules/wr_endpoint/ep_1000basex_pcs.vhd
\
../../modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd
\
../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd
\
../../ip_cores/general-cores/modules/common/gc_single_reset_gen.vhd
\
../../ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd
\
../../modules/wr_eca/eca_search.vhd
\
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd
\
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd
\
../../modules/wr_endpoint/ep_rx_bypass_queue.vhd
\
../../modules/wr_streamers/escape_inserter.vhd
\
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tag_fifo.vhd
\
../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd
\
../../modules/wr_streamers/tx_streamer.vhd
\
../../platform/xilinx/wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd
\
../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_slave_wrapper.vhd
\
../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd
\
../../modules/fabric/xwrf_loopback/wrf_loopback.vhd
\
../../modules/wr_endpoint/ep_tx_inject_ctrl.vhd
\
../../modules/wr_tlu/tlu_pkg.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd
\
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_split.vhd
\
../../ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd
\
../../modules/wr_endpoint/ep_rx_oob_insert.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd
\
../../modules/timing/multi_dmtd_with_deglitcher.vhd
\
../../modules/wr_endpoint/ep_tx_header_processor.vhd
\
../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_wb_if.vhd
\
../../modules/wr_endpoint/ep_rx_pcs_8bit.vhd
\
../../modules/wr_eca/eca_channel.vhd
\
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd
\
../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd
\
../../modules/wr_eca/eca_auto.vhd
\
../../modules/wr_eca/eca_tlu.vhd
\
../../modules/wrc_core/xwr_syscon_wb.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd
\
../../modules/wr_endpoint/ep_rx_early_address_match.vhd
\
../../modules/wr_streamers/xrtx_streamers_stats.vhd
\
../../modules/fabric/xwrf_reg.vhd
\
../../modules/wr_eca/eca_scubus_channel.vhd
\
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd
\
../../modules/timing/pulse_stamper.vhd
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../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd
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../../modules/wr_streamers/streamers_pkg.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v
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../../modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd
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../../modules/wr_streamers/rx_streamer.vhd
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../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd
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../../modules/timing/dmtd_with_deglitcher.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd
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../../platform/xilinx/xwrc_platform_xilinx.vhd
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../../modules/wr_endpoint/ep_timestamping_unit.vhd
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../../modules/fabric/xwb_fabric_sink.vhd
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../../modules/wrc_core/wrc_diags_pkg.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd
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../../modules/wr_si57x_interface/si570_if_wb.vhd
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../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd
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../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd
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../../modules/wr_endpoint/ep_rx_wb_master.vhd
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../../ip_cores/vme64x-core/hdl/rtl/vme_bus.vhd
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../../modules/wrc_core/wrcore_pkg.vhd
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../../modules/wr_endpoint/ep_sync_detect_16bit.vhd
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../../modules/wr_eca/eca_adder.vhd
\
../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_SharedComps.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd
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../../modules/wrc_core/xwr_core.vhd
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../../modules/fabric/xwrf_mux.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd
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../../modules/wrc_core/xwrc_diags_wb.vhd
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../../ip_cores/general-cores/modules/common/gc_single_reset_gen.vhd
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../../modules/wr_tlu/tlu.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd
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../../modules/wr_eca/eca_piso_fifo.vhd
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../../modules/wrc_core/wrc_dpram.vhd
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../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_top.vhd
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../../modules/wrc_core/wrc_syscon_wb.vhd
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../../modules/wrc_core/xwr_core.vhd
\
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd
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../../top/spec_ref_design/spec_wr_ref_top.ucf
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../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/vme64x_pack.vhd
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../../ip_cores/general-cores/modules/common/gc_word_packer.vhd
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../../modules/wr_eca/eca_rmw.vhd
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../../modules/wr_endpoint/ep_tx_pcs_8bit.vhd
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../../ip_cores/vme64x-core/hdl/rtl/vme64x_core.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_crossbar/wb_skidpad.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd
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../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd
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../../platform/xilinx/wr_gtp_phy/spartan6/gtp_phase_align.vhd
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../../modules/wr_endpoint/ep_tx_vlan_unit.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd
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../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd
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../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_raw_slave.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd
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../../modules/wr_dacs/spec_serial_dac.vhd
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../../modules/wrc_core/wrc_diags_wb.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd
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../../modules/wr_pps_gen/xwr_pps_gen.vhd
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../../board/common/xwrc_board_common.vhd
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../../ip_cores/gn4124-core/hdl/spec/ip_cores/l2p_fifo.ngc
\
../../ip_cores/general-cores/modules/common/gc_async_signals_input_stage.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd
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../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd
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../../modules/fabric/xwb_fabric_source.vhd
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../../modules/wr_eca/eca_tlu_auto.vhd
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../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd
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../../modules/wr_streamers/dropping_buffer.vhd
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../../modules/wr_softpll_ng/wr_softpll_ng.vhd
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../../modules/wr_tbi_phy/disparity_gen_pkg.vhd
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../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd
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../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd
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../../ip_cores/general-cores/modules/common/gc_word_packer.vhd
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../../platform/xilinx/wr_gtp_phy/whiterabbitgtx_wrapper_gtx.vhd
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../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v
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../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd
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../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd
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../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Init.vhd
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../../ip_cores/general-cores/modules/common/gencores_pkg.vhd
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../../modules/wr_eca/eca_sdp.vhd
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../../modules/wr_eca/eca_data.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_crossbar/wb_skidpad.vhd
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../../modules/fabric/xwrf_loopback/xwrf_loopback.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd
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../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd
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../../modules/wr_streamers/xtx_streamer.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v
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../../modules/fabric/xwrf_loopback/lbk_wishbone_controller.vhd
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../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd
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../../ip_cores/general-cores/modules/common/matrix_pkg.vhd
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../../modules/wr_streamers/wr_streamers_wb.vhd
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../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd
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../../modules/wr_endpoint/ep_rx_vlan_unit.vhd
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../../ip_cores/general-cores/modules/common/gc_big_adder.vhd
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../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_commit_fifo.vhd
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../../modules/wr_eca/eca_queue_auto.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd
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../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd
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../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd
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../../modules/wr_eca/eca_walker.vhd
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../../ip_cores/general-cores/modules/wishbone/wbgenplus/wbgenplus_pkg.vhd
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../../modules/wr_endpoint/ep_sync_detect.vhd
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../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd
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../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Wb_master.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd
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../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd
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../../modules/wrc_core/wrc_syscon_pkg.vhd
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../../modules/wr_eca/eca_tlu_fsm.vhd
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../../ip_cores/etherbone-core/hdl/eb_master_core/eb_record_gen.vhd
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../../platform/xilinx/chipscope/chipscope_icon.ngc
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../../modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd
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../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd
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../../ip_cores/general-cores/modules/common/gc_reset.vhd
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../../modules/wr_mini_nic/xwr_mini_nic.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd
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../../modules/wr_eca/wr_eca.vhd
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../../modules/wr_eca/eca_offset.vhd
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../../modules/wr_endpoint/ep_crc32_pkg.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd
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../../board/common/wr_board_pkg.vhd
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../../ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd
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../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME64xCore_Top.vhd
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../../platform/xilinx/wr_gtp_phy/gtx_reset.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd
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../../modules/fabric/wr_fabric_pkg.vhd
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../../modules/wr_eca/eca_scan.vhd
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../../ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v
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../../modules/wr_endpoint/ep_rx_pcs_16bit.vhd
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../../modules/wr_eca/eca_scubus_channel.vhd
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../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd
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../../modules/timing/pulse_stamper.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v
\
../../ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd
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../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd
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../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Access_Decode.vhd
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../../platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd
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../../modules/wr_endpoint/ep_sync_detect_16bit.vhd
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../../modules/fabric/xwrf_mux.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd
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../../modules/wr_eca/eca_rmw.vhd
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../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd
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../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_IRQ_Controller.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd
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../../modules/wr_eca/eca_tlu_auto_pkg.vhd
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../../modules/wr_tbi_phy/wr_tbi_phy.vhd
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../../platform/xilinx/chipscope/chipscope_ila.ngc
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../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v
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../../modules/wr_eca/eca_queue_auto_pkg.vhd
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../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd
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../../modules/wr_streamers/xwr_streamers.vhd
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../../modules/wr_softpll_ng/spll_wb_slave.vhd
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../../modules/timing/hpll_period_detect.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd
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../../modules/wr_tbi_phy/disparity_gen_pkg.vhd
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../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd
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../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd
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../../modules/wr_pps_gen/pps_gen_wb.vhd
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../../platform/xilinx/wr_gtp_phy/gtp_phase_align_virtex6.vhd
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../../modules/wr_endpoint/ep_rx_status_reg_insert.vhd
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../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd
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../../modules/wr_streamers/xtx_streamers_stats.vhd
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../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd
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../../modules/wr_endpoint/xwr_endpoint.vhd
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../../ip_cores/general-cores/modules/common/gc_dec_8b10b.vhd
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../../modules/wr_streamers/streamers_priv_pkg.vhd
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../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd
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../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd
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../../modules/wr_endpoint/ep_registers_pkg.vhd
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../../modules/wr_endpoint/ep_autonegotiation.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd
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../../modules/wr_endpoint/ep_tx_packet_injection.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/axi4_pkg.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd
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../../modules/wr_endpoint/endpoint_private_pkg.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v
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../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd
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../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd
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../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd
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../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v
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../../modules/wr_endpoint/ep_clock_alignment_fifo.vhd
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../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd
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../../modules/wr_endpoint/ep_tx_crc_inserter.vhd
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../../modules/wr_eca/eca.vhd
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../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_tx.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd
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../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd
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../../board/common/wr_board_pkg.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v
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../../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_decode32.vhd
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../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v
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../../modules/wr_endpoint/ep_rx_early_address_match.vhd
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../../modules/wr_si57x_interface/wr_si57x_interface.vhd
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../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_tx.vhd
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../../modules/wr_softpll_ng/spll_aligner.vhd
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../../ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd
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../../ip_cores/vme64x-core/hdl/rtl/vme_funct_match.vhd
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spec_wr_ref.xise
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../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd
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../../modules/wr_endpoint/wr_endpoint.vhd
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../../modules/wr_streamers/escape_detector.vhd
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../../modules/wr_softpll_ng/spll_period_detect.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd
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../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd
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../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd
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../../modules/wr_endpoint/ep_ts_counter.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v
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../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd
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../../modules/wr_eca/eca_ac_wbm.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v
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../../modules/wr_eca/eca_data.vhd
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../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd
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../../
ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v
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../../
modules/wr_eca/eca_queue.vhd
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../../modules/wr_mini_nic/minic_wbgen2_pkg.vhd
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../../modules/wr_eca/eca_auto_pkg.vhd
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../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd
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../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd
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../../ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd
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../../modules/fabric/xwrf_loopback/xwrf_loopback.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd
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../../modules/wr_endpoint/ep_rx_buffer.vhd
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../../modules/wr_mini_nic/minic_packet_buffer.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v
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../../modules/wr_eca/eca_internals_pkg.vhd
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../../modules/wr_streamers/xtx_streamer.vhd
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../../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd
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../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd
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../../modules/fabric/xwrf_loopback/lbk_wishbone_controller.vhd
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../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_pass_fifo.vhd
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../../modules/wr_mini_nic/wr_mini_nic.vhd
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../../ip_cores/etherbone-core/hdl/eb_master_core/eb_commit_len_fifo.vhd
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../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd
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../../platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd
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../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd
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../../ip_cores/vme64x-core/hdl/rtl/xvme64x_core.vhd
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../../ip_cores/etherbone-core/hdl/eb_master_core/eb_framer.vhd
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../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd
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../../ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd
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../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd
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../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd
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../../ip_cores/general-cores/modules/common/gc_sync_register.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_register_link.vhd
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../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd
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../../modules/timing/pulse_gen.vhd
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../../modules/wr_endpoint/ep_rx_vlan_unit.vhd
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../../ip_cores/general-cores/modules/common/gc_big_adder.vhd
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../../modules/wr_softpll_ng/wr_softpll_ng.vhd
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../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_ethernet_slave.vhd
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../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd
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../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd
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../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd
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../../modules/wr_endpoint/ep_1000basex_pcs.vhd
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../../board/spec/wrc_board_spec.vhd
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../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_swapper.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd
\
../../modules/wr_streamers/wr_streamers_wb.vhd
\
../../modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd
\
../../ip_cores/general-cores/modules/common/gc_delay_line.vhd
\
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd
\
../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd
\
../../modules/wr_eca/eca_tag_channel.vhd
\
../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd
\
../../modules/wr_eca/eca_tdp.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd
\
../../modules/wr_streamers/xwr_streamers.vhd
\
../../modules/wr_softpll_ng/softpll_pkg.vhd
\
../../ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd
\
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd
\
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd
\
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd
\
../../modules/wr_eca/eca_search.vhd
\
../../modules/wr_eca/eca_queue_auto_pkg.vhd
\
../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd
\
../../ip_cores/vme64x-core/hdl/rtl/vme_cr_csr_space.vhd
\
../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd
\
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_decode32.vhd
\
../../modules/wr_eca/eca_queue_auto.vhd
\
../../modules/wr_streamers/tx_streamer.vhd
\
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd
\
../../top/spec_ref_design/spec_wr_ref_top.vhd
\
../../modules/wr_eca/eca_wr_time.vhd
\
../../modules/wr_streamers/xrx_streamer.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
../../modules/wr_endpoint/ep_rx_bypass_queue.vhd
\
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd
\
../../modules/wr_streamers/escape_inserter.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd
\
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tag_fifo.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
\
../../modules/wr_endpoint/ep_leds_controller.vhd
\
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd
\
../../modules/wr_eca/eca_walker.vhd
\
../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd
\
../../modules/wr_softpll_ng/softpll_pkg.vhd
\
../../ip_cores/general-cores/modules/wishbone/wbgenplus/wbgenplus_pkg.vhd
\
../../modules/wr_endpoint/ep_packet_filter.vhd
\
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd
#target for running synthesis in the remote location
remote
:
__test_for_remote_synthesis_variables generate_tcl __send __do_synthesis
...
...
syn/spec_ref_design/spec_wr_ref.xise
View file @
69cc4cc3
...
...
@@ -329,13 +329,13 @@
</properties>
<libraries/>
<files>
<file
xil_pn:name=
"../../
top/spec_ref_design/spec_wr_ref_top.ucf"
xil_pn:type=
"FILE_UCF
"
>
<file
xil_pn:name=
"../../
platform/xilinx/chipscope/chipscope_icon.ngc"
xil_pn:type=
"FILE_NGC
"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1"
/>
</file>
<file
xil_pn:name=
"../../
ip_cores/gn4124-core/hdl/spec/ip_cores/l2p_fifo.ngc"
xil_pn:type=
"FILE_NGC
"
>
<file
xil_pn:name=
"../../
top/spec_ref_design/spec_wr_ref_top.ucf"
xil_pn:type=
"FILE_UCF
"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"2"
/>
</file>
<file
xil_pn:name=
"../../
platform/xilinx/chipscope/chipscope_icon
.ngc"
xil_pn:type=
"FILE_NGC"
>
<file
xil_pn:name=
"../../
ip_cores/gn4124-core/hdl/spec/ip_cores/l2p_fifo
.ngc"
xil_pn:type=
"FILE_NGC"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"3"
/>
</file>
<file
xil_pn:name=
"../../platform/xilinx/chipscope/chipscope_ila.ngc"
xil_pn:type=
"FILE_NGC"
>
...
...
@@ -344,1025 +344,983 @@
<file
xil_pn:name=
"../../modules/wr_pps_gen/wr_pps_gen.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"5"
/>
</file>
<file
xil_pn:name=
"../../
ip_cores/vme64x-core/hdl/vme64x-core/rtl/xvme64x_core_pkg
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../
modules/wr_si57x_interface/xwr_si57x_interface
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"6"
/>
</file>
<file
xil_pn:name=
"../../
modules/wr_dacs/spec_serial_dac_arb
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../
ip_cores/etherbone-core/hdl/eb_slave_core/eb_wbm_fifo
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"7"
/>
</file>
<file
xil_pn:name=
"../../
modules/wr_endpoint/ep_wishbone_controller
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../
ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"8"
/>
</file>
<file
xil_pn:name=
"../../
modules/wr_eca/eca_free
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../
ip_cores/vme64x-core/hdl/rtl/vme_user_csr
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"9"
/>
</file>
<file
xil_pn:name=
"../../modules/wr_endpoint/ep_
rtu_header_extra
ct.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../modules/wr_endpoint/ep_
sync_dete
ct.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"10"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/
general-cores/modules/wishbone/wb_lm32/src/lm32_ram
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../ip_cores/
etherbone-core/hdl/eb_slave_core/eb_commit_fifo
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"11"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/
etherbone-core/hdl/eb_slave_core/eb_stream_widen
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../ip_cores/
general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"12"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/etherbone-core/hdl/eb_
usb_core/ez_usb_fifos
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../ip_cores/etherbone-core/hdl/eb_
slave_core/eb_slave_top
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"13"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/
general-cores/modules/wishbone/wb_spi/xwb_spi
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../ip_cores/
etherbone-core/hdl/eb_master_core/eb_master_slave_wrapper
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"14"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/
wishbone/wb_simple_timer/wb_tics
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/
genrams/generic/generic_sync_fifo
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"15"
/>
</file>
<file
xil_pn:name=
"../../modules/
wr_softpll_ng/spll_aligner
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../modules/
fabric/xwrf_loopback/wrf_loopback
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"16"
/>
</file>
<file
xil_pn:name=
"../../modules/wr_e
ca/eca_msi
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../modules/wr_e
ndpoint/ep_tx_inject_ctrl
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"17"
/>
</file>
<file
xil_pn:name=
"../../modules/wr_endpoint/
wr_endpoint
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../modules/wr_endpoint/
ep_wishbone_controller
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"18"
/>
</file>
<file
xil_pn:name=
"../../modules/wr_
tlu/tlu_fsm
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../modules/wr_
endpoint/endpoint_pkg
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"19"
/>
</file>
<file
xil_pn:name=
"../../
ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/l2p_ser
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../
modules/wr_tbi_phy/enc_8b10b
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"20"
/>
</file>
<file
xil_pn:name=
"../../
ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../
modules/wrc_core/wrc_syscon_pkg
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"21"
/>
</file>
<file
xil_pn:name=
"../../modules/wr_eca/eca_
ac_wbm_auto
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../modules/wr_eca/eca_
tlu_fsm
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"22"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/
etherbone-core/hdl/eb_slave_core/eb_eth_rx
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../ip_cores/
general-cores/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"23"
/>
</file>
<file
xil_pn:name=
"../../
board/spec/xwrc_board_spec
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../
ip_cores/etherbone-core/hdl/eb_master_core/eb_record_gen
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"24"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/
general-cores/modules/genrams/xilinx/generic_simple_dpram
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../ip_cores/
etherbone-core/hdl/eb_master_core/eb_master_wb_if
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"25"
/>
</file>
<file
xil_pn:name=
"../../
modules/timing/dmtd_phase_meas
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../
ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_split
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"26"
/>
</file>
<file
xil_pn:name=
"../../
ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../
platform/xilinx/wr_gtp_phy/spartan6/whiterabbitgtp_wrapper_tile_spartan6
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"27"
/>
</file>
<file
xil_pn:name=
"../../
platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_til
e.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../
modules/wr_eca/eca_fre
e.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"28"
/>
</file>
<file
xil_pn:name=
"../../
modules/wr_endpoint/endpoint_pkg
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../
ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"29"
/>
</file>
<file
xil_pn:name=
"../../modules/
timing/dmtd_with_deglitcher
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../modules/
wr_endpoint/ep_rtu_header_extract
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"30"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/
vme64x-core/hdl/vme64x-core/rtl/xvme64x_core
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../ip_cores/
general-cores/modules/genrams/common/inferred_sync_fifo
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"31"
/>
</file>
<file
xil_pn:name=
"../../
ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_bus
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../
modules/wr_endpoint/ep_tx_path
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"32"
/>
</file>
<file
xil_pn:name=
"../../modules/wr_e
ca/eca_wb_event
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../modules/wr_e
ndpoint/ep_pcs_tbi_mdio_wb
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"33"
/>
</file>
<file
xil_pn:name=
"../../
modules/wrc_core/wrcore_pkg
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../
ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"34"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/g
eneral-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2
_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../ip_cores/g
n4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core
_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"35"
/>
</file>
<file
xil_pn:name=
"../../
ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../
modules/wr_endpoint/ep_tx_pcs_16bit
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"36"
/>
</file>
<file
xil_pn:name=
"../../
ip_cores/etherbone-core/hdl/eb_slave_core/eb_raw_slave
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../
modules/wrc_core/wrc_periph
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"37"
/>
</file>
<file
xil_pn:name=
"../../
ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Am_Match
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../
modules/wr_eca/eca_pkg
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"38"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/
general-cores/modules/wishbone/wb_i2c_master/wb_i2c_mast
er.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../ip_cores/
vme64x-core/hdl/rtl/vme_irq_controll
er.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"39"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/
common/gc_async_signals_input_stage
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/
wishbone/wb_spi/xwb_spi
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"40"
/>
</file>
<file
xil_pn:name=
"../../
modules/wr_tlu/tlu
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"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"326"
/>
</file>
<file
xil_pn:name=
"../../
modules/wr_eca/eca_internals_pkg
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../
ip_cores/general-cores/modules/common/gc_frequency_meter
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"327"
/>
</file>
<file
xil_pn:name=
"../../
platform/xilinx/wr_gtp_phy/gtp_bitslide
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../
modules/wr_softpll_ng/softpll_pkg
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"328"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/
platform/xilinx/wb_xil_multiboot/spi_master
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../ip_cores/general-cores/
modules/wishbone/wbgenplus/wbgenplus_pkg
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"329"
/>
</file>
<file
xil_pn:name=
"../../
ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../
modules/wr_endpoint/ep_packet_filter
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"330"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_
slave_core
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_
fifo
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"331"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"332"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_ethernet_slave.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"333"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"334"
/>
</file>
<file
xil_pn:name=
"../../board/spec/wrc_board_spec.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"335"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_swapper.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"336"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"337"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"338"
/>
</file>
<file
xil_pn:name=
"../../modules/wr_eca/eca_tdp.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"339"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"340"
/>
</file>
<file
xil_pn:name=
"../../modules/wr_streamers/xwr_streamers.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"341"
/>
</file>
<file
xil_pn:name=
"../../modules/wr_softpll_ng/softpll_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"342"
/>
</file>
<file
xil_pn:name=
"../../modules/wr_eca/eca_wr_time.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"343"
/>
</file>
<file
xil_pn:name=
"../../modules/wr_streamers/xrx_streamer.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"344"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"345"
/>
</file>
</files>
<bindings/>
...
...
syn/svec_ref_design/Makefile
View file @
69cc4cc3
...
...
@@ -60,352 +60,338 @@ endif
CWD
:=
$(
shell
pwd
)
FILES
:=
../../modules/wr_pps_gen/wr_pps_gen.vhd
\
../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/xvme64x_core_pkg.vhd
\
../../modules/wr_dacs/spec_serial_dac_arb.vhd
\
../../modules/wr_si57x_interface/xwr_si57x_interface.vhd
\
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_wbm_fifo.vhd
\
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd
\
../../ip_cores/vme64x-core/hdl/rtl/vme_user_csr.vhd
\
../../modules/wr_endpoint/ep_sync_detect.vhd
\
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_commit_fifo.vhd
\
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd
\
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd
\
../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_slave_wrapper.vhd
\
../../top/svec_ref_design/svec_wr_ref_top.vhd
\
../../modules/fabric/xwrf_loopback/wrf_loopback.vhd
\
../../modules/wr_endpoint/ep_tx_inject_ctrl.vhd
\
../../modules/wr_endpoint/ep_wishbone_controller.vhd
\
../../modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd
\
../../modules/wr_tbi_phy/enc_8b10b.vhd
\
../../modules/wrc_core/wrc_syscon_pkg.vhd
\
../../modules/wr_eca/eca_tlu_fsm.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd
\
../../ip_cores/etherbone-core/hdl/eb_master_core/eb_record_gen.vhd
\
../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_wb_if.vhd
\
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_split.vhd
\
../../platform/xilinx/chipscope/chipscope_icon.ngc
\
../../platform/xilinx/wr_gtp_phy/spartan6/whiterabbitgtp_wrapper_tile_spartan6.vhd
\
../../modules/wr_eca/eca_free.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd
\
../../modules/wr_endpoint/ep_rtu_header_extract.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd
\
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd
\
../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_fifos.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd
\
../../modules/wr_softpll_ng/spll_aligner.vhd
\
../../modules/wr_eca/eca_msi.vhd
\
../../modules/wr_endpoint/wr_endpoint.vhd
\
../../modules/wr_tlu/tlu_fsm.vhd
\
../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd
\
../../modules/wr_eca/eca_ac_wbm_auto.vhd
\
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd
\
../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd
\
../../modules/timing/dmtd_phase_meas.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd
\
../../platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd
\
../../modules/wr_endpoint/endpoint_pkg.vhd
\
../../modules/timing/dmtd_with_deglitcher.vhd
\
../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/xvme64x_core.vhd
\
../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_bus.vhd
\
../../modules/wr_eca/eca_wb_event.vhd
\
../../modules/wrc_core/wrcore_pkg.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd
\
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_raw_slave.vhd
\
../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Am_Match.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd
\
../../ip_cores/general-cores/modules/common/gc_async_signals_input_stage.vhd
\
../../modules/wr_tlu/tlu.vhd
\
../../top/svec_ref_design/svec_wr_ref_top.ucf
\
../../modules/wr_softpll_ng/spll_wb_slave.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd
\
../../modules/wr_streamers/rx_streamer.vhd
\
../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd
\
../../modules/wr_endpoint/ep_rx_status_reg_insert.vhd
\
../../modules/wr_streamers/xtx_streamers_stats.vhd
\
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd
\
../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd
\
../../modules/wr_endpoint/ep_registers_pkg.vhd
\
../../modules/wr_endpoint/ep_autonegotiation.vhd
\
../../board/common/xwrc_board_common.vhd
\
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd
\
../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd
\
../../modules/wr_endpoint/ep_tx_crc_inserter.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v
\
../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CRAM.vhd
\
../../modules/wr_streamers/escape_detector.vhd
\
../../modules/wr_endpoint/ep_ts_counter.vhd
\
../../modules/wr_eca/eca_queue.vhd
\
../../modules/wr_eca/eca_auto_pkg.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd
\
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_pass_fifo.vhd
\
../../modules/wr_mini_nic/wr_mini_nic.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd
\
../../ip_cores/etherbone-core/hdl/eb_master_core/eb_framer.vhd
\
../../ip_cores/general-cores/modules/common/gc_sync_register.vhd
\
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd
\
../../ip_cores/general-cores/modules/common/gc_moving_average.vhd
\
../../ip_cores/etherbone-core/hdl/eb_master_core/eb_commit_len_fifo.vhd
\
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd
\
../../modules/wr_eca/eca_tag_channel.vhd
\
../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CSR_pack.vhd
\
../../board/svec/wr_svec_pkg.vhd
\
../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd
\
../../modules/wr_endpoint/ep_leds_controller.vhd
\
../../modules/wr_endpoint/ep_packet_filter.vhd
\
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd
\
../../modules/wr_si57x_interface/xwr_si57x_interface.vhd
\
../../modules/wr_tbi_phy/dec_8b10b.vhd
\
../../modules/wr_tbi_phy/enc_8b10b.vhd
\
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/pulse_sync_rtl.vhd
\
../../ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd
\
../../modules/wr_endpoint/ep_tx_path.vhd
\
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd
\
../../modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd
\
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd
\
../../modules/wr_endpoint/ep_tx_pcs_16bit.vhd
\
../../modules/wrc_core/wrc_periph.vhd
\
../../modules/wr_eca/eca_pkg.vhd
\
../../ip_cores/vme64x-core/hdl/rtl/vme_irq_controller.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd
\
../../modules/wr_softpll_ng/spll_aligner.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd
\
../../modules/wr_endpoint/ep_rx_oob_insert.vhd
\
../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd
\
../../ip_cores/general-cores/modules/common/gc_moving_average.vhd
\
../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd
\
../../modules/wr_eca/eca_msi.vhd
\
../../modules/wrc_core/wr_core.vhd
\
../../ip_cores/general-cores/modules/common/gc_reset.vhd
\
../../modules/timing/multi_dmtd_with_deglitcher.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v
\
../../modules/wr_mini_nic/xwr_mini_nic.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd
\
../../modules/wr_endpoint/ep_tx_header_processor.vhd
\
../../ip_cores/general-cores/modules/common/gencores_pkg.vhd
\
../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb.vhd
\
../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_eth_tx.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_register_link.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd
\
../../modules/wr_eca/eca_channel.vhd
\
../../modules/wr_eca/wr_eca.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
\
../../modules/wr_eca/eca_offset.vhd
\
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd
\
../../modules/wr_endpoint/ep_crc32_pkg.vhd
\
../../modules/wr_endpoint/ep_rx_pcs_8bit.vhd
\
../../modules/wr_softpll_ng/spll_wbgen2_pkg.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd
\
../../modules/wr_eca/eca_wb_event.vhd
\
../../modules/wr_tlu/tlu_fsm.vhd
\
../../ip_cores/vme64x-core/hdl/rtl/vme64x_pkg.vhd
\
../../modules/fabric/xwrf_loopback/lbk_pkg.vhd
\
../../ip_cores/g
n4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg
.vhd
\
../../ip_cores/g
eneral-cores/modules/genrams/generic/generic_sync_fifo
.vhd
\
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd
\
../../modules/wr_dacs/spec_serial_dac_arb.vhd
\
../../modules/wr_streamers/xrx_streamers_stats.vhd
\
../../ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd
\
../../modules/wr_eca/eca_auto.vhd
\
../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd
\
../../modules/wr_endpoint/ep_rx_crc_size_check.vhd
\
../../platform/xilinx/wr_gtp_phy/spartan6/wr_gtp_phy_spartan6.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd
\
../../modules/wr_tlu/tlu_pkg.vhd
\
../../modules/wr_eca/eca_ac_wbm_auto.vhd
\
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd
\
../../modules/wr_softpll_ng/xwr_softpll_ng.vhd
\
../../modules/wr_eca/eca_tlu.vhd
\
../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_pkg.vhd
\
../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_fifos.vhd
\
../../modules/wr_mini_nic/minic_wb_slave.vhd
\
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd
\
../../platform/xilinx/wr_xilinx_pkg.vhd
\
../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CR_pack.vhd
\
../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd
\
../../modules/fabric/wr_fabric_pkg.vhd
\
../../modules/wr_eca/eca_sdp.vhd
\
../../modules/wr_eca/eca_scan.vhd
\
../../modules/wr_streamers/xrtx_streamers_stats.vhd
\
../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd
\
../../modules/wr_endpoint/ep_rx_path.vhd
\
../../modules/wr_streamers/dropping_buffer.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v
\
../../modules/fabric/xwrf_reg.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v
\
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd
\
../../modules/wr_eca/eca_ac_wbm_auto_pkg.vhd
\
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd
\
../../modules/timing/dmtd_phase_meas.vhd
\
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/pulse_sync_rtl.vhd
\
../../modules/wr_endpoint/ep_rx_pcs_16bit.vhd
\
../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd
\
../../modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd
\
../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Funct_Match.vhd
\
../../modules/fabric/xwb_fabric_sink.vhd
\
../../modules/wr_endpoint/ep_rx_wb_master.vhd
\
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd
\
../../platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd
\
../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_top.vhd
\
../../modules/wrc_core/wrc_syscon_wb.vhd
\
../../modules/wr_endpoint/ep_tx_pcs_8bit.vhd
\
../../modules/wr_endpoint/ep_tx_vlan_unit.vhd
\
../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd
\
../../modules/wrc_core/wrc_diags_wb.vhd
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../../modules/wr_pps_gen/xwr_pps_gen.vhd
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../../modules/wr_softpll_ng/spll_wbgen2_pkg.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd
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../../board/svec/xwrc_board_svec.vhd
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../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_wbm_fifo.vhd
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../../modules/wr_eca/eca.vhd
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../../modules/wr_endpoint/endpoint_private_pkg.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v
\
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_register_link.vhd
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../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd
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../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd
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../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd
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../../platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd
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../../modules/wr_softpll_ng/spll_period_detect.vhd
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../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd
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../../modules/wr_eca/eca_ac_wbm.vhd
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svec_wr_ref.xise
\
../../platform/xilinx/wr_gtp_phy/wr_gtx_phy_virtex6.vhd
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../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd
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../../modules/wr_endpoint/ep_clock_alignment_fifo.vhd
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../../modules/timing/pulse_gen.vhd
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../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd
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../../ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd
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../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd
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../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd
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../../modules/wr_endpoint/ep_1000basex_pcs.vhd
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../../modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd
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../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd
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../../ip_cores/general-cores/modules/common/gc_single_reset_gen.vhd
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../../ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd
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../../modules/wr_eca/eca_search.vhd
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../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd
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../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd
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../../modules/wr_endpoint/ep_rx_bypass_queue.vhd
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../../modules/wr_streamers/escape_inserter.vhd
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../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tag_fifo.vhd
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../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd
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../../modules/wr_streamers/tx_streamer.vhd
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../../platform/xilinx/wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd
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../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_slave_wrapper.vhd
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../../top/svec_ref_design/svec_wr_ref_top.vhd
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../../modules/fabric/xwrf_loopback/wrf_loopback.vhd
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../../modules/wr_endpoint/ep_tx_inject_ctrl.vhd
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../../modules/wr_tlu/tlu_pkg.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd
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../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_split.vhd
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../../ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd
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../../modules/wr_endpoint/ep_rx_oob_insert.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd
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../../modules/timing/multi_dmtd_with_deglitcher.vhd
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../../modules/wr_endpoint/ep_tx_header_processor.vhd
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../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_wb_if.vhd
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../../modules/wr_endpoint/ep_rx_pcs_8bit.vhd
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../../modules/wr_eca/eca_channel.vhd
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../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd
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../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd
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../../modules/wr_eca/eca_auto.vhd
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../../modules/wr_eca/eca_tlu.vhd
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../../modules/wrc_core/xwr_syscon_wb.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd
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../../modules/wr_endpoint/ep_rx_early_address_match.vhd
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../../modules/wr_streamers/xrtx_streamers_stats.vhd
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../../modules/fabric/xwrf_reg.vhd
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../../modules/wr_eca/eca_scubus_channel.vhd
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../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd
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../../modules/timing/pulse_stamper.vhd
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../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd
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../../modules/wr_streamers/streamers_pkg.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v
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../../modules/wr_endpoint/endpoint_pkg.vhd
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../../modules/wr_streamers/rx_streamer.vhd
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../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd
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../../modules/timing/dmtd_with_deglitcher.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd
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../../platform/xilinx/xwrc_platform_xilinx.vhd
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../../modules/wr_endpoint/ep_timestamping_unit.vhd
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../../modules/fabric/xwb_fabric_sink.vhd
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../../modules/wrc_core/wrc_diags_pkg.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd
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../../modules/wr_si57x_interface/si570_if_wb.vhd
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../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd
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../../modules/wr_endpoint/ep_rx_wb_master.vhd
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../../ip_cores/vme64x-core/hdl/rtl/vme_bus.vhd
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../../modules/wrc_core/wrcore_pkg.vhd
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../../modules/wr_endpoint/ep_sync_detect_16bit.vhd
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../../modules/wr_eca/eca_adder.vhd
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../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_SharedComps.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd
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../../modules/wrc_core/xwr_core.vhd
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../../modules/fabric/xwrf_mux.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd
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../../modules/wrc_core/xwrc_diags_wb.vhd
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../../ip_cores/general-cores/modules/common/gc_single_reset_gen.vhd
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../../modules/wr_tlu/tlu.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd
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../../modules/wr_eca/eca_piso_fifo.vhd
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../../modules/wrc_core/wrc_dpram.vhd
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../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_top.vhd
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../../modules/wrc_core/wrc_syscon_wb.vhd
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../../modules/wrc_core/xwr_core.vhd
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../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd
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../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/vme64x_pack.vhd
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../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd
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../../modules/wr_endpoint/xwr_endpoint.vhd
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../../modules/wr_eca/eca_rmw.vhd
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../../modules/wr_endpoint/ep_tx_pcs_8bit.vhd
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../../ip_cores/vme64x-core/hdl/rtl/vme64x_core.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_crossbar/wb_skidpad.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd
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../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd
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../../platform/xilinx/wr_gtp_phy/spartan6/gtp_phase_align.vhd
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../../modules/wr_endpoint/ep_tx_vlan_unit.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd
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../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd
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../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_raw_slave.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd
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../../modules/wr_dacs/spec_serial_dac.vhd
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../../modules/wrc_core/wrc_diags_wb.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd
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../../modules/wr_pps_gen/xwr_pps_gen.vhd
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../../board/common/xwrc_board_common.vhd
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../../ip_cores/gn4124-core/hdl/spec/ip_cores/l2p_fifo.ngc
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../../ip_cores/general-cores/modules/common/gc_async_signals_input_stage.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd
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../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd
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../../modules/fabric/xwb_fabric_source.vhd
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../../modules/wr_eca/eca_tlu_auto.vhd
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../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd
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../../modules/wr_streamers/dropping_buffer.vhd
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../../modules/wr_softpll_ng/wr_softpll_ng.vhd
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../../modules/wr_tbi_phy/disparity_gen_pkg.vhd
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../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd
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../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd
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../../ip_cores/general-cores/modules/common/gc_word_packer.vhd
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../../platform/xilinx/wr_gtp_phy/whiterabbitgtx_wrapper_gtx.vhd
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../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd
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../../board/svec/wrc_board_svec.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v
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../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd
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../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd
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../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Init.vhd
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../../ip_cores/general-cores/modules/common/gencores_pkg.vhd
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../../modules/wr_eca/eca_sdp.vhd
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../../modules/wr_eca/eca_data.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_crossbar/wb_skidpad.vhd
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../../modules/fabric/xwrf_loopback/xwrf_loopback.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd
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../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd
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../../modules/wr_streamers/xtx_streamer.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v
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../../modules/fabric/xwrf_loopback/lbk_wishbone_controller.vhd
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../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd
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../../ip_cores/general-cores/modules/common/matrix_pkg.vhd
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../../modules/wr_streamers/wr_streamers_wb.vhd
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../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd
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../../modules/wr_endpoint/ep_rx_vlan_unit.vhd
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../../ip_cores/general-cores/modules/common/gc_big_adder.vhd
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../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_commit_fifo.vhd
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../../modules/wr_eca/eca_queue_auto.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd
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../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd
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../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd
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../../modules/wr_eca/eca_walker.vhd
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../../ip_cores/general-cores/modules/wishbone/wbgenplus/wbgenplus_pkg.vhd
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../../modules/wr_endpoint/ep_sync_detect.vhd
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../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd
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../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Wb_master.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd
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../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd
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../../modules/wrc_core/wrc_syscon_pkg.vhd
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../../modules/wr_eca/eca_tlu_fsm.vhd
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../../ip_cores/etherbone-core/hdl/eb_master_core/eb_record_gen.vhd
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../../platform/xilinx/chipscope/chipscope_icon.ngc
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../../modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd
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../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd
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../../ip_cores/general-cores/modules/common/gc_reset.vhd
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../../modules/wr_mini_nic/xwr_mini_nic.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd
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../../modules/wr_eca/wr_eca.vhd
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../../modules/wr_eca/eca_offset.vhd
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../../modules/wr_endpoint/ep_crc32_pkg.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd
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../../board/common/wr_board_pkg.vhd
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../../ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd
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../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME64xCore_Top.vhd
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../../platform/xilinx/wr_gtp_phy/gtx_reset.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd
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../../modules/fabric/wr_fabric_pkg.vhd
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../../modules/wr_eca/eca_scan.vhd
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../../ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v
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../../modules/wr_endpoint/ep_rx_pcs_16bit.vhd
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../../modules/wr_eca/eca_scubus_channel.vhd
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../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd
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../../modules/timing/pulse_stamper.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v
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../../ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd
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../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd
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../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Access_Decode.vhd
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../../platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd
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../../modules/wr_endpoint/ep_sync_detect_16bit.vhd
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../../modules/fabric/xwrf_mux.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd
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../../modules/wr_eca/eca_rmw.vhd
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../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd
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../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_IRQ_Controller.vhd
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../../top/svec_ref_design/svec_wr_ref_top.ucf
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../../modules/wr_eca/eca_tlu_auto_pkg.vhd
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../../modules/wr_tbi_phy/wr_tbi_phy.vhd
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../../platform/xilinx/chipscope/chipscope_ila.ngc
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../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v
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../../modules/wr_eca/eca_queue_auto_pkg.vhd
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../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd
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run.tcl
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../../modules/wr_streamers/xwr_streamers.vhd
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../../modules/wr_softpll_ng/spll_wb_slave.vhd
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../../modules/timing/hpll_period_detect.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd
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../../modules/wr_tbi_phy/disparity_gen_pkg.vhd
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../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd
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../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd
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../../modules/wr_pps_gen/pps_gen_wb.vhd
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../../platform/xilinx/wr_gtp_phy/gtp_phase_align_virtex6.vhd
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../../modules/wr_endpoint/xwr_endpoint.vhd
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../../modules/wr_endpoint/ep_rx_status_reg_insert.vhd
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../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd
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../../modules/wr_streamers/xtx_streamers_stats.vhd
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../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd
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../../modules/wr_endpoint/ep_registers_pkg.vhd
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../../ip_cores/general-cores/modules/common/gc_dec_8b10b.vhd
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../../modules/wr_streamers/streamers_priv_pkg.vhd
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../../modules/wr_endpoint/ep_autonegotiation.vhd
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../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd
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../../board/svec/wrc_board_svec.vhd
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../../board/svec/xwrc_board_svec.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd
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../../modules/wr_endpoint/ep_tx_packet_injection.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/axi4_pkg.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd
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../../modules/wr_endpoint/endpoint_private_pkg.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v
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../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd
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../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd
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../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd
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../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v
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../../modules/wr_endpoint/ep_clock_alignment_fifo.vhd
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../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd
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../../modules/wr_endpoint/ep_tx_crc_inserter.vhd
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../../modules/wr_eca/eca.vhd
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../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_tx.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd
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../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd
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../../board/common/wr_board_pkg.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v
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../../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_decode32.vhd
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../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v
\
../../modules/wr_endpoint/ep_rx_early_address_match.vhd
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../../modules/wr_si57x_interface/wr_si57x_interface.vhd
\
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_tx.vhd
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../../ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd
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../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd
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../../ip_cores/vme64x-core/hdl/rtl/vme_funct_match.vhd
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../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd
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../../modules/wr_endpoint/wr_endpoint.vhd
\
../../modules/wr_streamers/escape_detector.vhd
\
../../modules/wr_softpll_ng/spll_period_detect.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd
\
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd
\
../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd
\
run.tcl
\
../../modules/wr_endpoint/ep_ts_counter.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v
\
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd
\
../../modules/wr_eca/eca_ac_wbm.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v
\
../../modules/wr_eca/eca_data.vhd
\
../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd
\
../../
ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v
\
../../
modules/wr_eca/eca_queue.vhd
\
../../modules/wr_mini_nic/minic_wbgen2_pkg.vhd
\
../../modules/wr_eca/eca_auto_pkg.vhd
\
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd
\
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd
\
../../ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd
\
../../modules/fabric/xwrf_loopback/xwrf_loopback.vhd
\
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd
\
../../modules/wr_endpoint/ep_rx_buffer.vhd
\
../../modules/wr_mini_nic/minic_packet_buffer.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v
\
../../modules/wr_eca/eca_internals_pkg.vhd
\
../../modules/wr_streamers/xtx_streamer.vhd
\
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd
\
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v
\
../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd
\
../../modules/wr_mini_nic/wr_mini_nic.vhd
\
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_pass_fifo.vhd
\
../../modules/fabric/xwrf_loopback/lbk_wishbone_controller.vhd
\
../../ip_cores/etherbone-core/hdl/eb_master_core/eb_commit_len_fifo.vhd
\
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd
\
../../platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd
\
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd
\
../../ip_cores/vme64x-core/hdl/rtl/xvme64x_core.vhd
\
../../ip_cores/etherbone-core/hdl/eb_master_core/eb_framer.vhd
\
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd
\
../../ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd
\
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd
\
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd
\
../../ip_cores/general-cores/modules/common/gc_sync_register.vhd
\
../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd
\
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd
\
../../modules/timing/pulse_gen.vhd
\
../../modules/wr_endpoint/ep_rx_vlan_unit.vhd
\
../../ip_cores/general-cores/modules/common/gc_big_adder.vhd
\
../../modules/wr_softpll_ng/wr_softpll_ng.vhd
\
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_ethernet_slave.vhd
\
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd
\
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd
\
../../modules/wr_endpoint/ep_1000basex_pcs.vhd
\
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd
\
../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_swapper.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd
\
../../modules/wr_streamers/wr_streamers_wb.vhd
\
../../modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd
\
../../ip_cores/general-cores/modules/common/gc_delay_line.vhd
\
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd
\
../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd
\
../../modules/wr_eca/eca_tag_channel.vhd
\
../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd
\
../../modules/wr_eca/eca_tdp.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd
\
../../modules/wr_streamers/xwr_streamers.vhd
\
../../modules/wr_softpll_ng/softpll_pkg.vhd
\
../../ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd
\
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd
\
../../ip_cores/general-cores/modules/common/gc_word_packer.vhd
\
../../board/svec/wr_svec_pkg.vhd
\
../../modules/wr_eca/eca_search.vhd
\
../../modules/wr_eca/eca_queue_auto_pkg.vhd
\
../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd
\
../../ip_cores/vme64x-core/hdl/rtl/vme_cr_csr_space.vhd
\
../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd
\
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_decode32.vhd
\
../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_eth_tx.vhd
\
../../modules/wr_eca/eca_queue_auto.vhd
\
../../modules/wr_streamers/tx_streamer.vhd
\
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd
\
../../modules/wr_eca/eca_wr_time.vhd
\
../../modules/wr_streamers/xrx_streamer.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
../../modules/wr_endpoint/ep_rx_bypass_queue.vhd
\
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd
\
../../modules/wr_streamers/escape_inserter.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd
\
svec_wr_ref.xise
\
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tag_fifo.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
\
../../modules/wr_endpoint/ep_leds_controller.vhd
\
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd
\
../../modules/wr_eca/eca_walker.vhd
\
../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd
\
../../modules/wr_softpll_ng/softpll_pkg.vhd
\
../../ip_cores/general-cores/modules/wishbone/wbgenplus/wbgenplus_pkg.vhd
\
../../modules/wr_endpoint/ep_packet_filter.vhd
\
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd
#target for running synthesis in the remote location
remote
:
__test_for_remote_synthesis_variables generate_tcl __send __do_synthesis
...
...
syn/svec_ref_design/svec_wr_ref.xise
View file @
69cc4cc3
...
...
@@ -104,7 +104,7 @@
<property
xil_pn:name=
"Add I/O Buffers"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Place MultiBoot Settings into Bitstream spartan6"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Load glbl"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"PROP_intWbtProjectID"
xil_pn:value=
"
3640E0256E2263C5D0B56356E76E4BB0
"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"PROP_intWbtProjectID"
xil_pn:value=
"
144D78D72FD56B55C2A7A7E4FEB1EEAF
"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"VCCAUX Voltage Level spartan6"
xil_pn:value=
"2.5V"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Extra Cost Tables Map"
xil_pn:value=
"0"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Keep Hierarchy"
xil_pn:value=
"No"
xil_pn:valueState=
"default"
/>
...
...
@@ -132,7 +132,7 @@
<property
xil_pn:name=
"Generate Asynchronous Delay Report"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Number of Clock Buffers"
xil_pn:value=
"16"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Post Translate Simulation Model Name"
xil_pn:value=
"svec_wr_ref_top_translate.v"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Pack I/O Registers/Latches into IOBs"
xil_pn:value=
"
For Outputs Only"
xil_pn:valueState=
"non-
default"
/>
<property
xil_pn:name=
"Pack I/O Registers/Latches into IOBs"
xil_pn:value=
"
Off"
xil_pn:valueState=
"
default"
/>
<property
xil_pn:name=
"Use RLOC Constraints"
xil_pn:value=
"Yes"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Resource Sharing"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"JTAG Pin TDI"
xil_pn:value=
"Pull Up"
xil_pn:valueState=
"default"
/>
...
...
@@ -200,7 +200,7 @@
<property
xil_pn:name=
"Timing Mode Par"
xil_pn:value=
"Performance Evaluation"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Other Compiler Options Map"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Run for Specified Time Par"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"PROP_intProjectCreationTimestamp"
xil_pn:value=
"2017-
03-06T15:45:20
"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"PROP_intProjectCreationTimestamp"
xil_pn:value=
"2017-
12-18T10:06:22
"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Working Directory"
xil_pn:value=
"."
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Rename Top Level Module To"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Do Not Escape Signal and Instance Names in Netlist"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
...
...
@@ -329,13 +329,13 @@
</properties>
<libraries/>
<files>
<file
xil_pn:name=
"../../
top/svec_ref_design/svec_wr_ref_top.ucf"
xil_pn:type=
"FILE_UCF
"
>
<file
xil_pn:name=
"../../
platform/xilinx/chipscope/chipscope_icon.ngc"
xil_pn:type=
"FILE_NGC
"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/gn4124-core/hdl/spec/ip_cores/l2p_fifo.ngc"
xil_pn:type=
"FILE_NGC"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"2"
/>
</file>
<file
xil_pn:name=
"../../
platform/xilinx/chipscope/chipscope_icon.ngc"
xil_pn:type=
"FILE_NGC
"
>
<file
xil_pn:name=
"../../
top/svec_ref_design/svec_wr_ref_top.ucf"
xil_pn:type=
"FILE_UCF
"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"3"
/>
</file>
<file
xil_pn:name=
"../../platform/xilinx/chipscope/chipscope_ila.ngc"
xil_pn:type=
"FILE_NGC"
>
...
...
@@ -344,1025 +344,983 @@
<file
xil_pn:name=
"../../modules/wr_pps_gen/wr_pps_gen.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"5"
/>
</file>
<file
xil_pn:name=
"../../
ip_cores/vme64x-core/hdl/vme64x-core/rtl/xvme64x_core_pkg
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../
modules/wr_si57x_interface/xwr_si57x_interface
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"6"
/>
</file>
<file
xil_pn:name=
"../../
modules/wr_dacs/spec_serial_dac_arb
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../
ip_cores/etherbone-core/hdl/eb_slave_core/eb_wbm_fifo
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"7"
/>
</file>
<file
xil_pn:name=
"../../
modules/wr_endpoint/ep_wishbone_controller
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../
ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"8"
/>
</file>
<file
xil_pn:name=
"../../
modules/wr_eca/eca_free
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../
ip_cores/vme64x-core/hdl/rtl/vme_user_csr
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"9"
/>
</file>
<file
xil_pn:name=
"../../modules/wr_endpoint/ep_
rtu_header_extra
ct.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../modules/wr_endpoint/ep_
sync_dete
ct.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"10"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/
general-cores/modules/wishbone/wb_lm32/src/lm32_ram
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../ip_cores/
etherbone-core/hdl/eb_slave_core/eb_commit_fifo
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"11"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/
etherbone-core/hdl/eb_slave_core/eb_stream_widen
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../ip_cores/
general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"12"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/etherbone-core/hdl/eb_
usb_core/ez_usb_fifos
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../ip_cores/etherbone-core/hdl/eb_
slave_core/eb_slave_top
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"13"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/
general-cores/modules/wishbone/wb_spi/xwb_spi
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../ip_cores/
etherbone-core/hdl/eb_master_core/eb_master_slave_wrapper
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"14"
/>
</file>
<file
xil_pn:name=
"../../
ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../
top/svec_ref_design/svec_wr_ref_top
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"15"
/>
</file>
<file
xil_pn:name=
"../../modules/
wr_softpll_ng/spll_aligner
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../modules/
fabric/xwrf_loopback/wrf_loopback
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"16"
/>
</file>
<file
xil_pn:name=
"../../modules/wr_e
ca/eca_msi
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../modules/wr_e
ndpoint/ep_tx_inject_ctrl
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"17"
/>
</file>
<file
xil_pn:name=
"../../modules/wr_endpoint/
wr_endpoint
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../modules/wr_endpoint/
ep_wishbone_controller
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"18"
/>
</file>
<file
xil_pn:name=
"../../modules/wr_
tlu/tlu_fsm
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../modules/wr_
si57x_interface/si570_if_wbgen2_pkg
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"19"
/>
</file>
<file
xil_pn:name=
"../../
ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../
modules/wr_tbi_phy/enc_8b10b
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"20"
/>
</file>
<file
xil_pn:name=
"../../
ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../
modules/wrc_core/wrc_syscon_pkg
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"21"
/>
</file>
<file
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...
...
syn/vfchd_ref_design/vfchd_wr_ref.qsf
View file @
69cc4cc3
...
...
@@ -468,330 +468,322 @@ set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name VHDL_FILE
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set_global_assignment -name VHDL_FILE ../../modules/wr_si57x_interface/xwr_si57x_interface.vhd
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set_global_assignment -name VHDL_FILE ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_tbi_phy/dec_8b10b.vhd
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set_global_assignment -name VHDL_FILE
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set_global_assignment -name VHDL_FILE
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set_global_assignment -name VHDL_FILE
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set_global_assignment -name VHDL_FILE
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set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_tx_inject_ctrl.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_wishbone_controller.vhd
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set_global_assignment -name VHDL_FILE ../../modules/wrc_core/wrc_syscon_pkg.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_tlu_fsm.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/etherbone-core/hdl/eb_master_core/eb_record_gen.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_wb_if.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/platform/altera/networks/altera_networks_pkg.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_master_core/eb_record_gen.vhd"
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set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd"
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set_global_assignment -name VHDL_FILE
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set_global_assignment -name VHDL_FILE
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set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_rtu_header_extract.vhd
set_global_assignment -name VHDL_FILE
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set_global_assignment -name VHDL_FILE
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set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_tx_path.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_tx_pcs_16bit.vhd
set_global_assignment -name VHDL_FILE ../../modules/wrc_core/wrc_periph.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_pkg.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd
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set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd"
set_global_assignment -name VHDL_FILE ../../top/vfchd_ref_design/vfchd_wr_ref_top.vhd
set_global_assignment -name VHDL_FILE
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set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_rx_oob_insert.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/common/gc_moving_average.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/genrams/altera/gc_shiftreg.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd"
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/common/gc_moving_average.vhd"
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/genrams/altera/gc_shiftreg.vhd"
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_msi.vhd
set_global_assignment -name VHDL_FILE ../../modules/wrc_core/wr_core.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/common/gc_reset.vhd
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/common/gc_reset.vhd"
set_global_assignment -name VHDL_FILE ../../modules/timing/multi_dmtd_with_deglitcher.vhd
set_global_assignment -name VERILOG_FILE ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v
set_global_assignment -name VHDL_FILE ../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Am_Match.vhd
set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v"
set_global_assignment -name VHDL_FILE ../../modules/wr_mini_nic/xwr_mini_nic.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_SharedComps.vhd
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_tx_header_processor.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/common/gencores_pkg.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/genrams/altera/generic_spram.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_register_link.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/common/gencores_pkg.vhd"
set_global_assignment -name VHDL_FILE
"../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb.vhd"
set_global_assignment -name VHDL_FILE
"../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_eth_tx.vhd"
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_channel.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/wr_eca.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_altera.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_altera.vhd"
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_offset.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_crc32_pkg.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_rx_pcs_8bit.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_softpll_ng/spll_wbgen2_pkg.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_wb_event.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_tlu/tlu_fsm.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/genrams/altera/altera_sync_fifo.vhd
set_global_assignment -name VHDL_FILE
"../../ip_cores/vme64x-core/hdl/rtl/vme64x_pkg.vhd"
set_global_assignment -name VHDL_FILE ../../modules/fabric/xwrf_loopback/lbk_pkg.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_dacs/spec_serial_dac_arb.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_streamers/xrx_streamers_stats.vhd
set_global_assignment -name VHDL_FILE ../../modules/wrc_core/wrc_diags_pkg.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_auto.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_rx_crc_size_check.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME64xCore_Top.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_tlu/tlu_pkg.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_64to32.vhd
set_global_assignment -name VERILOG_FILE ../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_64to32.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_wb.vhd"
set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v"
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_ac_wbm_auto.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd
set_global_assignment -name VHDL_FILE
"../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_softpll_ng/xwr_softpll_ng.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_tlu.vhd
set_global_assignment -name VHDL_FILE
../../modules/wrc_core/xwr_syscon_wb.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_pkg.vhd
set_global_assignment -name VHDL_FILE
"../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_pkg.vhd"
set_global_assignment -name VHDL_FILE
"../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_fifos.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_mini_nic/minic_wb_slave.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd"
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd"
set_global_assignment -name VHDL_FILE ../../modules/fabric/wr_fabric_pkg.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_sdp.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CR_pack.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_scan.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_streamers/xrtx_streamers_stats.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_rx_path.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_streamers/dropping_buffer.vhd
set_global_assignment -name VERILOG_FILE
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v
set_global_assignment -name VERILOG_FILE
"../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v"
set_global_assignment -name VHDL_FILE ../../modules/fabric/xwrf_reg.vhd
set_global_assignment -name VERILOG_FILE
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd
set_global_assignment -name VERILOG_FILE
"../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v"
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_ac_wbm_auto_pkg.vhd
set_global_assignment -name VHDL_FILE ../../modules/timing/dmtd_phase_meas.vhd
set_global_assignment -name VHDL_FILE ../../platform/altera/xwrc_platform_altera.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_rx_pcs_16bit.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_scubus_channel.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd
set_global_assignment -name VHDL_FILE
"../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd"
set_global_assignment -name VHDL_FILE ../../modules/timing/pulse_stamper.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_streamers/streamers_pkg.vhd
set_global_assignment -name VERILOG_FILE
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v
set_global_assignment -name VHDL_FILE ../../modules/wr_
endpoint/endpoint
_pkg.vhd
set_global_assignment -name VERILOG_FILE
"../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v"
set_global_assignment -name VHDL_FILE ../../modules/wr_
si57x_interface/si570_if_wbgen2
_pkg.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_streamers/rx_streamer.vhd
set_global_assignment -name VERILOG_FILE
../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/altera/jtag_tap.v
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd
set_global_assignment -name VERILOG_FILE
"../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/altera/jtag_tap.v"
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd"
set_global_assignment -name VHDL_FILE ../../modules/timing/dmtd_with_deglitcher.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/xvme64x_core.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Access_Decode.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Funct_Match.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_timestamping_unit.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_bus.vhd
set_global_assignment -name VHDL_FILE ../../modules/fabric/xwb_fabric_sink.vhd
set_global_assignment -name VHDL_FILE ../../platform/altera/wr_arria5_phy/wr_arria5_phy.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_sync_detect_16bit.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_si57x_interface/si570_if_wb.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_rx_wb_master.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd
set_global_assignment -name VHDL_FILE
"../../ip_cores/vme64x-core/hdl/rtl/vme_bus.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wrc_core/wrcore_pkg.vhd
set_global_assignment -name VERILOG_FILE ../../top/vfchd_ref_design/vfchd_i2cmux/SfpIdReader.v
set_global_assignment -name VHDL_FILE ../../platform/altera/wr_altera_pkg.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_adder.vhd
set_global_assignment -name VHDL_FILE ../../top/vfchd_ref_design/vfchd_i2cmux/vfchd_i2cmux_pkg.vhd
set_global_assignment -name SDC_FILE vfchd_wr_ref.sdc
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd"
set_global_assignment -name VHDL_FILE ../../modules/fabric/xwrf_mux.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wrc_core/xwrc_diags_wb.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/common/gc_single_reset_gen.vhd
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/common/gc_single_reset_gen.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_tlu/tlu.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_streamers/escape_detector.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/platform/altera/flash/altera_spi.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/platform/altera/flash/altera_spi.vhd"
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_piso_fifo.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_top.vhd
set_global_assignment -name VHDL_FILE
"../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_top.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wrc_core/wrc_syscon_wb.vhd
set_global_assignment -name VHDL_FILE ../../modules/wrc_core/wrc_dpram.vhd
set_global_assignment -name VHDL_FILE ../../modules/wrc_core/xwr_core.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/common/gc_word_packer.vhd
set_global_assignment -name VHDL_FILE
"../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd"
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/common/gc_word_packer.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_rmw.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_tx_pcs_8bit.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/vme64x_pack.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/vme64x-core/hdl/rtl/vme64x_core.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_crossbar/wb_skidpad.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_tx_vlan_unit.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_raw_slave.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd"
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd"
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd"
set_global_assignment -name VHDL_FILE
"../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_raw_slave.vhd"
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_dacs/spec_serial_dac.vhd
set_global_assignment -name VHDL_FILE ../../modules/wrc_core/wrc_diags_wb.vhd
set_global_assignment -name VERILOG_FILE ../../top/vfchd_ref_design/vfchd_i2cmux/I2cMuxAndExpMaster.v
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_IRQ_Controller.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_pps_gen/xwr_pps_gen.vhd
set_global_assignment -name VHDL_FILE ../../board/common/xwrc_board_common.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/common/gc_async_signals_input_stage.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/common/gc_async_signals_input_stage.vhd"
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd"
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd"
set_global_assignment -name VHDL_FILE ../../modules/fabric/xwb_fabric_source.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_tlu_auto.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_tlu_auto_pkg.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_tbi_phy/wr_tbi_phy.vhd
set_global_assignment -name VERILOG_FILE
../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd
set_global_assignment -name VERILOG_FILE
"../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v"
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_streamers/xwr_streamers.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_softpll_ng/spll_wb_slave.vhd
set_global_assignment -name VHDL_FILE ../../modules/timing/hpll_period_detect.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_tbi_phy/disparity_gen_pkg.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_pps_gen/pps_gen_wb.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_rx_status_reg_insert.vhd
set_global_assignment -name VHDL_FILE ../../board/vfchd/sfp_i2c_adapter.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_streamers/xtx_streamers_stats.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/xwr_endpoint.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_dec_8b10b.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_streamers/streamers_priv_pkg.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd"
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd"
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_registers_pkg.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_autonegotiation.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/genrams/altera/generic_simple_dpram.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/genrams/altera/generic_simple_dpram.vhd"
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd"
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_tx_packet_injection.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/axi4_pkg.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/endpoint_private_pkg.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_wbm_fifo.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd
set_global_assignment -name VERILOG_FILE ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_wbm_fifo.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd"
set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v"
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_clock_alignment_fifo.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_tlp.vhd
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_tlp.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_tx_crc_inserter.vhd
set_global_assignment -name VHDL_FILE ../../board/vfchd/wrc_board_vfchd.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_tx.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd
set_global_assignment -name VHDL_FILE
"../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_tx.vhd"
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd"
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd"
set_global_assignment -name VHDL_FILE ../../board/common/wr_board_pkg.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd
set_global_assignment -name VERILOG_FILE
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd"
set_global_assignment -name VERILOG_FILE
"../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v"
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_rx_early_address_match.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_si57x_interface/wr_si57x_interface.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_softpll_ng/spll_aligner.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Init.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CRAM.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_fifos.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/altera/generic_spram.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/vme64x-core/hdl/rtl/vme_funct_match.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/wr_endpoint.vhd
set_global_assignment -name VHDL_FILE ../../board/vfchd/wr_vfchd_pkg.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_softpll_ng/spll_period_detect.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd"
set_global_assignment -name VHDL_FILE
"../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_wr_time.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_ts_counter.vhd
set_global_assignment -name VERILOG_FILE
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd
set_global_assignment -name VERILOG_FILE
"../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v"
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_ac_wbm.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_data.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd"
set_global_assignment -name VHDL_FILE ../../board/vfchd/xwrc_board_vfchd.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_queue.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_mini_nic/minic_wbgen2_pkg.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_auto_pkg.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/wb_skidpad.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd"
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/genrams/altera/altera_sync_fifo.vhd"
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd"
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd"
set_global_assignment -name VHDL_FILE ../../modules/fabric/xwrf_loopback/xwrf_loopback.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_rx_buffer.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_mini_nic/minic_packet_buffer.vhd
set_global_assignment -name VERILOG_FILE
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd
set_global_assignment -name VERILOG_FILE
"../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v"
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_internals_pkg.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_streamers/xtx_streamer.vhd
set_global_assignment -name VERILOG_FILE
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_32to64.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd
set_global_assignment -name VERILOG_FILE
"../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v"
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_32to64.vhd"
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd"
set_global_assignment -name VHDL_FILE ../../modules/fabric/xwrf_loopback/lbk_wishbone_controller.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_pass_fifo.vhd
set_global_assignment -name VHDL_FILE
"../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_pass_fifo.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_mini_nic/wr_mini_nic.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/etherbone-core/hdl/eb_master_core/eb_commit_len_fifo.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_wb.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/etherbone-core/hdl/eb_master_core/eb_framer.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/platform/altera/flash/flash_top.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/genrams/altera/generic_dpram.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/common/gc_sync_register.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/common/matrix_pkg.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd
set_global_assignment -name VHDL_FILE
"../../ip_cores/etherbone-core/hdl/eb_master_core/eb_commit_len_fifo.vhd"
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd"
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd"
set_global_assignment -name VHDL_FILE
"../../ip_cores/vme64x-core/hdl/rtl/xvme64x_core.vhd"
set_global_assignment -name VHDL_FILE
"../../ip_cores/etherbone-core/hdl/eb_master_core/eb_framer.vhd"
set_global_assignment -name VHDL_FILE
"../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd"
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/platform/altera/flash/flash_top.vhd"
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/genrams/altera/generic_dpram.vhd"
set_global_assignment -name VHDL_FILE
"../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd"
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/common/gc_sync_register.vhd"
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_register_link.vhd"
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd"
set_global_assignment -name VHDL_FILE ../../modules/timing/pulse_gen.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_rx_vlan_unit.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/common/gc_big_adder.vhd
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/common/gc_big_adder.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_softpll_ng/wr_softpll_ng.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_ethernet_slave.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/genrams/altera/generic_dpram_mixed.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_ethernet_slave.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/altera/generic_dpram_mixed.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_wb_pkg.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_1000basex_pcs.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_swapper.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_streamers/wr_streamers_wb.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd
set_global_assignment -name V
ERILOG_FILE ../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v
set_global_assignment -name VHDL_FILE
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/platform/altera/flash/altera_flash_pkg.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd
set_global_assignment -name V
HDL_FILE "../../ip_cores/general-cores/modules/common/gc_delay_line.vhd"
set_global_assignment -name VHDL_FILE
"../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd"
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/platform/altera/flash/altera_flash_pkg.vhd"
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_tag_channel.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_tdp.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Wb_master.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CSR_pack.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_search.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_queue_auto_pkg.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_wb_pkg.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_eth_tx.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/vme64x-core/hdl/rtl/vme_cr_csr_space.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_queue_auto.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_streamers/tx_streamer.vhd
set_global_assignment -name VERILOG_FILE ../../top/vfchd_ref_design/vfchd_i2cmux/I2cMuxAndExpReqArbiter.v
set_global_assignment -name VHDL_FILE ../../modules/wr_streamers/xrx_streamer.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_rx_bypass_queue.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_streamers/escape_inserter.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tag_fifo.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd"
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd"
set_global_assignment -name VHDL_FILE
"../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tag_fifo.vhd"
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_leds_controller.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd
set_global_assignment -name VHDL_FILE
"../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_walker.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_softpll_ng/softpll_pkg.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/general-cores/modules/wishbone/wbgenplus/wbgenplus_pkg.vhd
set_global_assignment -name VHDL_FILE
"../../ip_cores/general-cores/modules/wishbone/wbgenplus/wbgenplus_pkg.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_packet_filter.vhd
set_global_assignment -name VHDL_FILE
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd
set_global_assignment -name VHDL_FILE
"../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd"
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:quartus_preflow.tcl"
...
...
@@ -801,4 +793,32 @@ set_global_assignment -name QIP_FILE ../../platform/altera/wr_arria5_phy/arria5_
set_global_assignment -name QIP_FILE ../../platform/altera/wr_arria5_phy/arria5_phy_reconf.qip
set_global_assignment -name QIP_FILE ../../platform/altera/wr_arria5_pll_default/arria5_dmtd_pll_default.qip
set_global_assignment -name QIP_FILE ../../platform/altera/wr_arria5_pll_default/arria5_ext_ref_pll_default.qip
set_global_assignment -name QIP_FILE ../../platform/altera/wr_arria5_pll_default/arria5_sys_pll_default.qip
\ No newline at end of file
set_global_assignment -name QIP_FILE ../../platform/altera/wr_arria5_pll_default/arria5_sys_pll_default.qip
set_location_assignment PIN_AK22 -to vme_irq_o[1]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_irq_o[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_irq_o[1]
set_instance_assignment -name SLEW_RATE 1 -to vme_irq_o[1]
set_location_assignment PIN_AT21 -to vme_irq_o[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_irq_o[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_irq_o[2]
set_instance_assignment -name SLEW_RATE 1 -to vme_irq_o[2]
set_location_assignment PIN_AR21 -to vme_irq_o[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_irq_o[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_irq_o[3]
set_instance_assignment -name SLEW_RATE 1 -to vme_irq_o[3]
set_location_assignment PIN_AH22 -to vme_irq_o[4]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_irq_o[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_irq_o[4]
set_instance_assignment -name SLEW_RATE 1 -to vme_irq_o[4]
set_location_assignment PIN_AG22 -to vme_irq_o[5]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_irq_o[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_irq_o[5]
set_instance_assignment -name SLEW_RATE 1 -to vme_irq_o[5]
set_location_assignment PIN_AU20 -to vme_irq_o[6]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_irq_o[6]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_irq_o[6]
set_instance_assignment -name SLEW_RATE 1 -to vme_irq_o[6]
set_location_assignment PIN_AT20 -to vme_irq_o[7]
set_instance_assignment -name IO_STANDARD "2.5 V" -to vme_irq_o[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vme_irq_o[7]
set_instance_assignment -name SLEW_RATE 1 -to vme_irq_o[7]
\ No newline at end of file
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