Skip to content

W
White Rabbit core collection
Commit 69d808db authored by Maciej Lipinski's avatar Maciej Lipinski
Browse files
Options

[ref_top/all] update reference top to allow its usage in simulation

parent 1304e31d
Hide whitespace changes
Inline Side-by-side
Showing with 27 additions and 4 deletions
top/spec_ref_design/spec_wr_ref_top.vhd
View file @ 69d808db
......@@ -61,6 +61,13 @@ library unisim;
use unisim.vcomponents.all;
entity spec_wr_ref_top is
generic (
g_dpram_initf : string := "../../bin/wrpc/wrc_phy8.bram";
-- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
-- changed to non-zero in the instantiation of the top level DUT in the testbench.
-- Its purpose is to reduce some internal counters/timeouts to speed up simulations.
g_simulation : integer := 0
);
port (
---------------------------------------------------------------------------
-- Clocks/resets
......@@ -414,9 +421,9 @@ begin -- architecture top
cmp_xwrc_board_spec : xwrc_board_spec
generic map (
g_simulation => 0,
g_simulation => g_simulation,
g_with_external_clock_input => TRUE,
g_dpram_initf => "../../bin/wrpc/wrc_phy8.bram",
g_dpram_initf => g_dpram_initf,
g_fabric_iface => ETHERBONE)
port map (
areset_n_i => areset_n,
......
top/svec_ref_design/svec_wr_ref_top.vhd
View file @ 69d808db
......@@ -61,6 +61,13 @@ library unisim;
use unisim.vcomponents.all;
entity svec_wr_ref_top is
generic (
g_dpram_initf : string := "../../bin/wrpc/wrc_phy8.bram";
-- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
-- changed to non-zero in the instantiation of the top level DUT in the testbench.
-- Its purpose is to reduce some internal counters/timeouts to speed up simulations.
g_simulation : integer := 0
);
port (
---------------------------------------------------------------------------
-- Clocks/resets
......@@ -347,8 +354,9 @@ begin -- architecture top
cmp_xwrc_board_svec : xwrc_board_svec
generic map (
g_simulation => g_simulation,
g_with_external_clock_input => TRUE,
g_dpram_initf => "../../bin/wrpc/wrc_phy8.bram",
g_dpram_initf => g_dpram_initf,
g_fabric_iface => ETHERBONE)
port map (
clk_20m_vcxo_i => clk_20m_vcxo_i,
......
top/vfchd_ref_design/vfchd_wr_ref_top.vhd
View file @ 69d808db
......@@ -59,6 +59,13 @@ use work.wr_vfchd_pkg.all;
use work.vfchd_i2cmux_pkg.all;
entity vfchd_wr_ref_top is
generic (
g_dpram_initf : string := "../../bin/wrpc/wrc_phy8.mif";
-- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
-- changed to non-zero in the instantiation of the top level DUT in the testbench.
-- Its purpose is to reduce some internal counters/timeouts to speed up simulations.
g_simulation : integer := 0
);
port (
---------------------------------------------------------------------------
-- Clocks/resets
......@@ -398,8 +405,9 @@ begin -- architecture top
cmp_xwrc_board_vfchd : xwrc_board_vfchd
generic map (
g_simulation => g_simulation,
g_with_external_clock_input => FALSE,
g_dpram_initf => "../../bin/wrpc/wrc_phy8.mif",
g_dpram_initf => g_dpram_initf,
g_fabric_iface => ETHERBONE)
port map (
clk_board_125m_i => clk_board_125m_i,
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment