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White Rabbit core collection
Commit 6a12587f authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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wr_core: updating the core and a reference design to feed phy_rdy_i of the endpoint 

phy_rdy_i was needed to fix the Virtex-6 FIFO reseting issue on the WRS.
However, WRPC uses inferred fifo which has fully asynchronous reset and does not
suffer from this bug. Therefore in case of the WRPC this signal can be tied to
'1' or drived from the GTP serdes.
parent cfdf688c
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modules/wrc_core/wr_core.vhd
View file @ 6a12587f
......@@ -152,6 +152,7 @@ entity wr_core is
phy_rst_o : out std_logic;
phy_loopen_o : out std_logic;
phy_rdy_i : in std_logic := '1';
-----------------------------------------
--GPIO
......@@ -648,6 +649,7 @@ begin
phy_rst_o => phy_rst_o,
phy_loopen_o => phy_loopen_o,
phy_rdy_i => phy_rdy_i,
phy_ref_clk_i => phy_ref_clk_i,
phy_tx_data_o => phy_tx_data_int,
phy_tx_k_o => phy_tx_k_int,
......
modules/wrc_core/wrcore_pkg.vhd
View file @ 6a12587f
......@@ -340,6 +340,7 @@ package wrcore_pkg is
phy_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
phy_rst_o : out std_logic;
phy_loopen_o : out std_logic;
phy_rdy_i : in std_logic := '1';
led_act_o : out std_logic;
led_link_o : out std_logic;
......@@ -472,6 +473,7 @@ package wrcore_pkg is
phy_rst_o : out std_logic;
phy_loopen_o : out std_logic;
phy_rdy_i : in std_logic := '1';
-----------------------------------------
--GPIO
......
modules/wrc_core/xwr_core.vhd
View file @ 6a12587f
......@@ -136,6 +136,7 @@ entity xwr_core is
phy_rst_o : out std_logic;
phy_loopen_o : out std_logic;
phy_rdy_i : in std_logic := '1';
-----------------------------------------
--GPIO
......@@ -268,6 +269,7 @@ begin
phy_rx_bitslide_i => phy_rx_bitslide_i,
phy_rst_o => phy_rst_o,
phy_loopen_o => phy_loopen_o,
phy_rdy_i => phy_rdy_i,
led_act_o => led_act_o,
led_link_o => led_link_o,
......
platform/xilinx/wr_xilinx_pkg.vhd
View file @ 6a12587f
......@@ -28,6 +28,7 @@ package wr_xilinx_pkg is
ch0_rx_bitslide_o : out std_logic_vector(3 downto 0);
ch0_rst_i : in std_logic := '0';
ch0_loopen_i : in std_logic := '0';
ch0_rdy_o : out std_logic;
ch1_ref_clk_i : in std_logic;
ch1_tx_data_i : in std_logic_vector(7 downto 0) := "00000000";
ch1_tx_k_i : in std_logic := '0';
......@@ -40,6 +41,7 @@ package wr_xilinx_pkg is
ch1_rx_bitslide_o : out std_logic_vector(3 downto 0);
ch1_rst_i : in std_logic := '0';
ch1_loopen_i : in std_logic := '0';
ch1_rdy_o : out std_logic;
pad_txn0_o : out std_logic;
pad_txp0_o : out std_logic;
pad_rxn0_i : in std_logic := '0';
......
top/spec_1_1/wr_core_demo/spec_top.vhd
View file @ 6a12587f
......@@ -359,6 +359,7 @@ architecture rtl of spec_top is
signal phy_rx_bitslide : std_logic_vector(3 downto 0);
signal phy_rst : std_logic;
signal phy_loopen : std_logic;
signal phy_rdy : std_logic;
signal dio_in : std_logic_vector(4 downto 0);
signal dio_out : std_logic_vector(4 downto 0);
......@@ -692,6 +693,7 @@ begin
phy_rx_bitslide_i => phy_rx_bitslide,
phy_rst_o => phy_rst,
phy_loopen_o => phy_loopen,
phy_rdy_i => phy_rdy,
led_act_o => LED_RED,
led_link_o => LED_GREEN,
......@@ -797,6 +799,7 @@ begin
ch0_rx_bitslide_o => open,
ch0_rst_i => '1',
ch0_loopen_i => '0',
ch0_rdy_o => open,
ch1_ref_clk_i => clk_125m_pllref,
ch1_tx_data_i => phy_tx_data,
......@@ -810,6 +813,7 @@ begin
ch1_rx_bitslide_o => phy_rx_bitslide,
ch1_rst_i => phy_rst,
ch1_loopen_i => phy_loopen,
ch1_rdy_o => phy_rdy,
pad_txn0_o => open,
pad_txp0_o => open,
pad_rxn0_i => '0',
......
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