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White Rabbit core collection
Commits
6b8136ef
Commit
6b8136ef
authored
Feb 03, 2017
by
Peter Jansweijer
Committed by
Grzegorz Daniluk
Dec 13, 2017
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disentangled artix, kintex and virtex into family7-gtp, gtx, gth and updated manifest.py
(cherry picked from commit
6d689ad2
)
parent
f0155974
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5 changed files
with
25 additions
and
22 deletions
+25
-22
Manifest.py
platform/xilinx/wr_gtp_phy/Manifest.py
+8
-5
whiterabbit_gthe2_channel_wrapper_gt.vhd
..._phy/family7-gth/whiterabbit_gthe2_channel_wrapper_gt.vhd
+2
-2
wr_gth_phy_family7.vhd
...form/xilinx/wr_gtp_phy/family7-gth/wr_gth_phy_family7.vhd
+5
-5
wr_gtp_phy_family7.vhd
...form/xilinx/wr_gtp_phy/family7-gtp/wr_gtp_phy_family7.vhd
+6
-6
wr_gtx_phy_family7.vhd
...form/xilinx/wr_gtp_phy/family7-gtx/wr_gtx_phy_family7.vhd
+4
-4
No files found.
platform/xilinx/wr_gtp_phy/Manifest.py
View file @
6b8136ef
...
@@ -12,16 +12,19 @@ elif (syn_device[0:4].upper()=="XC6V"): # Virtex6
...
@@ -12,16 +12,19 @@ elif (syn_device[0:4].upper()=="XC6V"): # Virtex6
"virtex6/gtp_phase_align_virtex6.vhd"
,
"virtex6/gtp_phase_align_virtex6.vhd"
,
"virtex6/gtx_reset.vhd"
])
"virtex6/gtx_reset.vhd"
])
elif
(
syn_device
[
0
:
4
]
.
upper
()
==
"XC7A"
):
# Family 7 GTP (Artix7)
elif
(
syn_device
[
0
:
4
]
.
upper
()
==
"XC7A"
):
# Family 7 GTP (Artix7)
files
.
extend
([
"family7-gtp/wr_gtp_phy_
artix
7.vhd"
,
files
.
extend
([
"family7-gtp/wr_gtp_phy_
family
7.vhd"
,
"family7-gtp/whiterabbit_gtpe2_channel_wrapper.vhd"
,
"family7-gtp/whiterabbit_gtpe2_channel_wrapper.vhd"
,
"family7-gtp/whiterabbit_gtpe2_channel_wrapper_gt.vhd"
,
"family7-gtp/whiterabbit_gtpe2_channel_wrapper_gt.vhd"
,
"family7-gtp/whiterabbit_gtpe2_channel_wrapper_gtrxreset_seq.vhd"
]);
"family7-gtp/whiterabbit_gtpe2_channel_wrapper_gtrxreset_seq.vhd"
]);
elif
(
syn_device
[
0
:
4
]
.
upper
()
==
"XC7K"
or
# Family 7 GTX (Kintex
-7 and Virtex
585, 2000, X485)
elif
(
syn_device
[
0
:
4
]
.
upper
()
==
"XC7K"
or
# Family 7 GTX (Kintex
7 and Virtex7
585, 2000, X485)
syn_device
[
0
:
7
]
.
upper
()
==
"XC7V585"
or
syn_device
[
0
:
7
]
.
upper
()
==
"XC7V585"
or
syn_device
[
0
:
8
]
.
upper
()
==
"XC7V2000"
or
syn_device
[
0
:
8
]
.
upper
()
==
"XC7V2000"
or
syn_device
[
0
:
8
]
.
upper
()
==
"XC7VX485"
):
syn_device
[
0
:
8
]
.
upper
()
==
"XC7VX485"
):
files
.
extend
([
"family7-gtx/wr_gtx_phy_
kintex
7.vhd"
,
files
.
extend
([
"family7-gtx/wr_gtx_phy_
family
7.vhd"
,
"family7-gtx/whiterabbit_gtxe2_channel_wrapper_gt.vhd"
]);
"family7-gtx/whiterabbit_gtxe2_channel_wrapper_gt.vhd"
]);
#elif (syn_device[0:4].upper()=="XC7V"): # Virtex7
elif
(
syn_device
[
0
:
4
]
.
upper
()
==
"XC7V"
):
# Family 7 GTH (other Virtex7 devices)
# files.extend(["family7-gth/wr_gth_phy_virtex7.vhd" ]);
files
.
extend
([
"family7-gth/wr_gth_phy_family7.vhd"
,
"whiterabbit_gthe2_channel_wrapper_gt.vhd"
,
"whiterabbit_gthe2_channel_wrapper_gtrxreset_seq.vhd"
,
"whiterabbit_gthe2_channel_wrapper_sync_block.vhd"
]);
\ No newline at end of file
platform/xilinx/wr_gtp_phy/family7-gth/whiterabbit_gthe2_channel_wrapper_gt.vhd
View file @
6b8136ef
...
@@ -366,8 +366,8 @@ begin
...
@@ -366,8 +366,8 @@ begin
RX_BIAS_CFG
=>
(
"000011000000000000010000"
),
RX_BIAS_CFG
=>
(
"000011000000000000010000"
),
DMONITOR_CFG
=>
(
x"000A00"
),
DMONITOR_CFG
=>
(
x"000A00"
),
RX_CM_SEL
=>
(
"11"
),
-- RX_CM_SEL was generated "01" as default by ISE for GND.
RX_CM_SEL
=>
(
"11"
),
-- RX_CM_SEL was generated "01" as default by ISE for GND.
-- Bitslider wont work with GND, it has to be "11" to select
-- Bitslider wont work with GND, it has to be "11" to select
-- programmable voltage (800mV).
-- programmable voltage (800mV).
RX_CM_TRIM
=>
(
"1010"
),
RX_CM_TRIM
=>
(
"1010"
),
RX_DEBUG_CFG
=>
(
"00000000000000"
),
RX_DEBUG_CFG
=>
(
"00000000000000"
),
RX_OS_CFG
=>
(
"0000010000000"
),
RX_OS_CFG
=>
(
"0000010000000"
),
...
...
platform/xilinx/wr_gtp_phy/family7-gth/wr_gth_phy_
virtex
7.vhd
→
platform/xilinx/wr_gtp_phy/family7-gth/wr_gth_phy_
family
7.vhd
View file @
6b8136ef
...
@@ -2,7 +2,7 @@
...
@@ -2,7 +2,7 @@
-- Title : Deterministic Xilinx GTX wrapper - kintex-7 top module
-- Title : Deterministic Xilinx GTX wrapper - kintex-7 top module
-- Project : White Rabbit Switch
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- File : wr_gth_phy_
virtex
7.vhd
-- File : wr_gth_phy_
family
7.vhd
-- Author : Peter Jansweijer, Muriel van der Spek, Tomasz Wlostowski
-- Author : Peter Jansweijer, Muriel van der Spek, Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Company : CERN BE-CO-HT
-- Created : 2017-02-02
-- Created : 2017-02-02
...
@@ -51,7 +51,7 @@ use unisim.vcomponents.all;
...
@@ -51,7 +51,7 @@ use unisim.vcomponents.all;
library
work
;
library
work
;
use
work
.
disparity_gen_pkg
.
all
;
use
work
.
disparity_gen_pkg
.
all
;
entity
wr_gth_phy_
virtex
7
is
entity
wr_gth_phy_
family
7
is
generic
(
generic
(
-- set to non-zero value to speed up the simulation by reducing some delays
-- set to non-zero value to speed up the simulation by reducing some delays
g_simulation
:
integer
:
=
0
);
g_simulation
:
integer
:
=
0
);
...
@@ -113,9 +113,9 @@ entity wr_gth_phy_virtex7 is
...
@@ -113,9 +113,9 @@ entity wr_gth_phy_virtex7 is
-- PHY ready
-- PHY ready
rdy_o
:
out
std_logic
);
rdy_o
:
out
std_logic
);
end
entity
wr_gth_phy_
virtex
7
;
end
entity
wr_gth_phy_
family
7
;
architecture
rtl
of
wr_gth_phy_
virtex
7
is
architecture
rtl
of
wr_gth_phy_
family
7
is
component
whiterabbit_gthe2_channel_wrapper_gt
is
component
whiterabbit_gthe2_channel_wrapper_gt
is
generic
(
generic
(
...
@@ -431,5 +431,5 @@ begin
...
@@ -431,5 +431,5 @@ begin
end
process
;
end
process
;
tx_disparity_o
<=
to_std_logic
(
cur_disp
);
tx_disparity_o
<=
to_std_logic
(
cur_disp
);
end
architecture
rtl
;
-- of wr_gth_phy_
virtex
7
end
architecture
rtl
;
-- of wr_gth_phy_
family
7
platform/xilinx/wr_gtp_phy/family7-gtp/wr_gtp_phy_
artix
7.vhd
→
platform/xilinx/wr_gtp_phy/family7-gtp/wr_gtp_phy_
family
7.vhd
View file @
6b8136ef
...
@@ -2,7 +2,7 @@
...
@@ -2,7 +2,7 @@
-- Title : Deterministic Xilinx GTP wrapper - artix-7 top module
-- Title : Deterministic Xilinx GTP wrapper - artix-7 top module
-- Project : White Rabbit Switch
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- File : wr_gtp_phy_
artix
7.vhd
-- File : wr_gtp_phy_
family
7.vhd
-- Author : Peter Jansweijer, Rick Lohlefink, Tomasz Wlostowski
-- Author : Peter Jansweijer, Rick Lohlefink, Tomasz Wlostowski
-- Company : Nikhef, CERN BE-CO-HT
-- Company : Nikhef, CERN BE-CO-HT
-- Created : 2016-05-19
-- Created : 2016-05-19
...
@@ -52,7 +52,7 @@ library work;
...
@@ -52,7 +52,7 @@ library work;
use
work
.
disparity_gen_pkg
.
all
;
use
work
.
disparity_gen_pkg
.
all
;
entity
wr_gtp_phy_
artix
7
is
entity
wr_gtp_phy_
family
7
is
generic
(
generic
(
-- set to non-zero value to speed up the simulation by reducing some delays
-- set to non-zero value to speed up the simulation by reducing some delays
g_simulation
:
integer
:
=
0
g_simulation
:
integer
:
=
0
...
@@ -112,14 +112,14 @@ entity wr_gtp_phy_artix7 is
...
@@ -112,14 +112,14 @@ entity wr_gtp_phy_artix7 is
rdy_o
:
out
std_logic
rdy_o
:
out
std_logic
);
);
end
entity
wr_gtp_phy_
artix
7
;
end
entity
wr_gtp_phy_
family
7
;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Object : Architecture work.wr_gtp_phy_
artix
7.structure
-- Object : Architecture work.wr_gtp_phy_
family
7.structure
-- Last modified : Mon Nov 23 12:54:18 2015.
-- Last modified : Mon Nov 23 12:54:18 2015.
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
architecture
structure
of
wr_gtp_phy_
artix
7
is
architecture
structure
of
wr_gtp_phy_
family
7
is
constant
REQ_DELAY
:
integer
:
=
500
;
-- unit = ns
constant
REQ_DELAY
:
integer
:
=
500
;
-- unit = ns
constant
CLK_PER
:
integer
:
=
8
;
-- unit = ns
constant
CLK_PER
:
integer
:
=
8
;
-- unit = ns
constant
INITIAL_WAIT_CYCLES
:
integer
:
=
REQ_DELAY
/
CLK_PER
;
-- Required 500 ns divided by RefClk period
constant
INITIAL_WAIT_CYCLES
:
integer
:
=
REQ_DELAY
/
CLK_PER
;
-- Required 500 ns divided by RefClk period
...
@@ -517,5 +517,5 @@ begin
...
@@ -517,5 +517,5 @@ begin
end
process
;
end
process
;
tx_disparity_o
<=
to_std_logic
(
cur_disp
);
tx_disparity_o
<=
to_std_logic
(
cur_disp
);
end
architecture
structure
;
-- of wr_gtp_phy_
artix
7
end
architecture
structure
;
-- of wr_gtp_phy_
family
7
platform/xilinx/wr_gtp_phy/family7-gtx/wr_gtx_phy_
kintex
7.vhd
→
platform/xilinx/wr_gtp_phy/family7-gtx/wr_gtx_phy_
family
7.vhd
View file @
6b8136ef
...
@@ -2,7 +2,7 @@
...
@@ -2,7 +2,7 @@
-- Title : Deterministic Xilinx GTX wrapper - kintex-7 top module
-- Title : Deterministic Xilinx GTX wrapper - kintex-7 top module
-- Project : White Rabbit Switch
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- File : wr_gtx_phy_
kintex
7.vhd
-- File : wr_gtx_phy_
family
7.vhd
-- Author : Peter Jansweijer, Tomasz Wlostowski
-- Author : Peter Jansweijer, Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Company : CERN BE-CO-HT
-- Created : 2013-04-08
-- Created : 2013-04-08
...
@@ -54,7 +54,7 @@ library work;
...
@@ -54,7 +54,7 @@ library work;
--use work.gencores_pkg.all;
--use work.gencores_pkg.all;
use
work
.
disparity_gen_pkg
.
all
;
use
work
.
disparity_gen_pkg
.
all
;
entity
wr_gtx_phy_
kintex
7
is
entity
wr_gtx_phy_
family
7
is
generic
(
generic
(
-- set to non-zero value to speed up the simulation by reducing some delays
-- set to non-zero value to speed up the simulation by reducing some delays
...
@@ -114,9 +114,9 @@ entity wr_gtx_phy_kintex7 is
...
@@ -114,9 +114,9 @@ entity wr_gtx_phy_kintex7 is
pad_rxp_i
:
in
std_logic
:
=
'0'
;
pad_rxp_i
:
in
std_logic
:
=
'0'
;
rdy_o
:
out
std_logic
);
rdy_o
:
out
std_logic
);
end
wr_gtx_phy_
kintex
7
;
end
wr_gtx_phy_
family
7
;
architecture
rtl
of
wr_gtx_phy_
kintex
7
is
architecture
rtl
of
wr_gtx_phy_
family
7
is
component
WHITERABBIT_GTXE2_CHANNEL_WRAPPER_GT
is
component
WHITERABBIT_GTXE2_CHANNEL_WRAPPER_GT
is
generic
generic
...
...
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