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White Rabbit core collection
Commit 6d689ad2 authored by Peter Jansweijer's avatar Peter Jansweijer
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disentangled artix, kintex and virtex into family7-gtp, gtx, gth and updated manifest.py

parent 70bf1927
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Showing with 25 additions and 22 deletions
platform/xilinx/wr_gtp_phy/Manifest.py
View file @ 6d689ad2
......@@ -12,16 +12,19 @@ elif (syn_device[0:4].upper()=="XC6V"): # Virtex6
"virtex6/gtp_phase_align_virtex6.vhd",
"virtex6/gtx_reset.vhd"])
elif (syn_device[0:4].upper()=="XC7A"): # Family 7 GTP (Artix7)
files.extend(["family7-gtp/wr_gtp_phy_artix7.vhd",
files.extend(["family7-gtp/wr_gtp_phy_family7.vhd",
"family7-gtp/whiterabbit_gtpe2_channel_wrapper.vhd",
"family7-gtp/whiterabbit_gtpe2_channel_wrapper_gt.vhd",
"family7-gtp/whiterabbit_gtpe2_channel_wrapper_gtrxreset_seq.vhd" ]);
elif (syn_device[0:4].upper()=="XC7K" or # Family 7 GTX (Kintex-7 and Virtex 585, 2000, X485)
elif (syn_device[0:4].upper()=="XC7K" or # Family 7 GTX (Kintex7 and Virtex7 585, 2000, X485)
syn_device[0:7].upper()=="XC7V585" or
syn_device[0:8].upper()=="XC7V2000" or
syn_device[0:8].upper()=="XC7VX485"):
files.extend(["family7-gtx/wr_gtx_phy_kintex7.vhd",
files.extend(["family7-gtx/wr_gtx_phy_family7.vhd",
"family7-gtx/whiterabbit_gtxe2_channel_wrapper_gt.vhd"]);
#elif (syn_device[0:4].upper()=="XC7V"): # Virtex7
# files.extend(["family7-gth/wr_gth_phy_virtex7.vhd" ]);
elif (syn_device[0:4].upper()=="XC7V"): # Family 7 GTH (other Virtex7 devices)
files.extend(["family7-gth/wr_gth_phy_family7.vhd",
"whiterabbit_gthe2_channel_wrapper_gt.vhd",
"whiterabbit_gthe2_channel_wrapper_gtrxreset_seq.vhd",
"whiterabbit_gthe2_channel_wrapper_sync_block.vhd" ]);
\ No newline at end of file
platform/xilinx/wr_gtp_phy/family7-gth/whiterabbit_gthe2_channel_wrapper_gt.vhd
View file @ 6d689ad2
......@@ -366,8 +366,8 @@ begin
RX_BIAS_CFG => ("000011000000000000010000"),
DMONITOR_CFG => (x"000A00"),
RX_CM_SEL => ("11"), -- RX_CM_SEL was generated "01" as default by ISE for GND.
-- Bitslider wont work with GND, it has to be "11" to select
-- programmable voltage (800mV).
-- Bitslider wont work with GND, it has to be "11" to select
-- programmable voltage (800mV).
RX_CM_TRIM => ("1010"),
RX_DEBUG_CFG => ("00000000000000"),
RX_OS_CFG => ("0000010000000"),
......
platform/xilinx/wr_gtp_phy/family7-gth/wr_gth_phy_virtex7.vhd → platform/xilinx/wr_gtp_phy/family7-gth/wr_gth_phy_family7.vhd
View file @ 6d689ad2
......@@ -2,7 +2,7 @@
-- Title : Deterministic Xilinx GTX wrapper - kintex-7 top module
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : wr_gth_phy_virtex7.vhd
-- File : wr_gth_phy_family7.vhd
-- Author : Peter Jansweijer, Muriel van der Spek, Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2017-02-02
......@@ -51,7 +51,7 @@ use unisim.vcomponents.all;
library work;
use work.disparity_gen_pkg.all;
entity wr_gth_phy_virtex7 is
entity wr_gth_phy_family7 is
generic(
-- set to non-zero value to speed up the simulation by reducing some delays
g_simulation : integer := 0);
......@@ -113,9 +113,9 @@ entity wr_gth_phy_virtex7 is
-- PHY ready
rdy_o : out std_logic);
end entity wr_gth_phy_virtex7;
end entity wr_gth_phy_family7;
architecture rtl of wr_gth_phy_virtex7 is
architecture rtl of wr_gth_phy_family7 is
component whiterabbit_gthe2_channel_wrapper_gt is
generic (
......@@ -431,5 +431,5 @@ begin
end process;
tx_disparity_o <= to_std_logic(cur_disp);
end architecture rtl ; -- of wr_gth_phy_virtex7
end architecture rtl ; -- of wr_gth_phy_family7
platform/xilinx/wr_gtp_phy/family7-gtp/wr_gtp_phy_artix7.vhd → platform/xilinx/wr_gtp_phy/family7-gtp/wr_gtp_phy_family7.vhd
View file @ 6d689ad2
......@@ -2,7 +2,7 @@
-- Title : Deterministic Xilinx GTP wrapper - artix-7 top module
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : wr_gtp_phy_artix7.vhd
-- File : wr_gtp_phy_family7.vhd
-- Author : Peter Jansweijer, Rick Lohlefink, Tomasz Wlostowski
-- Company : Nikhef, CERN BE-CO-HT
-- Created : 2016-05-19
......@@ -52,7 +52,7 @@ library work;
use work.disparity_gen_pkg.all;
entity wr_gtp_phy_artix7 is
entity wr_gtp_phy_family7 is
generic (
-- set to non-zero value to speed up the simulation by reducing some delays
g_simulation : integer := 0
......@@ -112,14 +112,14 @@ entity wr_gtp_phy_artix7 is
rdy_o : out std_logic
);
end entity wr_gtp_phy_artix7;
end entity wr_gtp_phy_family7;
--------------------------------------------------------------------------------
-- Object : Architecture work.wr_gtp_phy_artix7.structure
-- Object : Architecture work.wr_gtp_phy_family7.structure
-- Last modified : Mon Nov 23 12:54:18 2015.
--------------------------------------------------------------------------------
architecture structure of wr_gtp_phy_artix7 is
architecture structure of wr_gtp_phy_family7 is
constant REQ_DELAY : integer := 500; -- unit = ns
constant CLK_PER : integer := 8; -- unit = ns
constant INITIAL_WAIT_CYCLES : integer := REQ_DELAY / CLK_PER; -- Required 500 ns divided by RefClk period
......@@ -517,5 +517,5 @@ begin
end process;
tx_disparity_o <= to_std_logic(cur_disp);
end architecture structure ; -- of wr_gtp_phy_artix7
end architecture structure ; -- of wr_gtp_phy_family7
platform/xilinx/wr_gtp_phy/family7-gtx/wr_gtx_phy_kintex7.vhd → platform/xilinx/wr_gtp_phy/family7-gtx/wr_gtx_phy_family7.vhd
View file @ 6d689ad2
......@@ -2,7 +2,7 @@
-- Title : Deterministic Xilinx GTX wrapper - kintex-7 top module
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : wr_gtx_phy_kintex7.vhd
-- File : wr_gtx_phy_family7.vhd
-- Author : Peter Jansweijer, Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2013-04-08
......@@ -54,7 +54,7 @@ library work;
--use work.gencores_pkg.all;
use work.disparity_gen_pkg.all;
entity wr_gtx_phy_kintex7 is
entity wr_gtx_phy_family7 is
generic (
-- set to non-zero value to speed up the simulation by reducing some delays
......@@ -114,9 +114,9 @@ entity wr_gtx_phy_kintex7 is
pad_rxp_i : in std_logic := '0';
rdy_o : out std_logic);
end wr_gtx_phy_kintex7;
end wr_gtx_phy_family7;
architecture rtl of wr_gtx_phy_kintex7 is
architecture rtl of wr_gtx_phy_family7 is
component WHITERABBIT_GTXE2_CHANNEL_WRAPPER_GT is
generic
......
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