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White Rabbit core collection
Commit 6e339ab1 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana Committed by Grzegorz Daniluk
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[spi-flash]: cs pin driven also from syscon 

Signed-off-by: Grzegorz Daniluk's avatarGrzegorz Daniluk <grzegorz.daniluk@cern.ch>
parent 47bfe8f0
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Showing with 103 additions and 29 deletions
modules/wrc_core/wr_core.vhd
View file @ 6e339ab1
......@@ -167,6 +167,7 @@ entity wr_core is
btn1_i : in std_logic := '1';
btn2_i : in std_logic := '1';
spi_sclk_o : out std_logic;
spi_cs_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic := '0';
......@@ -761,6 +762,7 @@ begin
btn1_i => btn1_i,
btn2_i => btn2_i,
spi_sclk_o => spi_sclk_o,
spi_cs_o => spi_cs_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i,
......
modules/wrc_core/wrc_periph.vhd
View file @ 6e339ab1
......@@ -256,6 +256,12 @@ begin
spi_sclk_o <= '0';
end if;
if(sysc_regs_o.gpsr_spi_cs_load_o = '1' and sysc_regs_o.gpsr_spi_cs_o = '1') then
spi_sclk_o <= '1';
elsif(sysc_regs_o.gpcr_spi_cs_o = '1') then
spi_sclk_o <= '0';
end if;
if(sysc_regs_o.gpsr_spi_mosi_load_o = '1' and sysc_regs_o.gpsr_spi_mosi_o = '1') then
spi_mosi_o <= '1';
elsif(sysc_regs_o.gpcr_spi_mosi_o = '1') then
......@@ -264,6 +270,7 @@ begin
end if;
end process;
sysc_regs_i.gpsr_spi_sclk_i <= '0';
sysc_regs_i.gpsr_spi_cs_i <= '0';
sysc_regs_i.gpsr_spi_mosi_i <= '0';
sysc_regs_i.gpsr_spi_miso_i <= spi_miso_i;
......
modules/wrc_core/wrc_syscon_pkg.vhd
View file @ 6e339ab1
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wrc_syscon_pkg.vhd
-- Author : auto-generated by wbgen2 from wrc_syscon_wb.wb
-- Created : Wed Sep 25 08:57:01 2013
-- Created : Wed Sep 25 13:27:18 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
......@@ -28,6 +28,7 @@ package sysc_wbgen2_pkg is
gpsr_sfp_scl_i : std_logic;
gpsr_sfp_sda_i : std_logic;
gpsr_spi_sclk_i : std_logic;
gpsr_spi_cs_i : std_logic;
gpsr_spi_mosi_i : std_logic;
gpsr_spi_miso_i : std_logic;
hwfr_memsize_i : std_logic_vector(3 downto 0);
......@@ -44,6 +45,7 @@ package sysc_wbgen2_pkg is
gpsr_sfp_scl_i => '0',
gpsr_sfp_sda_i => '0',
gpsr_spi_sclk_i => '0',
gpsr_spi_cs_i => '0',
gpsr_spi_mosi_i => '0',
gpsr_spi_miso_i => '0',
hwfr_memsize_i => (others => '0'),
......@@ -70,6 +72,8 @@ package sysc_wbgen2_pkg is
gpsr_sfp_sda_load_o : std_logic;
gpsr_spi_sclk_o : std_logic;
gpsr_spi_sclk_load_o : std_logic;
gpsr_spi_cs_o : std_logic;
gpsr_spi_cs_load_o : std_logic;
gpsr_spi_mosi_o : std_logic;
gpsr_spi_mosi_load_o : std_logic;
gpcr_led_stat_o : std_logic;
......@@ -79,6 +83,7 @@ package sysc_wbgen2_pkg is
gpcr_sfp_scl_o : std_logic;
gpcr_sfp_sda_o : std_logic;
gpcr_spi_sclk_o : std_logic;
gpcr_spi_cs_o : std_logic;
gpcr_spi_mosi_o : std_logic;
tcr_enable_o : std_logic;
end record;
......@@ -100,6 +105,8 @@ package sysc_wbgen2_pkg is
gpsr_sfp_sda_load_o => '0',
gpsr_spi_sclk_o => '0',
gpsr_spi_sclk_load_o => '0',
gpsr_spi_cs_o => '0',
gpsr_spi_cs_load_o => '0',
gpsr_spi_mosi_o => '0',
gpsr_spi_mosi_load_o => '0',
gpcr_led_stat_o => '0',
......@@ -109,6 +116,7 @@ package sysc_wbgen2_pkg is
gpcr_sfp_scl_o => '0',
gpcr_sfp_sda_o => '0',
gpcr_spi_sclk_o => '0',
gpcr_spi_cs_o => '0',
gpcr_spi_mosi_o => '0',
tcr_enable_o => '0'
);
......@@ -149,6 +157,7 @@ tmp.gpsr_sfp_det_i := f_x_to_zero(left.gpsr_sfp_det_i) or f_x_to_zero(right.gpsr
tmp.gpsr_sfp_scl_i := f_x_to_zero(left.gpsr_sfp_scl_i) or f_x_to_zero(right.gpsr_sfp_scl_i);
tmp.gpsr_sfp_sda_i := f_x_to_zero(left.gpsr_sfp_sda_i) or f_x_to_zero(right.gpsr_sfp_sda_i);
tmp.gpsr_spi_sclk_i := f_x_to_zero(left.gpsr_spi_sclk_i) or f_x_to_zero(right.gpsr_spi_sclk_i);
tmp.gpsr_spi_cs_i := f_x_to_zero(left.gpsr_spi_cs_i) or f_x_to_zero(right.gpsr_spi_cs_i);
tmp.gpsr_spi_mosi_i := f_x_to_zero(left.gpsr_spi_mosi_i) or f_x_to_zero(right.gpsr_spi_mosi_i);
tmp.gpsr_spi_miso_i := f_x_to_zero(left.gpsr_spi_miso_i) or f_x_to_zero(right.gpsr_spi_miso_i);
tmp.hwfr_memsize_i := f_x_to_zero(left.hwfr_memsize_i) or f_x_to_zero(right.hwfr_memsize_i);
......
modules/wrc_core/wrc_syscon_regs.h
View file @ 6e339ab1
......@@ -3,7 +3,7 @@
* File : wrc_syscon_regs.h
* Author : auto-generated by wbgen2 from wrc_syscon_wb.wb
* Created : Wed Sep 25 08:57:01 2013
* Created : Wed Sep 25 13:27:18 2013
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
......@@ -77,11 +77,14 @@
/* definitions for field: SPI bitbanged SCLK in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_SPI_SCLK WBGEN2_GEN_MASK(10, 1)
/* definitions for field: SPI bitbanged CS in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_SPI_CS WBGEN2_GEN_MASK(11, 1)
/* definitions for field: SPI bitbanged MOSI in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_SPI_MOSI WBGEN2_GEN_MASK(11, 1)
#define SYSC_GPSR_SPI_MOSI WBGEN2_GEN_MASK(12, 1)
/* definitions for field: SPI bitbanged MISO in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_SPI_MISO WBGEN2_GEN_MASK(12, 1)
#define SYSC_GPSR_SPI_MISO WBGEN2_GEN_MASK(13, 1)
/* definitions for register: GPIO Clear Register */
......@@ -106,8 +109,11 @@
/* definitions for field: SPI bitbanged SCLK in reg: GPIO Clear Register */
#define SYSC_GPCR_SPI_SCLK WBGEN2_GEN_MASK(10, 1)
/* definitions for field: SPI bitbanged CS in reg: GPIO Clear Register */
#define SYSC_GPCR_SPI_CS WBGEN2_GEN_MASK(11, 1)
/* definitions for field: SPI bitbanged MOSI in reg: GPIO Clear Register */
#define SYSC_GPCR_SPI_MOSI WBGEN2_GEN_MASK(11, 1)
#define SYSC_GPCR_SPI_MOSI WBGEN2_GEN_MASK(12, 1)
/* definitions for register: Hardware Feature Register */
......
modules/wrc_core/wrc_syscon_wb.vhd
View file @ 6e339ab1
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wrc_syscon_wb.vhd
-- Author : auto-generated by wbgen2 from wrc_syscon_wb.wb
-- Created : Wed Sep 25 08:57:01 2013
-- Created : Wed Sep 25 13:27:18 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
......@@ -58,6 +58,8 @@ signal sysc_gpcr_sfp_sda_dly0 : std_logic ;
signal sysc_gpcr_sfp_sda_int : std_logic ;
signal sysc_gpcr_spi_sclk_dly0 : std_logic ;
signal sysc_gpcr_spi_sclk_int : std_logic ;
signal sysc_gpcr_spi_cs_dly0 : std_logic ;
signal sysc_gpcr_spi_cs_int : std_logic ;
signal sysc_gpcr_spi_mosi_dly0 : std_logic ;
signal sysc_gpcr_spi_mosi_int : std_logic ;
signal sysc_tcr_enable_int : std_logic ;
......@@ -98,6 +100,7 @@ begin
regs_o.gpsr_sfp_scl_load_o <= '0';
regs_o.gpsr_sfp_sda_load_o <= '0';
regs_o.gpsr_spi_sclk_load_o <= '0';
regs_o.gpsr_spi_cs_load_o <= '0';
regs_o.gpsr_spi_mosi_load_o <= '0';
sysc_gpcr_led_stat_int <= '0';
sysc_gpcr_led_link_int <= '0';
......@@ -106,6 +109,7 @@ begin
sysc_gpcr_sfp_scl_int <= '0';
sysc_gpcr_sfp_sda_int <= '0';
sysc_gpcr_spi_sclk_int <= '0';
sysc_gpcr_spi_cs_int <= '0';
sysc_gpcr_spi_mosi_int <= '0';
sysc_tcr_enable_int <= '0';
elsif rising_edge(clk_sys_i) then
......@@ -123,6 +127,7 @@ begin
regs_o.gpsr_sfp_scl_load_o <= '0';
regs_o.gpsr_sfp_sda_load_o <= '0';
regs_o.gpsr_spi_sclk_load_o <= '0';
regs_o.gpsr_spi_cs_load_o <= '0';
regs_o.gpsr_spi_mosi_load_o <= '0';
sysc_gpcr_led_stat_int <= '0';
sysc_gpcr_led_link_int <= '0';
......@@ -131,6 +136,7 @@ begin
sysc_gpcr_sfp_scl_int <= '0';
sysc_gpcr_sfp_sda_int <= '0';
sysc_gpcr_spi_sclk_int <= '0';
sysc_gpcr_spi_cs_int <= '0';
sysc_gpcr_spi_mosi_int <= '0';
ack_in_progress <= '0';
else
......@@ -140,6 +146,7 @@ begin
regs_o.gpsr_sfp_scl_load_o <= '0';
regs_o.gpsr_sfp_sda_load_o <= '0';
regs_o.gpsr_spi_sclk_load_o <= '0';
regs_o.gpsr_spi_cs_load_o <= '0';
regs_o.gpsr_spi_mosi_load_o <= '0';
end if;
else
......@@ -194,22 +201,23 @@ begin
regs_o.gpsr_sfp_scl_load_o <= '1';
regs_o.gpsr_sfp_sda_load_o <= '1';
regs_o.gpsr_spi_sclk_load_o <= '1';
regs_o.gpsr_spi_cs_load_o <= '1';
regs_o.gpsr_spi_mosi_load_o <= '1';
end if;
rddata_reg(0) <= '0';
rddata_reg(1) <= '0';
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= regs_i.gpsr_fmc_scl_i;
rddata_reg(3) <= regs_i.gpsr_fmc_sda_i;
rddata_reg(4) <= '0';
rddata_reg(4) <= 'X';
rddata_reg(5) <= regs_i.gpsr_btn1_i;
rddata_reg(6) <= regs_i.gpsr_btn2_i;
rddata_reg(7) <= regs_i.gpsr_sfp_det_i;
rddata_reg(8) <= regs_i.gpsr_sfp_scl_i;
rddata_reg(9) <= regs_i.gpsr_sfp_sda_i;
rddata_reg(10) <= regs_i.gpsr_spi_sclk_i;
rddata_reg(11) <= regs_i.gpsr_spi_mosi_i;
rddata_reg(12) <= regs_i.gpsr_spi_miso_i;
rddata_reg(13) <= 'X';
rddata_reg(11) <= regs_i.gpsr_spi_cs_i;
rddata_reg(12) <= regs_i.gpsr_spi_mosi_i;
rddata_reg(13) <= regs_i.gpsr_spi_miso_i;
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
......@@ -239,16 +247,18 @@ begin
sysc_gpcr_sfp_scl_int <= wrdata_reg(8);
sysc_gpcr_sfp_sda_int <= wrdata_reg(9);
sysc_gpcr_spi_sclk_int <= wrdata_reg(10);
sysc_gpcr_spi_mosi_int <= wrdata_reg(11);
sysc_gpcr_spi_cs_int <= wrdata_reg(11);
sysc_gpcr_spi_mosi_int <= wrdata_reg(12);
end if;
rddata_reg(0) <= '0';
rddata_reg(1) <= '0';
rddata_reg(2) <= '0';
rddata_reg(3) <= '0';
rddata_reg(8) <= '0';
rddata_reg(9) <= '0';
rddata_reg(10) <= '0';
rddata_reg(11) <= '0';
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
......@@ -420,8 +430,10 @@ begin
regs_o.gpsr_sfp_sda_o <= wrdata_reg(9);
-- SPI bitbanged SCLK
regs_o.gpsr_spi_sclk_o <= wrdata_reg(10);
-- SPI bitbanged CS
regs_o.gpsr_spi_cs_o <= wrdata_reg(11);
-- SPI bitbanged MOSI
regs_o.gpsr_spi_mosi_o <= wrdata_reg(11);
regs_o.gpsr_spi_mosi_o <= wrdata_reg(12);
-- SPI bitbanged MISO
-- Status LED
process (clk_sys_i, rst_n_i)
......@@ -514,6 +526,19 @@ begin
end process;
-- SPI bitbanged CS
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
sysc_gpcr_spi_cs_dly0 <= '0';
regs_o.gpcr_spi_cs_o <= '0';
elsif rising_edge(clk_sys_i) then
sysc_gpcr_spi_cs_dly0 <= sysc_gpcr_spi_cs_int;
regs_o.gpcr_spi_cs_o <= sysc_gpcr_spi_cs_int and (not sysc_gpcr_spi_cs_dly0);
end if;
end process;
-- SPI bitbanged MOSI
process (clk_sys_i, rst_n_i)
begin
......
modules/wrc_core/wrc_syscon_wb.wb
View file @ 6e339ab1
......@@ -131,7 +131,7 @@ peripheral {
field {
name = "SPI bitbanged SCLK";
prefix = "spi_sclk";
description = "write 1: drive SPI clk to 1\
description = "write 1: drive SPI CLK to 1\
read: always 0";
type = BIT;
access_bus = READ_WRITE;
......@@ -140,6 +140,18 @@ peripheral {
align = 10;
};
field {
name = "SPI bitbanged CS";
prefix = "spi_cs";
description = "write 1: drive SPI CS to 1\
read: always 0";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
align = 11;
};
field {
name = "SPI bitbanged MOSI";
prefix = "spi_mosi";
......@@ -149,7 +161,7 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
align = 11;
align = 12;
};
field {
......@@ -160,7 +172,7 @@ peripheral {
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
load = LOAD_EXT;
align = 12;
align = 13;
};
};
......@@ -218,17 +230,25 @@ peripheral {
field {
name = "SPI bitbanged SCLK";
prefix = "spi_sclk";
description = "write 1: Set SPI clk line to 0.";
description = "write 1: Set SPI CLK line to 0.";
type = MONOSTABLE;
align = 10;
};
field {
name = "SPI bitbanged CS";
prefix = "spi_cs";
description = "write 1: Set SPI CS line to 0";
type = MONOSTABLE;
align = 11;
};
field {
name = "SPI bitbanged MOSI";
prefix = "spi_mosi";
description = "write 1: Set SPI MOSI line to 0.";
type = MONOSTABLE;
align = 11;
align = 12;
};
};
......
modules/wrc_core/wrcore_pkg.vhd
View file @ 6e339ab1
......@@ -216,6 +216,7 @@ package wrcore_pkg is
btn1_i : in std_logic;
btn2_i : in std_logic;
spi_sclk_o : out std_logic;
spi_cs_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic;
slave_i : in t_wishbone_slave_in_array(0 to 2);
......@@ -349,6 +350,7 @@ package wrcore_pkg is
btn1_i : in std_logic := 'H';
btn2_i : in std_logic := 'H';
spi_sclk_o : out std_logic;
spi_cs_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic := '0';
......@@ -480,6 +482,7 @@ package wrcore_pkg is
btn1_i : in std_logic := '1';
btn2_i : in std_logic := '1';
spi_sclk_o : out std_logic;
spi_cs_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic := '0';
......
modules/wrc_core/xwr_core.vhd
View file @ 6e339ab1
......@@ -151,6 +151,7 @@ entity xwr_core is
btn1_i : in std_logic := '1';
btn2_i : in std_logic := '1';
spi_sclk_o : out std_logic;
spi_cs_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic := '0';
......@@ -277,6 +278,7 @@ begin
btn1_i => btn1_i,
btn2_i => btn2_i,
spi_sclk_o => spi_sclk_o,
spi_cs_o => spi_cs_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i,
uart_rxd_i => uart_rxd_i,
......
top/spec_1_1/wr_core_demo/spec_top.vhd
View file @ 6e339ab1
......@@ -87,8 +87,8 @@ entity spec_top is
button1_i : in std_logic := 'H';
button2_i : in std_logic := 'H';
spi_ncs_o : out std_logic;
spi_sclk_o : out std_logic;
spi_cs_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic := 'L';
......@@ -705,6 +705,7 @@ begin
btn1_i => button1_i,
btn2_i => button2_i,
spi_sclk_o => spi_sclk_o,
spi_cs_o => spi_cs_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i,
......@@ -904,7 +905,6 @@ begin
dio_sdn_n_o <= '1';
sfp_tx_disable_o <= '0';
spi_ncs_o <= '0';
end rtl;
......
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