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White Rabbit core collection
Commit 6ec8f73a authored by A. Hahn's avatar A. Hahn
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arria10: scu4 -> removed autogenerated files (plls and phy)

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platform/altera/wr_arria10_scu4_phy/wr_arria10_scu4_atx_pll/wr_arria10_scu4_atx_pll/synth/wr_arria10_scu4_atx_pll.qicache deleted 100644 → 0
View file @ 091556ba
<?xml version='1.0' encoding='us-ascii'?>
<qsys_generation_info>
<qsys_file path="/home/alex/workspace/projects/r13/bel_projects/ip_cores/wr-cores/platform/altera/wr_arria10_scu4_phy/wr_arria10_scu4_atx_pll/wr_arria10_scu4_atx_pll.qsys" />
<gen_dir path="/home/alex/workspace/projects/r13/bel_projects/ip_cores/wr-cores/platform/altera/wr_arria10_scu4_phy/wr_arria10_scu4_atx_pll/wr_arria10_scu4_atx_pll/" />
<user_regen_policy value="Never Regenerate Existing IP" />
<actual_regen_policy value="Never Regenerate Existing IP" />
<gen_action value="IP Generation Skipped" />
<gen_status value="IP Generation Succeeded" />
</qsys_generation_info>
\ No newline at end of file
platform/altera/wr_arria10_scu4_phy/wr_arria10_scu4_atx_pll/wr_arria10_scu4_atx_pll/wr_arria10_scu4_atx_pll_generation.rpt deleted 100644 → 0
View file @ 091556ba
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate /home/alex/workspace/projects/r13/bel_projects/ip_cores/wr-cores/platform/altera/wr_arria10_scu4_phy/wr_arria10_scu4_atx_pll/wr_arria10_scu4_atx_pll.qsys --synthesis=VERILOG --output-directory=/home/alex/workspace/projects/r13/bel_projects/ip_cores/wr-cores/platform/altera/wr_arria10_scu4_phy/wr_arria10_scu4_atx_pll/wr_arria10_scu4_atx_pll --family="Arria 10" --part=10AX027E3F29E2SG
Progress: Loading wr_arria10_scu4_atx_pll/wr_arria10_scu4_atx_pll.qsys
Progress: Reading input file
Progress: Adding xcvr_atx_pll_a10_0 [altera_xcvr_atx_pll_a10 18.1]
Progress: Parameterizing module xcvr_atx_pll_a10_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: wr_arria10_scu4_atx_pll.xcvr_atx_pll_a10_0: For the selected device(10AX027E3F29E2SG), PLL speed grade is 3.
Info: wr_arria10_scu4_atx_pll: "Transforming system: wr_arria10_scu4_atx_pll"
Info: wr_arria10_scu4_atx_pll: Running transform generation_view_transform
Info: wr_arria10_scu4_atx_pll: Running transform generation_view_transform took 0.000s
Info: xcvr_atx_pll_a10_0: Running transform generation_view_transform
Info: xcvr_atx_pll_a10_0: Running transform generation_view_transform took 0.000s
Info: wr_arria10_scu4_atx_pll: Running transform merlin_avalon_transform
Info: wr_arria10_scu4_atx_pll: Running transform merlin_avalon_transform took 0.228s
Info: wr_arria10_scu4_atx_pll: "Naming system components in system: wr_arria10_scu4_atx_pll"
Info: wr_arria10_scu4_atx_pll: "Processing generation queue"
Info: wr_arria10_scu4_atx_pll: "Generating: wr_arria10_scu4_atx_pll"
Info: wr_arria10_scu4_atx_pll: "Generating: wr_arria10_scu4_atx_pll_altera_xcvr_atx_pll_a10_181_n7tbbgq"
Info: xcvr_atx_pll_a10_0: add_fileset_file ./twentynm_xcvr_avmm.sv SYSTEM_VERILOG PATH ../../../alt_xcvr_core/nf/twentynm_xcvr_avmm.sv
Info: xcvr_atx_pll_a10_0: add_fileset_file ./alt_xcvr_resync.sv SYSTEM_VERILOG PATH ../../../../altera_xcvr_generic/ctrl/alt_xcvr_resync.sv
Info: xcvr_atx_pll_a10_0: add_fileset_file ./alt_xcvr_arbiter.sv SYSTEM_VERILOG PATH ../../../../altera_xcvr_generic/ctrl/alt_xcvr_arbiter.sv
Info: xcvr_atx_pll_a10_0: add_fileset_file ./a10_avmm_h.sv SYSTEM_VERILOG PATH ../../../altera_xcvr_native_phy/altera_xcvr_native_vi/a10_avmm_h.sv
Info: xcvr_atx_pll_a10_0: add_fileset_file ./altera_xcvr_native_a10_functions_h.sv SYSTEM_VERILOG PATH ../../../altera_xcvr_native_phy/altera_xcvr_native_vi/altera_xcvr_native_a10_functions_h.sv
Info: xcvr_atx_pll_a10_0: add_fileset_file ./alt_xcvr_atx_pll_rcfg_arb.sv SYSTEM_VERILOG PATH ../source/alt_xcvr_atx_pll_rcfg_arb.sv
Info: xcvr_atx_pll_a10_0: add_fileset_file ./a10_xcvr_atx_pll.sv SYSTEM_VERILOG PATH ../source/a10_xcvr_atx_pll.sv
Info: xcvr_atx_pll_a10_0: add_fileset_file ./alt_xcvr_pll_embedded_debug.sv SYSTEM_VERILOG PATH ../source/alt_xcvr_pll_embedded_debug.sv
Info: xcvr_atx_pll_a10_0: add_fileset_file ./alt_xcvr_pll_avmm_csr.sv SYSTEM_VERILOG PATH ../source/alt_xcvr_pll_avmm_csr.sv
Info: wr_arria10_scu4_atx_pll: Done "wr_arria10_scu4_atx_pll" with 2 modules, 14 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis
platform/altera/wr_arria10_scu4_phy/wr_arria10_scu4_atx_pll/wr_arria10_scu4_atx_pll/wr_arria10_scu4_atx_pll_generation_previous.rpt deleted 100644 → 0
View file @ 091556ba
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate /home/alex/workspace/projects/r13/bel_projects/ip_cores/wr-cores/platform/altera/wr_arria10_scu4_phy/wr_arria10_scu4_atx_pll/wr_arria10_scu4_atx_pll.qsys --synthesis=VERILOG --output-directory=/home/alex/workspace/projects/r13/bel_projects/ip_cores/wr-cores/platform/altera/wr_arria10_scu4_phy/wr_arria10_scu4_atx_pll/wr_arria10_scu4_atx_pll --family="Arria 10" --part=10AX027E3F29E2SG
Progress: Loading wr_arria10_scu4_atx_pll/wr_arria10_scu4_atx_pll.qsys
Progress: Reading input file
Progress: Adding xcvr_atx_pll_a10_0 [altera_xcvr_atx_pll_a10 18.1]
Progress: Parameterizing module xcvr_atx_pll_a10_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: wr_arria10_scu4_atx_pll.xcvr_atx_pll_a10_0: For the selected device(10AX027E3F29E2SG), PLL speed grade is 3.
Info: wr_arria10_scu4_atx_pll: "Transforming system: wr_arria10_scu4_atx_pll"
Info: wr_arria10_scu4_atx_pll: Running transform generation_view_transform
Info: wr_arria10_scu4_atx_pll: Running transform generation_view_transform took 0.000s
Info: xcvr_atx_pll_a10_0: Running transform generation_view_transform
Info: xcvr_atx_pll_a10_0: Running transform generation_view_transform took 0.000s
Info: wr_arria10_scu4_atx_pll: Running transform merlin_avalon_transform
Info: wr_arria10_scu4_atx_pll: Running transform merlin_avalon_transform took 0.068s
Info: wr_arria10_scu4_atx_pll: "Naming system components in system: wr_arria10_scu4_atx_pll"
Info: wr_arria10_scu4_atx_pll: "Processing generation queue"
Info: wr_arria10_scu4_atx_pll: "Generating: wr_arria10_scu4_atx_pll"
Info: wr_arria10_scu4_atx_pll: "Generating: wr_arria10_scu4_atx_pll_altera_xcvr_atx_pll_a10_181_n7tbbgq"
Info: xcvr_atx_pll_a10_0: add_fileset_file ./twentynm_xcvr_avmm.sv SYSTEM_VERILOG PATH ../../../alt_xcvr_core/nf/twentynm_xcvr_avmm.sv
Info: xcvr_atx_pll_a10_0: add_fileset_file ./alt_xcvr_resync.sv SYSTEM_VERILOG PATH ../../../../altera_xcvr_generic/ctrl/alt_xcvr_resync.sv
Info: xcvr_atx_pll_a10_0: add_fileset_file ./alt_xcvr_arbiter.sv SYSTEM_VERILOG PATH ../../../../altera_xcvr_generic/ctrl/alt_xcvr_arbiter.sv
Info: xcvr_atx_pll_a10_0: add_fileset_file ./a10_avmm_h.sv SYSTEM_VERILOG PATH ../../../altera_xcvr_native_phy/altera_xcvr_native_vi/a10_avmm_h.sv
Info: xcvr_atx_pll_a10_0: add_fileset_file ./altera_xcvr_native_a10_functions_h.sv SYSTEM_VERILOG PATH ../../../altera_xcvr_native_phy/altera_xcvr_native_vi/altera_xcvr_native_a10_functions_h.sv
Info: xcvr_atx_pll_a10_0: add_fileset_file ./alt_xcvr_atx_pll_rcfg_arb.sv SYSTEM_VERILOG PATH ../source/alt_xcvr_atx_pll_rcfg_arb.sv
Info: xcvr_atx_pll_a10_0: add_fileset_file ./a10_xcvr_atx_pll.sv SYSTEM_VERILOG PATH ../source/a10_xcvr_atx_pll.sv
Info: xcvr_atx_pll_a10_0: add_fileset_file ./alt_xcvr_pll_embedded_debug.sv SYSTEM_VERILOG PATH ../source/alt_xcvr_pll_embedded_debug.sv
Info: xcvr_atx_pll_a10_0: add_fileset_file ./alt_xcvr_pll_avmm_csr.sv SYSTEM_VERILOG PATH ../source/alt_xcvr_pll_avmm_csr.sv
Info: wr_arria10_scu4_atx_pll: Done "wr_arria10_scu4_atx_pll" with 2 modules, 14 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis
platform/altera/wr_arria10_scu4_phy/wr_arria10_scu4_phy/wr_arria10_scu4_phy/synth/wr_arria10_scu4_phy.qicache deleted 100644 → 0
View file @ 091556ba
<?xml version='1.0' encoding='us-ascii'?>
<qsys_generation_info>
<qsys_file path="/home/alex/workspace/projects/r13/bel_projects/ip_cores/wr-cores/platform/altera/wr_arria10_scu4_phy/wr_arria10_scu4_phy/wr_arria10_scu4_phy.qsys" />
<gen_dir path="/home/alex/workspace/projects/r13/bel_projects/ip_cores/wr-cores/platform/altera/wr_arria10_scu4_phy/wr_arria10_scu4_phy/wr_arria10_scu4_phy/" />
<user_regen_policy value="Never Regenerate Existing IP" />
<actual_regen_policy value="Never Regenerate Existing IP" />
<gen_action value="IP Generation Skipped" />
<gen_status value="IP Generation Succeeded" />
</qsys_generation_info>
\ No newline at end of file
platform/altera/wr_arria10_scu4_phy/wr_arria10_scu4_phy/wr_arria10_scu4_phy/wr_arria10_scu4_phy_generation.rpt deleted 100644 → 0
View file @ 091556ba
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate /home/alex/workspace/projects/r13/bel_projects/ip_cores/wr-cores/platform/altera/wr_arria10_scu4_phy/wr_arria10_scu4_phy/wr_arria10_scu4_phy.qsys --synthesis=VERILOG --output-directory=/home/alex/workspace/projects/r13/bel_projects/ip_cores/wr-cores/platform/altera/wr_arria10_scu4_phy/wr_arria10_scu4_phy/wr_arria10_scu4_phy --family="Arria 10" --part=10AX027E3F29E2SG
Progress: Loading wr_arria10_scu4_phy/wr_arria10_scu4_phy.qsys
Progress: Reading input file
Progress: Adding xcvr_native_a10_0 [altera_xcvr_native_a10 18.1]
Progress: Parameterizing module xcvr_native_a10_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: wr_arria10_scu4_phy.xcvr_native_a10_0: Simplified data interface has been enabled. The Native PHY will present the data/control interface for the current configuration only. Dynamic reconfiguration of the data interface cannot be supported. The unused_tx_parallel_data and unused_tx_control ports should be connected to 0.
Info: wr_arria10_scu4_phy.xcvr_native_a10_0: The "rx_std_bitslip" port must be enabled if Standard PCS RX bitslip capability is desired.
Info: wr_arria10_scu4_phy.xcvr_native_a10_0: For the selected device(10AX027E3F29E2SG), transceiver speed grade is 3 and core speed grade is 2.
Warning: wr_arria10_scu4_phy.xcvr_native_a10_0: Note - For Arria10 GX/SX devices, 1_1V is not a valid option for supply voltage (VCCR_GXB and VCCT_GXB supply voltage for the Transceiver)
Info: wr_arria10_scu4_phy.xcvr_native_a10_0: Note - The external TX PLL IP must be configured with an output clock frequency of 625.0 MHz.
Info: wr_arria10_scu4_phy: "Transforming system: wr_arria10_scu4_phy"
Info: wr_arria10_scu4_phy: Running transform generation_view_transform
Info: wr_arria10_scu4_phy: Running transform generation_view_transform took 0.000s
Info: xcvr_native_a10_0: Running transform generation_view_transform
Info: xcvr_native_a10_0: Running transform generation_view_transform took 0.000s
Info: wr_arria10_scu4_phy: Running transform merlin_avalon_transform
Info: wr_arria10_scu4_phy: Running transform merlin_avalon_transform took 0.069s
Info: wr_arria10_scu4_phy: "Naming system components in system: wr_arria10_scu4_phy"
Info: wr_arria10_scu4_phy: "Processing generation queue"
Info: wr_arria10_scu4_phy: "Generating: wr_arria10_scu4_phy"
Info: wr_arria10_scu4_phy: "Generating: wr_arria10_scu4_phy_altera_xcvr_native_a10_181_wire5gy"
Info: xcvr_native_a10_0: add_fileset_file ./alt_xcvr_resync.sv SYSTEM_VERILOG PATH ../../../../altera_xcvr_generic/ctrl/alt_xcvr_resync.sv
Info: xcvr_native_a10_0: add_fileset_file ./alt_xcvr_arbiter.sv SYSTEM_VERILOG PATH ../../../../altera_xcvr_generic/ctrl/alt_xcvr_arbiter.sv
Info: xcvr_native_a10_0: add_fileset_file ./twentynm_pcs.sv SYSTEM_VERILOG PATH ../../../alt_xcvr_core/nf/twentynm_pcs.sv
Info: xcvr_native_a10_0: add_fileset_file ./twentynm_pma.sv SYSTEM_VERILOG PATH ../../../alt_xcvr_core/nf/twentynm_pma.sv
Info: xcvr_native_a10_0: add_fileset_file ./twentynm_xcvr_avmm.sv SYSTEM_VERILOG PATH ../../../alt_xcvr_core/nf/twentynm_xcvr_avmm.sv
Info: xcvr_native_a10_0: add_fileset_file ./twentynm_xcvr_native.sv SYSTEM_VERILOG PATH ../../../alt_xcvr_core/nf/twentynm_xcvr_native.sv
Info: xcvr_native_a10_0: add_fileset_file ./altera_xcvr_native_a10_functions_h.sv SYSTEM_VERILOG PATH ..//altera_xcvr_native_a10_functions_h.sv
Info: xcvr_native_a10_0: add_fileset_file ./a10_avmm_h.sv SYSTEM_VERILOG PATH ..//a10_avmm_h.sv
Info: xcvr_native_a10_0: add_fileset_file ./alt_xcvr_native_pipe_retry.sv SYSTEM_VERILOG PATH ..//alt_xcvr_native_pipe_retry.sv
Info: xcvr_native_a10_0: add_fileset_file ./alt_xcvr_native_avmm_csr.sv SYSTEM_VERILOG PATH ..//alt_xcvr_native_avmm_csr.sv
Info: xcvr_native_a10_0: add_fileset_file ./alt_xcvr_native_prbs_accum.sv SYSTEM_VERILOG PATH ..//alt_xcvr_native_prbs_accum.sv
Info: xcvr_native_a10_0: add_fileset_file ./alt_xcvr_native_odi_accel.sv SYSTEM_VERILOG PATH ..//alt_xcvr_native_odi_accel.sv
Info: xcvr_native_a10_0: add_fileset_file ./alt_xcvr_native_rcfg_arb.sv SYSTEM_VERILOG PATH ..//alt_xcvr_native_rcfg_arb.sv
Info: xcvr_native_a10_0: add_fileset_file ./altera_xcvr_native_a10_false_paths.sdc SDC PATH ..//altera_xcvr_native_a10_false_paths.sdc
Info: xcvr_native_a10_0: add_fileset_file ./altera_xcvr_native_pcie_dfe_params_h.sv SYSTEM_VERILOG PATH ../pcie_dfe_ip/altera_xcvr_native_pcie_dfe_params_h.sv
Info: xcvr_native_a10_0: add_fileset_file ./pcie_mgmt_commands_h.sv SYSTEM_VERILOG PATH ../pcie_dfe_ip/pcie_mgmt_commands_h.sv
Info: xcvr_native_a10_0: add_fileset_file ./pcie_mgmt_functions_h.sv SYSTEM_VERILOG PATH ../pcie_dfe_ip/pcie_mgmt_functions_h.sv
Info: xcvr_native_a10_0: add_fileset_file ./pcie_mgmt_program.sv SYSTEM_VERILOG PATH ../pcie_dfe_ip/pcie_mgmt_program.sv
Info: xcvr_native_a10_0: add_fileset_file ./pcie_mgmt_cpu.sv SYSTEM_VERILOG PATH ../pcie_dfe_ip/pcie_mgmt_cpu.sv
Info: xcvr_native_a10_0: add_fileset_file ./pcie_mgmt_master.sv SYSTEM_VERILOG PATH ../pcie_dfe_ip/pcie_mgmt_master.sv
Info: xcvr_native_a10_0: add_fileset_file ./altera_xcvr_native_pcie_dfe_ip.sv SYSTEM_VERILOG PATH ../pcie_dfe_ip/altera_xcvr_native_pcie_dfe_ip.sv
Info: wr_arria10_scu4_phy: Done "wr_arria10_scu4_phy" with 2 modules, 26 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis
platform/altera/wr_arria10_scu4_phy/wr_arria10_scu4_rst_ctl/wr_arria10_scu4_rst_ctl/synth/wr_arria10_scu4_rst_ctl.qicache deleted 100644 → 0
View file @ 091556ba
<?xml version='1.0' encoding='us-ascii'?>
<qsys_generation_info>
<qsys_file path="/home/alex/workspace/projects/r13/bel_projects/ip_cores/wr-cores/platform/altera/wr_arria10_scu4_phy/wr_arria10_scu4_rst_ctl/wr_arria10_scu4_rst_ctl.qsys" />
<gen_dir path="/home/alex/workspace/projects/r13/bel_projects/ip_cores/wr-cores/platform/altera/wr_arria10_scu4_phy/wr_arria10_scu4_rst_ctl/wr_arria10_scu4_rst_ctl/" />
<user_regen_policy value="Never Regenerate Existing IP" />
<actual_regen_policy value="Never Regenerate Existing IP" />
<gen_action value="IP Generation Skipped" />
<gen_status value="IP Generation Succeeded" />
</qsys_generation_info>
\ No newline at end of file
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