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White Rabbit core collection
Commit 752afb7f authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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wr_endpoint: re-genrated WB slaves using new wbgen

parent a02c0d0f
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Showing with 14 additions and 4 deletions
modules/wr_endpoint/build_wb.sh
View file @ 752afb7f
#!/bin/bash
mkdir -p doc
~/wbgen2/wishbone-gen/wbgen2 -D ./doc/wrsw_endpoint.html -p ep_registers_pkg.vhd -H record -V ep_wishbone_controller.vhd --cstyle defines --lang vhdl -K ../../sim/endpoint_regs.v ep_wishbone_controller.wb
~/wbgen2/wishbone-gen/wbgen2 -D ./doc/wrsw_endpoint.html -C endpoint_regs.h -p ep_registers_pkg.vhd -H record -V ep_wishbone_controller.vhd --cstyle struct --lang vhdl -K ../../sim/endpoint_regs.v ep_wishbone_controller.wb
wbgen2 -D ./doc/wrsw_endpoint_mdio.html -V ep_pcs_tbi_mdio_wb.vhd --cstyle defines --lang vhdl -K ../../sim/endpoint_mdio.v pcs_regs.wb
\ No newline at end of file
modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd
View file @ 752afb7f
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ep_pcs_tbi_mdio_wb.vhd
-- Author : auto-generated by wbgen2 from pcs_regs.wb
-- Created : Tue Oct 18 16:46:39 2011
-- Created : Wed Oct 26 22:05:09 2011
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pcs_regs.wb
......@@ -175,6 +175,7 @@ begin
rddata_reg(5) <= 'X';
mdio_mcr_uni_en_int <= wrdata_reg(5);
mdio_mcr_anrestart_int <= wrdata_reg(9);
rddata_reg(9) <= 'X';
rddata_reg(11) <= 'X';
mdio_mcr_pdown_int <= wrdata_reg(11);
rddata_reg(12) <= 'X';
......@@ -182,17 +183,20 @@ begin
rddata_reg(14) <= 'X';
mdio_mcr_loopback_int <= wrdata_reg(14);
mdio_mcr_reset_int <= wrdata_reg(15);
rddata_reg(15) <= 'X';
else
rddata_reg(4 downto 0) <= "00000";
rddata_reg(5) <= mdio_mcr_uni_en_int;
rddata_reg(6) <= '1';
rddata_reg(7) <= '0';
rddata_reg(8) <= '1';
rddata_reg(9) <= 'X';
rddata_reg(10) <= '0';
rddata_reg(11) <= mdio_mcr_pdown_int;
rddata_reg(12) <= mdio_mcr_anenable_int;
rddata_reg(13) <= '0';
rddata_reg(14) <= mdio_mcr_loopback_int;
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
......@@ -426,11 +430,13 @@ begin
mdio_wr_spec_tx_cal_int <= wrdata_reg(0);
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
mdio_wr_spec_cal_crst_int <= wrdata_reg(2);
mdio_wr_spec_cal_crst_int_delay <= wrdata_reg(2);
else
rddata_reg(0) <= mdio_wr_spec_tx_cal_int;
rddata_reg(1) <= mdio_wr_spec_rx_cal_stat_sync1;
rddata_reg(2) <= 'X';
mdio_wr_spec_bslide_lwb <= '1';
mdio_wr_spec_bslide_lwb_delay <= '1';
mdio_wr_spec_bslide_lwb_in_progress <= '1';
......
modules/wr_endpoint/ep_registers_pkg.vhd
View file @ 752afb7f
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ep_registers_pkg.vhd
-- Author : auto-generated by wbgen2 from ep_wishbone_controller.wb
-- Created : Tue Oct 18 16:46:38 2011
-- Created : Wed Oct 26 22:05:09 2011
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ep_wishbone_controller.wb
......
modules/wr_endpoint/ep_wishbone_controller.vhd
View file @ 752afb7f
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ep_wishbone_controller.vhd
-- Author : auto-generated by wbgen2 from ep_wishbone_controller.wb
-- Created : Tue Oct 18 16:46:38 2011
-- Created : Wed Oct 26 22:05:09 2011
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ep_wishbone_controller.wb
......@@ -188,6 +188,7 @@ begin
if (wb_we_i = '1') then
ep_ecr_portid_int <= wrdata_reg(4 downto 0);
ep_ecr_rst_cnt_int <= wrdata_reg(5);
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
ep_ecr_tx_en_int <= wrdata_reg(6);
rddata_reg(7) <= 'X';
......@@ -198,6 +199,7 @@ begin
rddata_reg(27) <= 'X';
else
rddata_reg(4 downto 0) <= ep_ecr_portid_int;
rddata_reg(5) <= 'X';
rddata_reg(6) <= ep_ecr_tx_en_int;
rddata_reg(7) <= ep_ecr_rx_en_int;
rddata_reg(24) <= regs_i.ecr_feat_vlan_i;
......@@ -233,12 +235,14 @@ begin
ep_tscr_en_txts_int <= wrdata_reg(0);
rddata_reg(1) <= 'X';
ep_tscr_en_rxts_int <= wrdata_reg(1);
rddata_reg(2) <= 'X';
ep_tscr_cs_start_int <= wrdata_reg(2);
ep_tscr_cs_start_int_delay <= wrdata_reg(2);
rddata_reg(3) <= 'X';
else
rddata_reg(0) <= ep_tscr_en_txts_int;
rddata_reg(1) <= ep_tscr_en_rxts_int;
rddata_reg(2) <= 'X';
rddata_reg(3) <= ep_tscr_cs_done_sync1;
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
......
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