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White Rabbit core collection
Commit 78880297 authored by Peter Jansweijer's avatar Peter Jansweijer Committed by Grzegorz Daniluk
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platform/gtp: adding PRBS generator inputs

parent 5b9d66fc
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Showing with 22 additions and 6 deletions
platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd
View file @ 78880297
......@@ -99,8 +99,10 @@ entity WHITERABBITGTP_WRAPPER_TILE_SPARTAN6 is
TXN0_OUT : out std_logic;
TXN1_OUT : out std_logic;
TXP0_OUT : out std_logic;
TXP1_OUT : out std_logic
TXP1_OUT : out std_logic;
--------------- Transmit Ports - PRBS Generator ----------------------------
TXENPRBSTST0_IN : in std_logic_vector(2 downto 0);
TXENPRBSTST1_IN : in std_logic_vector(2 downto 0)
);
......@@ -683,8 +685,8 @@ begin
TXPREEMPHASIS0 => "000",
TXPREEMPHASIS1 => "000",
--------------------- Transmit Ports - TX PRBS Generator -------------------
TXENPRBSTST0 => tied_to_ground_vec_i(2 downto 0),
TXENPRBSTST1 => tied_to_ground_vec_i(2 downto 0),
TXENPRBSTST0 => TXENPRBSTST0_IN,
TXENPRBSTST1 => TXENPRBSTST1_IN,
TXPRBSFORCEERR0 => tied_to_ground_i,
TXPRBSFORCEERR1 => tied_to_ground_i,
-------------------- Transmit Ports - TX Polarity Control ------------------
......
platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd
View file @ 78880297
......@@ -111,6 +111,9 @@ entity wr_gtp_phy_spartan6 is
ch0_loopen_i : in std_logic;
ch0_loopen_vec_i : in std_logic_vector(2 downto 0) := (others=>'0');
-- PRBS select (see Xilinx UG386 Table 3-15; "000" = Standard operation, pattern generator off)
ch0_tx_prbs_sel_i : in std_logic_vector(2 downto 0) := (others=>'0');
-- gtp0 ready: locked & aligned
ch0_rdy_o : out std_logic;
......@@ -131,6 +134,7 @@ entity wr_gtp_phy_spartan6 is
ch1_rst_i : in std_logic := '0';
ch1_loopen_i : in std_logic := '0';
ch1_loopen_vec_i : in std_logic_vector(2 downto 0) := (others=>'0');
ch1_tx_prbs_sel_i: in std_logic_vector(2 downto 0) := (others=>'0');
ch1_rdy_o : out std_logic;
-- Serial I/O
......@@ -228,7 +232,9 @@ architecture rtl of wr_gtp_phy_spartan6 is
TXN0_OUT : out std_logic;
TXN1_OUT : out std_logic;
TXP0_OUT : out std_logic;
TXP1_OUT : out std_logic);
TXP1_OUT : out std_logic;
TXENPRBSTST0_IN : in std_logic_vector(2 downto 0);
TXENPRBSTST1_IN : in std_logic_vector(2 downto 0));
end component;
component BUFG
......@@ -799,7 +805,10 @@ begin -- rtl
TXN0_OUT => pad_txn0_o,
TXN1_OUT => pad_txn1_o,
TXP0_OUT => pad_txp0_o,
TXP1_OUT => pad_txp1_o
TXP1_OUT => pad_txp1_o,
--------------- Transmit Ports - TX PRBS Generator -------------------------
TXENPRBSTST0_IN => ch0_tx_prbs_sel_i,
TXENPRBSTST1_IN => ch1_tx_prbs_sel_i
);
......
platform/xilinx/wr_xilinx_pkg.vhd
View file @ 78880297
......@@ -29,6 +29,7 @@ package wr_xilinx_pkg is
ch0_rst_i : in std_logic := '0';
ch0_loopen_i : in std_logic := '0';
ch0_loopen_vec_i : in std_logic_vector(2 downto 0) := (others=>'0');
ch0_tx_prbs_sel_i : in std_logic_vector(2 downto 0) := (others=>'0');
ch0_rdy_o : out std_logic;
ch1_ref_clk_i : in std_logic;
ch1_tx_data_i : in std_logic_vector(7 downto 0) := "00000000";
......@@ -43,6 +44,7 @@ package wr_xilinx_pkg is
ch1_rst_i : in std_logic := '0';
ch1_loopen_i : in std_logic := '0';
ch1_loopen_vec_i : in std_logic_vector(2 downto 0) := (others=>'0');
ch1_tx_prbs_sel_i : in std_logic_vector(2 downto 0) := (others=>'0');
ch1_rdy_o : out std_logic;
pad_txn0_o : out std_logic;
pad_txp0_o : out std_logic;
......
top/spec_1_1/wr_core_demo/spec_top.vhd
View file @ 78880297
......@@ -361,6 +361,7 @@ architecture rtl of spec_top is
signal phy_rst : std_logic;
signal phy_loopen : std_logic;
signal phy_loopen_vec : std_logic_vector(2 downto 0);
signal phy_prbs_sel : std_logic_vector(2 downto 0);
signal phy_rdy : std_logic;
signal dio_in : std_logic_vector(4 downto 0);
......@@ -703,6 +704,7 @@ begin
phy_sfp_tx_fault_i => sfp_tx_fault_i,
phy_sfp_los_i => sfp_los_i,
phy_sfp_tx_disable_o => sfp_tx_disable_o,
phy_tx_prbs_sel_o => phy_prbs_sel,
led_act_o => LED_RED,
led_link_o => LED_GREEN,
......@@ -823,6 +825,7 @@ begin
ch1_rst_i => phy_rst,
ch1_loopen_i => phy_loopen,
ch1_loopen_vec_i => phy_loopen_vec,
ch1_tx_prbs_sel_i => phy_prbs_sel,
ch1_rdy_o => phy_rdy,
pad_txn0_o => open,
pad_txp0_o => open,
......
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