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White Rabbit core collection
Commit 79013c4e authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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pps_gen: increased address bus width for byte granularity

parent 422fe764
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Showing with 5 additions and 5 deletions
modules/wrsw_pps_gen/wrsw_pps_gen.vhd
View file @ 79013c4e
......@@ -40,7 +40,7 @@ entity wrsw_pps_gen is
rst_n_i : in std_logic;
wb_addr_i : in std_logic_vector(3 downto 0);
wb_addr_i : in std_logic_vector(4 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
......@@ -160,8 +160,8 @@ architecture behavioral of wrsw_pps_gen is
begin -- behavioral
resized_addr(3 downto 0) <= wb_addr_i;
resized_addr(c_wishbone_address_width-1 downto 4) <= (others => '0');
resized_addr(4 downto 0) <= wb_addr_i;
resized_addr(c_wishbone_address_width-1 downto 5) <= (others => '0');
U_Adapter : wb_slave_adapter
generic map (
......
modules/wrsw_pps_gen/xwb_pps_gen.vhd
View file @ 79013c4e
......@@ -68,7 +68,7 @@ architecture behavioral of xwb_pps_gen is
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_addr_i : in std_logic_vector(3 downto 0);
wb_addr_i : in std_logic_vector(4 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
......@@ -98,7 +98,7 @@ begin -- behavioral
clk_ref_i => clk_ref_i,
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
wb_addr_i => slave_i.adr(3 downto 0),
wb_addr_i => slave_i.adr(4 downto 0),
wb_data_i => slave_i.dat,
wb_data_o => slave_o.dat,
wb_cyc_i => slave_i.cyc,
......
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