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White Rabbit core collection
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7ac9c72f
Commit
7ac9c72f
authored
Apr 08, 2020
by
Grzegorz Daniluk
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Merge branch 'BTrain-v1.2' into proposed_master
parents
8299d657
4e70a456
Pipeline
#185
failed with stages
in 6 seconds
Changes
7
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1
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7 changed files
with
84 additions
and
11 deletions
+84
-11
xwrc_board_cute.vhd
board/cute/xwrc_board_cute.vhd
+14
-3
softpll_pkg.vhd
modules/wr_softpll_ng/softpll_pkg.vhd
+24
-1
wr_softpll_ng.vhd
modules/wr_softpll_ng/wr_softpll_ng.vhd
+1
-1
xwr_softpll_ng.vhd
modules/wr_softpll_ng/xwr_softpll_ng.vhd
+2
-2
xrtx_streamers_stats.vhd
modules/wr_streamers/xrtx_streamers_stats.vhd
+41
-2
xrx_streamer.vhd
modules/wr_streamers/xrx_streamer.vhd
+1
-1
wrcore_pkg.vhd
modules/wrc_core/wrcore_pkg.vhd
+1
-1
No files found.
board/cute/xwrc_board_cute.vhd
View file @
7ac9c72f
...
...
@@ -415,6 +415,8 @@ architecture struct of xwrc_board_cute is
signal
multiboot_wb_out
:
t_wishbone_master_out
;
signal
multiboot_wb_in
:
t_wishbone_master_in
;
signal
clk_pll_aux_locked
:
std_logic
;
begin
-- architecture struct
-----------------------------------------------------------------------------
...
...
@@ -759,10 +761,19 @@ end generate;
rst_oserdes
<=
not
pll_aux_locked
;
clk_10m_ext_o
<=
sd_out
(
0
);
cmp_pll_aux_locked
:
gc_sync_ffs
generic
map
(
g_sync_edge
=>
"positive"
)
port
map
(
clk_i
=>
clk_pll_125m
,
rst_n_i
=>
rstlogic_rst_out
(
1
),
data_i
=>
pll_aux_locked
,
synced_o
=>
clk_pll_aux_locked
);
process
(
clk_pll_125m
)
begin
if
rising_edge
(
clk_pll_125m
)
then
if
(
rstlogic_rst_out
(
1
)
=
'0'
or
pll_aux_locked
=
'0'
)
then
if
(
rstlogic_rst_out
(
1
)
=
'0'
or
clk_
pll_aux_locked
=
'0'
)
then
tm_time_valid_d1
<=
'0'
;
elsif
(
pps_csync
=
'1'
)
then
tm_time_valid_d1
<=
tm_time_valid
;
...
...
@@ -776,7 +787,7 @@ end generate;
variable
v_bit
:
std_logic
;
begin
if
rising_edge
(
clk_pll_125m
)
then
if
(
rstlogic_rst_out
(
1
)
=
'0'
or
pll_aux_locked
=
'0'
or
clk_realign
=
'1'
)
then
if
(
rstlogic_rst_out
(
1
)
=
'0'
or
clk_
pll_aux_locked
=
'0'
or
clk_realign
=
'1'
)
then
rest
:
=
to_integer
(
aux_half_high
-
aux_shift
);
v_bit
:
=
'1'
;
else
...
...
modules/wr_softpll_ng/softpll_pkg.vhd
View file @
7ac9c72f
...
...
@@ -24,8 +24,31 @@ package softpll_pkg is
constant
c_softpll_out_status_aligning
:
std_logic_vector
(
3
downto
0
)
:
=
"0011"
;
constant
c_softpll_out_status_holdover
:
std_logic_vector
(
3
downto
0
)
:
=
"0100"
;
function
f_nonzero_vector
(
vector_width
:
integer
)
return
integer
;
end
package
;
package
body
softpll_pkg
is
-- Function f_nonzero_vector() is to be used in generating std_logic_vector
-- in which the number of bits can be specified to be zero, e.g.
-- (see xwr_softpll_ng)
--
-- clk_ext_mul_i : in std_logic_vector(g_num_exts-1 downto 0);
--
-- There might not be any external clocks, i.e. g_num_exts. In such case,
-- the code would not compile because std_logic_vector(-1 to 0) is not valid.
-- This function is used to generate std_logic_vector(0 to 0) in the case
-- when g_num_exts=0.
--
function
f_nonzero_vector
(
vector_width
:
integer
)
return
integer
is
begin
if
(
vector_width
>
0
)
then
return
vector_width
;
else
return
1
;
end
if
;
end
function
;
end
softpll_pkg
;
modules/wr_softpll_ng/wr_softpll_ng.vhd
View file @
7ac9c72f
...
...
@@ -115,7 +115,7 @@ entity wr_softpll_ng is
clk_ext_i
:
in
std_logic
;
-- External clock, multiplied to 125 MHz using the FPGA's PLL
clk_ext_mul_i
:
in
std_logic_vector
(
g_num_exts
-1
downto
0
);
clk_ext_mul_i
:
in
std_logic_vector
(
f_nonzero_vector
(
g_num_exts
)
-1
downto
0
);
clk_ext_mul_locked_i
:
in
std_logic
:
=
'1'
;
clk_ext_stopped_i
:
in
std_logic
:
=
'0'
;
clk_ext_rst_o
:
out
std_logic
;
...
...
modules/wr_softpll_ng/xwr_softpll_ng.vhd
View file @
7ac9c72f
...
...
@@ -105,7 +105,7 @@ entity xwr_softpll_ng is
clk_ext_i
:
in
std_logic
;
-- External clock, multiplied to 125 MHz using the FPGA's PLL
clk_ext_mul_i
:
in
std_logic_vector
(
g_num_exts
-1
downto
0
);
clk_ext_mul_i
:
in
std_logic_vector
(
f_nonzero_vector
(
g_num_exts
)
-1
downto
0
);
clk_ext_mul_locked_i
:
in
std_logic
:
=
'1'
;
clk_ext_stopped_i
:
in
std_logic
:
=
'0'
;
clk_ext_rst_o
:
out
std_logic
;
...
...
@@ -166,7 +166,7 @@ architecture wrapper of xwr_softpll_ng is
clk_fb_i
:
in
std_logic_vector
(
g_num_outputs
-1
downto
0
);
clk_dmtd_i
:
in
std_logic
;
clk_ext_i
:
in
std_logic
;
clk_ext_mul_i
:
in
std_logic_vector
(
g_num_exts
-1
downto
0
);
clk_ext_mul_i
:
in
std_logic_vector
(
f_nonzero_vector
(
g_num_exts
)
-1
downto
0
);
clk_ext_mul_locked_i
:
in
std_logic
;
clk_ext_stopped_i
:
in
std_logic
;
clk_ext_rst_o
:
out
std_logic
;
...
...
modules/wr_streamers/xrtx_streamers_stats.vhd
View file @
7ac9c72f
...
...
@@ -54,6 +54,7 @@ use IEEE.STD_LOGIC_1164.ALL;
use
IEEE
.
NUMERIC_STD
.
ALL
;
library
work
;
use
work
.
gencores_pkg
.
all
;
-- needed for gc_sync_ffs
use
work
.
wishbone_pkg
.
all
;
-- needed for t_wishbone_slave_in, etc
use
work
.
streamers_pkg
.
all
;
-- needed for streamers
use
work
.
wr_fabric_pkg
.
all
;
-- neede for :t_wrf_source_in, etc
...
...
@@ -166,10 +167,48 @@ architecture rtl of xrtx_streamers_stats is
-- for code cleanness
constant
c_cw
:
integer
:
=
g_cnt_width
;
constant
c_aw
:
integer
:
=
g_acc_width
;
-- signals derived from tm_time_valid_i in sys_clk domain
signal
time_valid_sys_clk_d1
:
std_logic
;
-- synched signal
signal
time_valid_sys_clk_p1
:
std_logic
;
-- pulse on rising edge
signal
first_reset_p1
:
std_logic
;
signal
first_reset_pending
:
std_logic
;
begin
-- reset statistics when receiving signal from SNMP or Wishbone
reset_stats
<=
reset_stats_remote
or
reset_stats_i
;
-- synch tm_time_valid_i from ref_clk to sys_clk domain
U_SYNC_TO_SYS_CLK
:
gc_sync_ffs
port
map
(
clk_i
=>
clk_i
,
rst_n_i
=>
rst_n_i
,
data_i
=>
tm_time_valid_i
,
ppulse_o
=>
time_valid_sys_clk_p1
,
synced_o
=>
time_valid_sys_clk_d1
);
-- After system reset, once time_valid is TRUE, resest statistics,
-- This is done to have valid timestamp. Otherwise, the stats need to
-- be always reset after starting device and it is correctly synched
-- (if not done, the reset timestamp=0, so 1970...)
p_first_stats_reset
:
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
(
rst_n_i
=
'0'
)
then
first_reset_pending
<=
'1'
;
first_reset_p1
<=
'0'
;
else
if
(
first_reset_pending
=
'1'
and
time_valid_sys_clk_p1
=
'1'
)
then
first_reset_pending
<=
'0'
;
first_reset_p1
<=
'1'
;
else
first_reset_p1
<=
'0'
;
end
if
;
end
if
;
end
if
;
end
process
;
-- reset statistics
-- 1) after start/restert
-- 2) when receiving signal from SNMP or Wishbone
reset_stats
<=
first_reset_p1
or
reset_stats_remote
or
reset_stats_i
;
-------------------------------------------------------------------------------------------
-- produce pulse of reset input signal, this pulse produces timesstamp to be timestamped
-------------------------------------------------------------------------------------------
...
...
modules/wr_streamers/xrx_streamer.vhd
View file @
7ac9c72f
...
...
@@ -370,7 +370,7 @@ begin -- rtl
U_RestoreTAITimeFromRXTimestamp
:
entity
work
.
ts_restore_tai
generic
map
(
g_tm_sample_period
=>
2
0
,
g_tm_sample_period
=>
3
0
,
g_clk_ref_rate
=>
g_clk_ref_rate
,
g_simulation
=>
g_simulation
,
g_sim_cycle_counter_range
=>
g_sim_cycle_counter_range
)
...
...
modules/wrc_core/wrcore_pkg.vhd
View file @
7ac9c72f
...
...
@@ -332,7 +332,7 @@ package wrcore_pkg is
clk_fb_i
:
in
std_logic_vector
(
g_num_outputs
-1
downto
0
);
clk_dmtd_i
:
in
std_logic
;
clk_ext_i
:
in
std_logic
;
clk_ext_mul_i
:
in
std_logic_vector
(
g_num_exts
-1
downto
0
);
clk_ext_mul_i
:
in
std_logic_vector
(
f_nonzero_vector
(
g_num_exts
)
-1
downto
0
);
clk_ext_mul_locked_i
:
in
std_logic
;
clk_ext_stopped_i
:
in
std_logic
;
clk_ext_rst_o
:
out
std_logic
;
...
...
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