Commit 7c7701e3 authored by Dimitris Lampridis's avatar Dimitris Lampridis

hdl: further cleanup of WB INT

parent d4b42139
......@@ -7,7 +7,7 @@
-- Author(s) : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-02-17
-- Last update: 2017-07-04
-- Last update: 2018-03-20
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Copyright (c) 2017 CERN
......@@ -217,7 +217,6 @@ package wr_spec_pkg is
wb_cyc_i : in std_logic := '0';
wb_stb_i : in std_logic := '0';
wb_ack_o : out std_logic;
wb_int_o : out std_logic;
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
......@@ -229,7 +228,6 @@ package wr_spec_pkg is
aux_master_cyc_o : out std_logic;
aux_master_stb_o : out std_logic;
aux_master_ack_i : in std_logic := '0';
aux_master_int_i : in std_logic := '0';
aux_master_err_i : in std_logic := '0';
aux_master_rty_i : in std_logic := '0';
aux_master_stall_i : in std_logic := '0';
......@@ -280,7 +278,6 @@ package wr_spec_pkg is
wb_eth_cyc_o : out std_logic;
wb_eth_stb_o : out std_logic;
wb_eth_ack_i : in std_logic := '0';
wb_eth_int_i : in std_logic := '0';
wb_eth_err_i : in std_logic := '0';
wb_eth_rty_i : in std_logic := '0';
wb_eth_stall_i : in std_logic := '0';
......
......@@ -7,7 +7,7 @@
-- Author(s) : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-02-17
-- Last update: 2017-07-04
-- Last update: 2018-03-20
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
......@@ -169,7 +169,6 @@ entity wrc_board_spec is
wb_cyc_i : in std_logic := '0';
wb_stb_i : in std_logic := '0';
wb_ack_o : out std_logic;
wb_int_o : out std_logic;
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
......@@ -182,7 +181,6 @@ entity wrc_board_spec is
aux_master_cyc_o : out std_logic;
aux_master_stb_o : out std_logic;
aux_master_ack_i : in std_logic := '0';
aux_master_int_i : in std_logic := '0';
aux_master_err_i : in std_logic := '0';
aux_master_rty_i : in std_logic := '0';
aux_master_stall_i : in std_logic := '0';
......@@ -244,7 +242,6 @@ entity wrc_board_spec is
wb_eth_cyc_o : out std_logic;
wb_eth_stb_o : out std_logic;
wb_eth_ack_i : in std_logic := '0';
wb_eth_int_i : in std_logic := '0';
wb_eth_err_i : in std_logic := '0';
wb_eth_rty_i : in std_logic := '0';
wb_eth_stall_i : in std_logic := '0';
......@@ -362,7 +359,6 @@ begin -- architecture struct
wb_err_o <= wb_slave_out.err;
wb_rty_o <= wb_slave_out.rty;
wb_stall_o <= wb_slave_out.stall;
wb_int_o <= wb_slave_out.int;
wb_dat_o <= wb_slave_out.dat;
aux_master_adr_o <= aux_master_out.adr;
......@@ -374,7 +370,6 @@ begin -- architecture struct
aux_master_in.dat <= aux_master_dat_i;
aux_master_in.ack <= aux_master_ack_i;
aux_master_in.int <= aux_master_int_i;
aux_master_in.err <= aux_master_err_i;
aux_master_in.rty <= aux_master_rty_i;
aux_master_in.stall <= aux_master_stall_i;
......@@ -411,7 +406,6 @@ begin -- architecture struct
wb_eth_master_in.dat <= wb_eth_dat_i;
wb_eth_master_in.ack <= wb_eth_ack_i;
wb_eth_master_in.int <= wb_eth_int_i;
wb_eth_master_in.err <= wb_eth_err_i;
wb_eth_master_in.rty <= wb_eth_rty_i;
wb_eth_master_in.stall <= wb_eth_stall_i;
......
......@@ -7,7 +7,7 @@
-- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-02-16
-- Last update: 2017-07-04
-- Last update: 2018-03-20
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Copyright (c) 2017 CERN
......@@ -218,7 +218,6 @@ package wr_svec_pkg is
wb_cyc_i : in std_logic := '0';
wb_stb_i : in std_logic := '0';
wb_ack_o : out std_logic;
wb_int_o : out std_logic;
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
......@@ -230,7 +229,6 @@ package wr_svec_pkg is
aux_master_cyc_o : out std_logic;
aux_master_stb_o : out std_logic;
aux_master_ack_i : in std_logic := '0';
aux_master_int_i : in std_logic := '0';
aux_master_err_i : in std_logic := '0';
aux_master_rty_i : in std_logic := '0';
aux_master_stall_i : in std_logic := '0';
......@@ -281,7 +279,6 @@ package wr_svec_pkg is
wb_eth_cyc_o : out std_logic;
wb_eth_stb_o : out std_logic;
wb_eth_ack_i : in std_logic := '0';
wb_eth_int_i : in std_logic := '0';
wb_eth_err_i : in std_logic := '0';
wb_eth_rty_i : in std_logic := '0';
wb_eth_stall_i : in std_logic := '0';
......
......@@ -7,7 +7,7 @@
-- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-02-16
-- Last update: 2017-07-04
-- Last update: 2018-03-20
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
......@@ -171,7 +171,6 @@ entity wrc_board_svec is
wb_cyc_i : in std_logic := '0';
wb_stb_i : in std_logic := '0';
wb_ack_o : out std_logic;
wb_int_o : out std_logic;
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
......@@ -184,7 +183,6 @@ entity wrc_board_svec is
aux_master_cyc_o : out std_logic;
aux_master_stb_o : out std_logic;
aux_master_ack_i : in std_logic := '0';
aux_master_int_i : in std_logic := '0';
aux_master_err_i : in std_logic := '0';
aux_master_rty_i : in std_logic := '0';
aux_master_stall_i : in std_logic := '0';
......@@ -246,7 +244,6 @@ entity wrc_board_svec is
wb_eth_cyc_o : out std_logic;
wb_eth_stb_o : out std_logic;
wb_eth_ack_i : in std_logic := '0';
wb_eth_int_i : in std_logic := '0';
wb_eth_err_i : in std_logic := '0';
wb_eth_rty_i : in std_logic := '0';
wb_eth_stall_i : in std_logic := '0';
......@@ -358,7 +355,6 @@ begin -- architecture struct
wb_err_o <= wb_slave_out.err;
wb_rty_o <= wb_slave_out.rty;
wb_stall_o <= wb_slave_out.stall;
wb_int_o <= wb_slave_out.int;
wb_dat_o <= wb_slave_out.dat;
aux_master_adr_o <= aux_master_out.adr;
......@@ -370,7 +366,6 @@ begin -- architecture struct
aux_master_in.dat <= aux_master_dat_i;
aux_master_in.ack <= aux_master_ack_i;
aux_master_in.int <= aux_master_int_i;
aux_master_in.err <= aux_master_err_i;
aux_master_in.rty <= aux_master_rty_i;
aux_master_in.stall <= aux_master_stall_i;
......@@ -407,7 +402,6 @@ begin -- architecture struct
wb_eth_master_in.dat <= wb_eth_dat_i;
wb_eth_master_in.ack <= wb_eth_ack_i;
wb_eth_master_in.int <= wb_eth_int_i;
wb_eth_master_in.err <= wb_eth_err_i;
wb_eth_master_in.rty <= wb_eth_rty_i;
wb_eth_master_in.stall <= wb_eth_stall_i;
......
......@@ -7,7 +7,7 @@
-- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2016-07-26
-- Last update: 2017-07-04
-- Last update: 2018-03-20
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Copyright (c) 2016-2017 CERN
......@@ -186,7 +186,6 @@ package wr_vfchd_pkg is
wb_cyc_i : in std_logic := '0';
wb_stb_i : in std_logic := '0';
wb_ack_o : out std_logic;
wb_int_o : out std_logic;
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
......@@ -198,7 +197,6 @@ package wr_vfchd_pkg is
aux_master_cyc_o : out std_logic;
aux_master_stb_o : out std_logic;
aux_master_ack_i : in std_logic := '0';
aux_master_int_i : in std_logic := '0';
aux_master_err_i : in std_logic := '0';
aux_master_rty_i : in std_logic := '0';
aux_master_stall_i : in std_logic := '0';
......@@ -249,7 +247,6 @@ package wr_vfchd_pkg is
wb_eth_cyc_o : out std_logic;
wb_eth_stb_o : out std_logic;
wb_eth_ack_i : in std_logic := '0';
wb_eth_int_i : in std_logic := '0';
wb_eth_err_i : in std_logic := '0';
wb_eth_rty_i : in std_logic := '0';
wb_eth_stall_i : in std_logic := '0';
......
......@@ -7,7 +7,7 @@
-- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2016-07-26
-- Last update: 2017-07-04
-- Last update: 2018-03-20
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
......@@ -155,7 +155,6 @@ entity wrc_board_vfchd is
wb_cyc_i : in std_logic := '0';
wb_stb_i : in std_logic := '0';
wb_ack_o : out std_logic;
wb_int_o : out std_logic;
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
......@@ -168,7 +167,6 @@ entity wrc_board_vfchd is
aux_master_cyc_o : out std_logic;
aux_master_stb_o : out std_logic;
aux_master_ack_i : in std_logic := '0';
aux_master_int_i : in std_logic := '0';
aux_master_err_i : in std_logic := '0';
aux_master_rty_i : in std_logic := '0';
aux_master_stall_i : in std_logic := '0';
......@@ -230,7 +228,6 @@ entity wrc_board_vfchd is
wb_eth_cyc_o : out std_logic;
wb_eth_stb_o : out std_logic;
wb_eth_ack_i : in std_logic := '0';
wb_eth_int_i : in std_logic := '0';
wb_eth_err_i : in std_logic := '0';
wb_eth_rty_i : in std_logic := '0';
wb_eth_stall_i : in std_logic := '0';
......@@ -342,7 +339,6 @@ begin -- architecture struct
wb_err_o <= wb_slave_out.err;
wb_rty_o <= wb_slave_out.rty;
wb_stall_o <= wb_slave_out.stall;
wb_int_o <= wb_slave_out.int;
wb_dat_o <= wb_slave_out.dat;
aux_master_adr_o <= aux_master_out.adr;
......@@ -354,7 +350,6 @@ begin -- architecture struct
aux_master_in.dat <= aux_master_dat_i;
aux_master_in.ack <= aux_master_ack_i;
aux_master_in.int <= aux_master_int_i;
aux_master_in.err <= aux_master_err_i;
aux_master_in.rty <= aux_master_rty_i;
aux_master_in.stall <= aux_master_stall_i;
......@@ -391,7 +386,6 @@ begin -- architecture struct
wb_eth_master_in.dat <= wb_eth_dat_i;
wb_eth_master_in.ack <= wb_eth_ack_i;
wb_eth_master_in.int <= wb_eth_int_i;
wb_eth_master_in.err <= wb_eth_err_i;
wb_eth_master_in.rty <= wb_eth_rty_i;
wb_eth_master_in.stall <= wb_eth_stall_i;
......
etherbone-core @ f19220ff
Subproject commit 79a6081166043ee24d835cbe7c5e5632dacad1f6
Subproject commit f19220ffa3c5e526f66ebbded5e0e1e789e7255d
gn4124-core @ 3b989e6e
Subproject commit e7cd73db41ba056ed4b27731c21a3b2aa53eaa51
Subproject commit 3b989e6ea4309b939ba1222aafa6dcd9f6dbdbeb
vme64x-core @ 73232ebd
Subproject commit a120e2262e1cb23fa611dddb7fa3727b520a125c
Subproject commit 73232ebd0c03bb48b74764816ef1dbb06e3505db
......@@ -102,7 +102,6 @@ begin
w_slave_o.DAT <= (others => '0');
w_slave_o.STALL <= '0'; -- Never stall; report error if something bad happens
w_slave_o.RTY <= '0';
w_slave_o.INT <= '0'; -- This doesn't belong in the struct :-/
Q : eca_sdp
generic map(
......
......@@ -7,7 +7,7 @@
-- Author(s) : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-02-20
-- Last update: 2017-03-10
-- Last update: 2018-03-20
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level file for the WRPC reference design on the SPEC.
......@@ -391,7 +391,6 @@ begin -- architecture top
csr_stall_i => cnx_master_in(c_WB_MASTER_PCIE).stall,
csr_err_i => cnx_master_in(c_WB_MASTER_PCIE).err,
csr_rty_i => cnx_master_in(c_WB_MASTER_PCIE).rty,
csr_int_i => cnx_master_in(c_WB_MASTER_PCIE).int,
---------------------------------------------------------
-- L2P DMA Interface (Pipelined Wishbone master)
......@@ -400,8 +399,7 @@ begin -- architecture top
dma_ack_i => '1',
dma_stall_i => '0',
dma_err_i => '0',
dma_rty_i => '0',
dma_int_i => '0');
dma_rty_i => '0');
-- "translating" word addressing of Gennum module into byte addressing
cnx_master_out(c_WB_MASTER_PCIE).adr(1 downto 0) <= (others => '0');
......
......@@ -7,7 +7,7 @@
-- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-01-24
-- Last update: 2017-03-10
-- Last update: 2018-03-20
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level file for the WRPC reference design on the VFC-HD.
......@@ -635,14 +635,12 @@ begin -- architecture top
cnx2_slave_out(c_WB_SLAVE_I2CMUX).dat <= X"000000" & i2c_wb_dat_out;
cnx2_slave_out(c_WB_SLAVE_I2CMUX).err <= '0';
cnx2_slave_out(c_WB_SLAVE_I2CMUX).rty <= '0';
cnx2_slave_out(c_WB_SLAVE_I2CMUX).int <= '0';
cnx2_slave_out(c_WB_SLAVE_I2CMUX).stall <= not cnx2_slave_out(c_WB_SLAVE_I2CMUX).ack and
(cnx2_slave_in(c_WB_SLAVE_I2CMUX).stb and
cnx2_slave_in(c_WB_SLAVE_I2CMUX).cyc);
cnx1_slave_out(c_WB_SLAVE_I2CCFG).err <= '0';
cnx1_slave_out(c_WB_SLAVE_I2CCFG).rty <= '0';
cnx1_slave_out(c_WB_SLAVE_I2CCFG).int <= '0';
cnx1_slave_out(c_WB_SLAVE_I2CCFG).stall <= not cnx1_slave_out(c_WB_SLAVE_I2CCFG).ack and
(cnx1_slave_in(c_WB_SLAVE_I2CCFG).stb and
cnx1_slave_in(c_WB_SLAVE_I2CCFG).cyc);
......
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