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White Rabbit core collection
Commit 7c8ec4b7 authored by li hongming's avatar li hongming Committed by Grzegorz Daniluk
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use the 20MHz clock source of multiboot module (required by ICAP max frequency)

parent 971d500b
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Showing with 24 additions and 4 deletions
board/cute/xwrc_board_cute.vhd
View file @ 7c8ec4b7
......@@ -320,6 +320,7 @@ architecture struct of xwrc_board_cute is
signal clk_pll_62m5 : std_logic;
signal clk_pll_125m : std_logic;
signal clk_pll_500m : std_logic;
signal clk_pll_20m : std_logic;
signal clk_pll_dmtd : std_logic;
signal pll_locked : std_logic;
signal clk_10m_ext : std_logic;
......@@ -377,6 +378,9 @@ architecture struct of xwrc_board_cute is
signal multiboot_slave_out : t_wishbone_slave_out;
signal multiboot_slave_in : t_wishbone_slave_in := cc_dummy_slave_in;
signal multiboot_wb_out : t_wishbone_master_out;
signal multiboot_wb_in : t_wishbone_master_in;
begin -- architecture struct
-----------------------------------------------------------------------------
......@@ -419,6 +423,7 @@ begin -- architecture struct
clk_62m5_sys_o => clk_pll_62m5,
clk_125m_ref_o => clk_pll_125m,
clk_500m_o => clk_pll_500m,
clk_20m_o => clk_pll_20m,
clk_62m5_dmtd_o => clk_pll_dmtd,
pll_locked_o => pll_locked,
clk_10m_ext_o => clk_10m_ext,
......@@ -681,12 +686,23 @@ U_WRPC_MULTIBOOT: if (g_multiboot_enable = true) generate
aux_master_in <= multiboot_slave_out;
aux_master_o <= cc_dummy_master_out;
cmp_clock_crossing: xwb_clock_crossing
port map (
slave_clk_i => clk_pll_62m5,
slave_rst_n_i => rst_62m5_n,
slave_i => multiboot_slave_in,
slave_o => multiboot_slave_out,
master_clk_i => clk_pll_20m,
master_rst_n_i => '1',
master_i => multiboot_wb_in,
master_o => multiboot_wb_out);
u_multiboot: xwb_xil_multiboot
port map (
clk_i => clk_pll_62m5,
rst_n_i => rst_62m5_n,
wbs_i => multiboot_slave_in,
wbs_o => multiboot_slave_out,
clk_i => clk_pll_20m,
rst_n_i => '1',
wbs_i => multiboot_wb_out,
wbs_o => multiboot_wb_in,
spi_cs_n_o => open,
spi_sclk_o => open,
spi_mosi_o => open,
......
platform/xilinx/wr_xilinx_pkg.vhd
View file @ 7c8ec4b7
......@@ -97,6 +97,7 @@ package wr_xilinx_pkg is
pll_aux_locked_o : out std_logic;
clk_62m5_sys_o : out std_logic;
clk_125m_ref_o : out std_logic;
clk_20m_o : out std_logic;
clk_ref_locked_o : out std_logic;
clk_62m5_dmtd_o : out std_logic;
pll_locked_o : out std_logic;
......
platform/xilinx/xwrc_platform_xilinx.vhd
View file @ 7c8ec4b7
......@@ -150,6 +150,7 @@ entity xwrc_platform_xilinx is
-- PLL outputs
clk_62m5_sys_o : out std_logic;
clk_125m_ref_o : out std_logic;
clk_20m_o : out std_logic;
clk_ref_locked_o : out std_logic;
clk_62m5_dmtd_o : out std_logic;
pll_locked_o : out std_logic;
......@@ -238,6 +239,7 @@ begin -- architecture rtl
-- 125MHz reference clock
gen_spartan6_default_plls : if (g_fpga_family = "spartan6") generate
signal clk_20m : std_logic;
signal clk_sys : std_logic;
signal clk_sys_out : std_logic;
signal clk_sys_fb : std_logic;
......@@ -328,6 +330,7 @@ begin -- architecture rtl
O => clk_125m_pllref_buf,
I => clk_125m_pllref_buf_int2);
clk_20m_o <= clk_20m_vcxo_buf;
clk_62m5_sys_o <= clk_sys_out;
clk_125m_ref_o <= clk_125m_pllref_buf;
pll_locked_o <= pll_sys_locked and pll_dmtd_locked;
......
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