Commit 7eaac3d8 authored by Dimitris Lampridis's avatar Dimitris Lampridis

board/vfchd: Introduce board support package for the VFC-HD board

parent f8e30f3a
This diff is collapsed.
files = [
"wr_vfchd_pkg.vhd",
"xwrc_board_vfchd.vhd",
"wrc_board_vfchd.vhd",
"sfp_i2c_adapter.vhd",
]
-------------------------------------------------------------------------------
-- Title : SFP I2C adapter for VFC-HD board
-- Project : WR PTP Core
-- URL : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
-------------------------------------------------------------------------------
-- File : sfp_i2c_adapter.vhd
-- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2016-11-25
-- Last update: 2016-11-28
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Simple interface betweent the I2C master port of the WR PTP
-- core (used to retrieve the SFP configuration) and the parallel interface
-- provided by the VFC-HD board. Uses internally the I2C slave from
-- general-cores.
-------------------------------------------------------------------------------
-- Copyright (c) 2016 CERN
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.gencores_pkg.all;
entity sfp_i2c_adapter is
port (
-- Clock, reset ports
clk_i : in std_logic;
rst_n_i : in std_logic;
-- I2C lines
scl_i : in std_logic;
sda_i : in std_logic;
sda_en_o : out std_logic;
-- HIGH if both of the following are true:
-- 1. SFP is detected (plugged in)
-- 2. The part number has been successfully read after the SFP detection
sfp_det_valid_i : in std_logic;
-- 16 byte vendor Part Number (PN)
-- (ASCII encoded, first character byte in bits 127 downto 120)
sfp_data_i : in std_logic_vector (127 downto 0)
);
end entity sfp_i2c_adapter;
architecture rtl of sfp_i2c_adapter is
-----------------------------------------------------------------------------
-- Types
-----------------------------------------------------------------------------
-- 64-byte array representing the DDM serial ID area of the SFP management
type t_sfp_ddm_serial_id is array (0 to 63) of std_logic_vector(7 downto 0);
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal sfp_i2c_tx_byte : std_logic_vector(7 downto 0);
signal sfp_i2c_rx_byte : std_logic_vector(7 downto 0);
signal sfp_i2c_r_done : std_logic;
signal sfp_i2c_w_done : std_logic;
signal sfp_ddm_din : t_sfp_ddm_serial_id := (others => (others => '0'));
signal sfp_ddm_reg : t_sfp_ddm_serial_id := (others => (others => '0'));
signal sfp_ddm_addr : unsigned(5 downto 0);
signal sfp_ddm_sum : unsigned(7 downto 0);
begin -- architecture rtl
cmp_gc_i2c_slave : gc_i2c_slave
generic map (
g_auto_addr_ack => TRUE)
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
scl_i => scl_i,
-- clock streching not implemented by module
scl_o => open,
scl_en_o => open,
sda_i => sda_i,
-- sda_o is not necessary, sda_en has all the info that we need
sda_o => open,
sda_en_o => sda_en_o,
-- standard SFP management I2C address
i2c_addr_i => "1010000",
-- no need to ACK, we use auto address ACK
-- and only use one byte writes
ack_i => '0',
tx_byte_i => sfp_i2c_tx_byte,
rx_byte_o => sfp_i2c_rx_byte,
-- we only care about r_done (new address)
-- and w_done (load next byte from serial_id)
i2c_sta_p_o => open,
i2c_sto_p_o => open,
addr_good_p_o => open,
r_done_p_o => sfp_i2c_r_done,
w_done_p_o => sfp_i2c_w_done,
op_o => open);
-- Populate the sfp_ddm Vendor PN using the sfp_data_i input
gen_sfp_ddm_data : for i in 0 to 15 generate
sfp_ddm_din(40+i) <= sfp_data_i(127-i*8 downto 120-i*8);
end generate gen_sfp_ddm_data;
-- Calculate CC_BASE for the last byte of the sfp_ddm.
-- We only sum the 16 bytes, all other bytes are zero anyway.
sfp_ddm_sum <=
(((unsigned(sfp_data_i(127 downto 120)) + unsigned(sfp_data_i(119 downto 112))) +
(unsigned(sfp_data_i(111 downto 104)) + unsigned(sfp_data_i(103 downto 96)))) +
((unsigned(sfp_data_i(95 downto 88)) + unsigned(sfp_data_i(87 downto 80))) +
(unsigned(sfp_data_i(79 downto 72)) + unsigned(sfp_data_i(71 downto 64))))) +
(((unsigned(sfp_data_i(63 downto 56)) + unsigned(sfp_data_i(55 downto 48))) +
(unsigned(sfp_data_i(47 downto 40)) + unsigned(sfp_data_i(39 downto 32)))) +
((unsigned(sfp_data_i(31 downto 24)) + unsigned(sfp_data_i(23 downto 16))) +
(unsigned(sfp_data_i(15 downto 8)) + unsigned(sfp_data_i(7 downto 0)))));
sfp_ddm_din(63) <= std_logic_vector(sfp_ddm_sum);
-- always offer to send the next byte pointed to by the address counter
sfp_i2c_tx_byte <= sfp_ddm_reg(to_integer(sfp_ddm_addr));
-- Drive the SFP DDM based on the r_done/w_done pulses
p_sfp_ddm_addr_counter : process (clk_i) is
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
sfp_ddm_addr <= (others => '0');
sfp_ddm_reg <= (others => (others => '0'));
else
-- check valid flag to load DDM register
if sfp_det_valid_i = '1' then
sfp_ddm_reg <= sfp_ddm_din;
else
sfp_ddm_reg <= (others => (others => '0'));
end if;
if sfp_i2c_r_done = '1' then
-- update address pointer with new value
sfp_ddm_addr <= unsigned(sfp_i2c_rx_byte(5 downto 0));
elsif sfp_i2c_w_done = '1' then
-- increase address pointer
sfp_ddm_addr <= sfp_ddm_addr + 1;
end if;
end if;
end if;
end process p_sfp_ddm_addr_counter;
end architecture rtl;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.wishbone_pkg.all;
use work.wr_fabric_pkg.all;
package wr_vfchd_pkg is
component xwrc_board_vfchd is
generic (
g_simulation : integer := 0;
g_with_external_clock_input : boolean := TRUE;
g_pcs_16bit : boolean := FALSE;
g_fabric_iface : string := "plain";
g_streamer_width : integer := 32;
g_dpram_initf : string := "../../bin/wrpc/wrc_phy8.mif");
port (
clk_board_125m_i : in std_logic;
clk_board_20m_i : in std_logic;
clk_ext_10m_i : in std_logic;
areset_n_i : in std_logic;
clk_sys_62m5_o : out std_logic;
clk_ref_125m_o : out std_logic;
rst_sys_62m5_o : out std_logic;
dac_ref_sync_n_o : out std_logic;
dac_dmtd_sync_n_o : out std_logic;
dac_din_o : out std_logic;
dac_sclk_o : out std_logic;
sfp_tx_o : out std_logic;
sfp_rx_i : in std_logic;
sfp_det_valid_i : in std_logic;
sfp_data_i : in std_logic_vector (127 downto 0);
sfp_tx_fault_i : in std_logic;
sfp_los_i : in std_logic;
sfp_tx_disable_o : out std_logic;
eeprom_sda_i : in std_logic;
eeprom_sda_o : out std_logic;
eeprom_scl_i : in std_logic;
eeprom_scl_o : out std_logic;
onewire_i : in std_logic;
onewire_oen_o : out std_logic;
wb_slave_o : out t_wishbone_slave_out;
wb_slave_i : in t_wishbone_slave_in := cc_dummy_slave_in;
wrf_src_o : out t_wrf_source_out;
wrf_src_i : in t_wrf_source_in := c_dummy_src_in;
wrf_snk_o : out t_wrf_sink_out;
wrf_snk_i : in t_wrf_sink_in := c_dummy_snk_in;
wrs_tx_data_i : in std_logic_vector(g_streamer_width-1 downto 0) := (others => '0');
wrs_tx_valid_i : in std_logic := '0';
wrs_tx_dreq_o : out std_logic;
wrs_tx_last_i : in std_logic := '1';
wrs_tx_flush_i : in std_logic := '0';
wrs_rx_first_o : out std_logic;
wrs_rx_last_o : out std_logic;
wrs_rx_data_o : out std_logic_vector(g_streamer_width-1 downto 0);
wrs_rx_valid_o : out std_logic;
wrs_rx_dreq_i : in std_logic := '0';
wb_eth_master_o : out t_wishbone_master_out;
wb_eth_master_i : in t_wishbone_master_in := cc_dummy_master_in;
pps_ext_i : in std_logic;
pps_p_o : out std_logic;
pps_led_o : out std_logic;
tm_time_valid_o : out std_logic;
tm_tai_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
led_link_o : out std_logic;
led_act_o : out std_logic);
end component xwrc_board_vfchd;
component wrc_board_vfchd is
generic (
g_simulation : integer := 0;
g_with_external_clock_input : integer := 1;
g_pcs_16bit : integer := 0;
g_fabric_iface : string := "plain";
g_streamer_width : integer := 32;
g_dpram_initf : string := "../../bin/wrpc/wrc_phy8.mif");
port (
clk_board_125m_i : in std_logic;
clk_board_20m_i : in std_logic;
clk_ext_10m_i : in std_logic;
areset_n_i : in std_logic;
clk_sys_62m5_o : out std_logic;
clk_ref_125m_o : out std_logic;
rst_sys_62m5_o : out std_logic;
dac_ref_sync_n_o : out std_logic;
dac_dmtd_sync_n_o : out std_logic;
dac_din_o : out std_logic;
dac_sclk_o : out std_logic;
sfp_tx_o : out std_logic;
sfp_rx_i : in std_logic;
sfp_det_valid_i : in std_logic;
sfp_data_i : in std_logic_vector (127 downto 0);
sfp_tx_fault_i : in std_logic;
sfp_los_i : in std_logic;
sfp_tx_disable_o : out std_logic;
eeprom_sda_i : in std_logic;
eeprom_sda_o : out std_logic;
eeprom_scl_i : in std_logic;
eeprom_scl_o : out std_logic;
onewire_i : in std_logic;
onewire_oen_o : out std_logic;
wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0) := (others => '0');
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_sel_i : in std_logic_vector(c_wishbone_address_width/8-1 downto 0) := (others => '0');
wb_we_i : in std_logic := '0';
wb_cyc_i : in std_logic := '0';
wb_stb_i : in std_logic := '0';
wb_ack_o : out std_logic;
wb_int_o : out std_logic;
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
wrf_src_adr : out std_logic_vector(1 downto 0);
wrf_src_dat : out std_logic_vector(15 downto 0);
wrf_src_cyc : out std_logic;
wrf_src_stb : out std_logic;
wrf_src_we : out std_logic;
wrf_src_sel : out std_logic_vector(1 downto 0);
wrf_src_ack : in std_logic;
wrf_src_stall : in std_logic;
wrf_src_err : in std_logic;
wrf_src_rty : in std_logic;
wrf_snk_adr : in std_logic_vector(1 downto 0);
wrf_snk_dat : in std_logic_vector(15 downto 0);
wrf_snk_cyc : in std_logic;
wrf_snk_stb : in std_logic;
wrf_snk_we : in std_logic;
wrf_snk_sel : in std_logic_vector(1 downto 0);
wrf_snk_ack : out std_logic;
wrf_snk_stall : out std_logic;
wrf_snk_err : out std_logic;
wrf_snk_rty : out std_logic;
trans_tx_data_i : in std_logic_vector(g_streamer_width-1 downto 0) := (others => '0');
trans_tx_valid_i : in std_logic := '0';
trans_tx_dreq_o : out std_logic;
trans_tx_last_i : in std_logic := '1';
trans_tx_flush_i : in std_logic := '0';
trans_rx_first_o : out std_logic;
trans_rx_last_o : out std_logic;
trans_rx_data_o : out std_logic_vector(g_streamer_width-1 downto 0);
trans_rx_valid_o : out std_logic;
trans_rx_dreq_i : in std_logic := '0';
wb_eth_adr_o : out std_logic_vector(c_wishbone_address_width-1 downto 0);
wb_eth_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_eth_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
wb_eth_sel_o : out std_logic_vector(c_wishbone_address_width/8-1 downto 0);
wb_eth_we_o : out std_logic;
wb_eth_cyc_o : out std_logic;
wb_eth_stb_o : out std_logic;
wb_eth_ack_i : in std_logic := '0';
wb_eth_int_i : in std_logic := '0';
wb_eth_err_i : in std_logic := '0';
wb_eth_rty_i : in std_logic := '0';
wb_eth_stall_i : in std_logic := '0';
pps_ext_i : in std_logic;
pps_p_o : out std_logic;
pps_led_o : out std_logic;
tm_time_valid_o : out std_logic;
tm_tai_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
led_link_o : out std_logic;
led_act_o : out std_logic);
end component wrc_board_vfchd;
component sfp_i2c_adapter is
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
scl_i : in std_logic;
sda_i : in std_logic;
sda_en_o : out std_logic;
sfp_det_valid_i : in std_logic;
sfp_data_i : in std_logic_vector (127 downto 0));
end component sfp_i2c_adapter;
end wr_vfchd_pkg;
This diff is collapsed.
This diff is collapsed.
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment