Skip to content

W
White Rabbit core collection
Commit 814e2ab2 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
Browse files
Options

g_with_dmtd generic from wr_endpoint propagated to xwr_endpoint and wr_core

parent 3ddf7c25
Show whitespace changes
Inline Side-by-side
Showing with 73 additions and 68 deletions
modules/wr_endpoint/endpoint_pkg.vhd
View file @ 814e2ab2
......@@ -21,7 +21,8 @@ package endpoint_pkg is
g_with_dpi_classifier : boolean := false;
g_with_vlans : boolean := false;
g_with_rtu : boolean := false;
g_with_leds : boolean := false);
g_with_leds : boolean := false;
g_with_dmtd : boolean := false);
port (
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
......@@ -91,7 +92,7 @@ package endpoint_pkg is
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_ack_o : out std_logic;
wb_stall_o: out std_logic;
wb_stall_o : out std_logic;
led_link_o : out std_logic;
led_act_o : out std_logic);
end component;
......@@ -110,11 +111,12 @@ package endpoint_pkg is
g_with_dpi_classifier : boolean := false;
g_with_vlans : boolean := false;
g_with_rtu : boolean := false;
g_with_leds : boolean := false);
g_with_leds : boolean := false;
g_with_dmtd : boolean := false);
port (
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
clk_dmtd_i: in std_logic := '0';
clk_dmtd_i : in std_logic := '0';
rst_n_i : in std_logic;
pps_csync_p1_i : in std_logic := '0';
phy_rst_o : out std_logic;
......
modules/wr_endpoint/xwr_endpoint.vhd
View file @ 814e2ab2
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-04-26
-- Last update: 2012-01-23
-- Last update: 2012-03-07
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -41,7 +41,8 @@ entity xwr_endpoint is
g_with_dpi_classifier : boolean := true;
g_with_vlans : boolean := true;
g_with_rtu : boolean := true;
g_with_leds : boolean := true
g_with_leds : boolean := true;
g_with_dmtd : boolean := true
);
port (
......@@ -55,7 +56,7 @@ entity xwr_endpoint is
-- reference clock / 2 (62.5 MHz, in-phase with refclk)
clk_sys_i : in std_logic;
clk_dmtd_i: in std_logic;
clk_dmtd_i : in std_logic;
-- sync reset (clk_sys_i domain), active LO
rst_n_i : in std_logic;
......@@ -102,11 +103,11 @@ entity xwr_endpoint is
-- Wishbone I/O
---------------------------------------------------------------------------
src_o: out t_wrf_source_out;
src_i: in t_wrf_source_in;
src_o : out t_wrf_source_out;
src_i : in t_wrf_source_in;
snk_o: out t_wrf_sink_out;
snk_i: in t_wrf_sink_in;
snk_o : out t_wrf_sink_out;
snk_i : in t_wrf_sink_in;
-------------------------------------------------------------------------------
-- TX timestamping unit interface
......@@ -132,10 +133,10 @@ entity xwr_endpoint is
-------------------------------------------------------------------------------
-- 1 indicates that coresponding RTU port is full.
rtu_full_i : in std_logic:='0';
rtu_full_i : in std_logic := '0';
-- 1 indicates that coresponding RTU port is almost full.
rtu_almost_full_i : in std_logic:='0';
rtu_almost_full_i : in std_logic := '0';
-- request strobe, single HI pulse begins evaluation of the request.
rtu_rq_strobe_p1_o : out std_logic;
......@@ -161,15 +162,15 @@ entity xwr_endpoint is
-- Wishbone bus
-------------------------------------------------------------------------------
wb_i: in t_wishbone_slave_in;
wb_o: out t_wishbone_slave_out;
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out;
-------------------------------------------------------------------------------
-- Misc stuff
-------------------------------------------------------------------------------
led_link_o: out std_logic;
led_act_o: out std_logic
led_link_o : out std_logic;
led_act_o : out std_logic
);
......@@ -179,7 +180,7 @@ architecture syn of xwr_endpoint is
begin
U_Wrapped_Endpoint: wr_endpoint
U_Wrapped_Endpoint : wr_endpoint
generic map (
g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity,
......@@ -194,7 +195,8 @@ begin
g_with_dpi_classifier => g_with_dpi_classifier,
g_with_vlans => g_with_vlans,
g_with_rtu => g_with_rtu,
g_with_leds => g_with_leds)
g_with_leds => g_with_leds,
g_with_dmtd => g_with_dmtd)
port map (
clk_ref_i => clk_ref_i,
clk_sys_i => clk_sys_i,
......
modules/wrc_core/wr_core.vhd
View file @ 814e2ab2
......@@ -5,7 +5,7 @@
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-02-02
-- Last update: 2012-02-28
-- Last update: 2012-03-07
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -471,7 +471,8 @@ begin
g_with_dpi_classifier => true,
g_with_vlans => false,
g_with_rtu => false,
g_with_leds => false)
g_with_leds => false,
g_with_dmtd => true)
port map (
clk_ref_i => clk_ref_i,
clk_sys_i => clk_sys_i,
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment