Commit 832831cc authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

timing/dmtd_with_deglitcher: optional /2 input divider for FPGA routing improvement

parent 4f86239f
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-02-25
-- Last update: 2012-03-06
-- Last update: 2012-04-30
-- Platform : FPGA-generic
-- Standard : VHDL '93
-------------------------------------------------------------------------------
......@@ -56,7 +56,12 @@ entity dmtd_with_deglitcher is
-- the following formula:
-- g_counter_bits = log2(f_in / abs(f_in - f_dmtd)) + 1
g_counter_bits : natural := 17;
g_chipscope : boolean := false
g_chipscope : boolean := false;
-- Divides the inputs by 2 (effectively passing the clock through a flip flop)
-- before it gets to the DMTD, effectively removing Place&Route warnings
-- (at the cost of detector bandwidth)
g_divide_input_by_2 : boolean := false
);
port (
-- resets for different clock domains
......@@ -114,8 +119,7 @@ architecture rtl of dmtd_with_deglitcher is
signal in_d0, in_d1 : std_logic;
signal s_one : std_logic;
--attribute optimize_primitives : string;
--attribute optimize_primitives of clk_i_d0:signal is "yes";
--attribute keep : string;
--attribute keep of clk_i_d0: signal is “true”;
--attribute keep of clk_i_d1: signal is “true”;
--attribute keep of clk_i_d2: signal is “true”;
......@@ -128,35 +132,28 @@ architecture rtl of dmtd_with_deglitcher is
signal tag_int : unsigned(g_counter_bits-1 downto 0);
component chipscope_ila
port (
CONTROL : inout std_logic_vector(35 downto 0);
CLK : in std_logic;
TRIG0 : in std_logic_vector(31 downto 0);
TRIG1 : in std_logic_vector(31 downto 0);
TRIG2 : in std_logic_vector(31 downto 0);
TRIG3 : in std_logic_vector(31 downto 0));
end component;
component chipscope_icon
port (
CONTROL0 : inout std_logic_vector (35 downto 0));
end component;
signal CONTROL : std_logic_vector(35 downto 0);
signal CLK : std_logic;
signal TRIG0 : std_logic_vector(31 downto 0);
signal TRIG1 : std_logic_vector(31 downto 0);
signal TRIG2 : std_logic_vector(31 downto 0);
signal TRIG3 : std_logic_vector(31 downto 0);
signal clk_in : std_logic;
begin -- rtl
gen_input_div2: if(g_divide_input_by_2 = true) generate
p_divide_input_clock: process(clk_in_i, rst_n_sysclk_i)
begin
if rst_n_sysclk_i = '0' then
clk_in <= '0';
elsif rising_edge(clk_in_i) then
clk_in <= not clk_in;
end if;
end process;
end generate gen_input_div2;
gen_input_straight: if(g_divide_input_by_2 = false) generate
clk_in <= clk_in_i;
end generate gen_input_straight;
p_the_dmtd_itself : process(clk_dmtd_i)
begin
if rising_edge(clk_dmtd_i) then
clk_i_d0 <= clk_in_i;
clk_i_d0 <= clk_in;
clk_i_d1 <= clk_i_d0;
clk_i_d2 <= clk_i_d1;
clk_i_d3 <= clk_i_d2;
......@@ -248,30 +245,6 @@ begin -- rtl
pulse_i => new_edge_p,
extended_o => dbg_dmtdout_o);
gen_with_csc : if(g_chipscope) generate
chipscope_ila_1 : chipscope_ila
port map (
CONTROL => CONTROL,
CLK => clk_dmtd_i,
TRIG0 => TRIG0,
TRIG1 => TRIG1,
TRIG2 => TRIG2,
TRIG3 => TRIG3);
chipscope_icon_1 : chipscope_icon
port map (
CONTROL0 => CONTROL);
TRIG0(tag_int'left downto 0) <= std_logic_vector(tag_int);
TRIG0(31) <= clk_i_d3;
TRIG0(30) <= '1' when (state = WAIT_STABLE_0) else '0';
TRIG0(29) <= '1' when (state = WAIT_EDGE) else '0';
TRIG0(28) <= '1' when (state = GOT_EDGE) else '0';
TRIG1(stab_cntr'left downto 0) <= std_logic_vector(stab_cntr);
TRIG2(free_cntr'left downto 0) <= std_logic_vector(free_cntr);
end generate gen_with_csc;
end rtl;
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