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White Rabbit core collection
Commits
836bccd7
Commit
836bccd7
authored
Dec 14, 2017
by
Grzegorz Daniluk
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no technical change, cleanup copyright and license notices
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45 changed files
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1130 additions
and
17 deletions
+1130
-17
wr_clbv2_pkg.vhd
board/clbv2/wr_clbv2_pkg.vhd
+34
-0
wr_clbv3_pkg.vhd
board/clbv3/wr_clbv3_pkg.vhd
+34
-0
wr_board_pkg.vhd
board/common/wr_board_pkg.vhd
+32
-0
xwrc_board_common.vhd
board/common/xwrc_board_common.vhd
+2
-4
wr_fasec_pkg.vhd
board/fasec/wr_fasec_pkg.vhd
+35
-0
wr_spec_pkg.vhd
board/spec/wr_spec_pkg.vhd
+34
-0
wr_svec_pkg.vhd
board/svec/wr_svec_pkg.vhd
+34
-0
wr_vfchd_pkg.vhd
board/vfchd/wr_vfchd_pkg.vhd
+34
-0
wr_fabric_pkg.vhd
modules/fabric/wr_fabric_pkg.vhd
+31
-0
xwb_fabric_source.vhd
modules/fabric/xwb_fabric_source.vhd
+33
-0
xwrf_mux.vhd
modules/fabric/xwrf_mux.vhd
+19
-2
xwrf_reg.vhd
modules/fabric/xwrf_reg.vhd
+30
-0
multi_dmtd_with_deglitcher.vhd
modules/timing/multi_dmtd_with_deglitcher.vhd
+30
-0
spec_serial_dac.vhd
modules/wr_dacs/spec_serial_dac.vhd
+22
-3
spec_serial_dac_arb.vhd
modules/wr_dacs/spec_serial_dac_arb.vhd
+31
-0
endpoint_pkg.vhd
modules/wr_endpoint/endpoint_pkg.vhd
+1
-1
ep_crc32_pkg.vhd
modules/wr_endpoint/ep_crc32_pkg.vhd
+31
-0
ep_leds_controller.vhd
modules/wr_endpoint/ep_leds_controller.vhd
+31
-0
ep_rtu_header_extract.vhd
modules/wr_endpoint/ep_rtu_header_extract.vhd
+31
-0
ep_rx_crc_size_check.vhd
modules/wr_endpoint/ep_rx_crc_size_check.vhd
+31
-0
ep_rx_early_address_match.vhd
modules/wr_endpoint/ep_rx_early_address_match.vhd
+31
-0
ep_rx_oob_insert.vhd
modules/wr_endpoint/ep_rx_oob_insert.vhd
+31
-0
ep_rx_status_reg_insert.vhd
modules/wr_endpoint/ep_rx_status_reg_insert.vhd
+31
-0
ep_rx_vlan_unit.vhd
modules/wr_endpoint/ep_rx_vlan_unit.vhd
+31
-0
ep_rx_wb_master.vhd
modules/wr_endpoint/ep_rx_wb_master.vhd
+18
-0
ep_sync_detect.vhd
modules/wr_endpoint/ep_sync_detect.vhd
+18
-0
ep_sync_detect_16bit.vhd
modules/wr_endpoint/ep_sync_detect_16bit.vhd
+18
-0
ep_timestamping_unit.vhd
modules/wr_endpoint/ep_timestamping_unit.vhd
+18
-0
ep_ts_counter.vhd
modules/wr_endpoint/ep_ts_counter.vhd
+18
-0
ep_tx_framer.vhd
modules/wr_endpoint/ep_tx_framer.vhd
+18
-0
minic_packet_buffer.vhd
modules/wr_mini_nic/minic_packet_buffer.vhd
+18
-0
wr_mini_nic.vhd
modules/wr_mini_nic/wr_mini_nic.vhd
+18
-0
xwr_mini_nic.vhd
modules/wr_mini_nic/xwr_mini_nic.vhd
+33
-0
wr_pps_gen.vhd
modules/wr_pps_gen/wr_pps_gen.vhd
+19
-1
xwr_pps_gen.vhd
modules/wr_pps_gen/xwr_pps_gen.vhd
+18
-0
spll_aligner.vhd
modules/wr_softpll_ng/spll_aligner.vhd
+31
-0
spll_bangbang_pd.vhd
modules/wr_softpll_ng/spll_bangbang_pd.vhd
+18
-0
spll_period_detect.vhd
modules/wr_softpll_ng/spll_period_detect.vhd
+18
-0
wr_tbi_phy.vhd
modules/wr_tbi_phy/wr_tbi_phy.vhd
+18
-0
wr_altera_pkg.vhd
platform/altera/wr_altera_pkg.vhd
+34
-0
gtp_bitslide.vhd
platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd
+16
-2
gtp_phase_align.vhd
platform/xilinx/wr_gtp_phy/spartan6/gtp_phase_align.vhd
+16
-2
gtp_phase_align_virtex6.vhd
...orm/xilinx/wr_gtp_phy/virtex6/gtp_phase_align_virtex6.vhd
+16
-2
gtx_reset.vhd
platform/xilinx/wr_gtp_phy/virtex6/gtx_reset.vhd
+33
-0
wr_xilinx_pkg.vhd
platform/xilinx/wr_xilinx_pkg.vhd
+32
-0
No files found.
board/clbv2/wr_clbv2_pkg.vhd
View file @
836bccd7
-------------------------------------------------------------------------------
-- Title : WRPC Wrapper for clbv2 package
-- Project : WR PTP Core
-- URL : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
-------------------------------------------------------------------------------
-- File : wr_clbv2_pkg.vhd
-- Author(s) : Peter Jansweijer <peterj@nikhef.nl>
-- Company : Nikhef
-- Created : 2017-11-08
-- Last update: 2017-11-08
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Copyright (c) 2017 Nikhef
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
...
...
board/clbv3/wr_clbv3_pkg.vhd
View file @
836bccd7
-------------------------------------------------------------------------------
-- Title : WRPC Wrapper for clbv3 package
-- Project : WR PTP Core
-- URL : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
-------------------------------------------------------------------------------
-- File : wr_clbv3_pkg.vhd
-- Author(s) : Peter Jansweijer <peterj@nikhef.nl>
-- Company : Nikhef
-- Created : 2017-11-08
-- Last update: 2017-11-08
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Copyright (c) 2017 Nikhef
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
...
...
board/common/wr_board_pkg.vhd
View file @
836bccd7
-------------------------------------------------------------------------------
-- Title : Common WRPC Wrapper package
-- Project : WR PTP Core
-- URL : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
-------------------------------------------------------------------------------
-- File : xwrc_board_common.vhd
-- Company : CERN (BE-CO-HT)
-- Standard : VHDL'93
-------------------------------------------------------------------------------
--
-- Copyright (c) 2017 CERN
--
-- GNU LESSER GENERAL PUBLIC LICENSE
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
...
...
board/common/xwrc_board_common.vhd
View file @
836bccd7
...
...
@@ -4,18 +4,16 @@
-- URL : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
-------------------------------------------------------------------------------
-- File : xwrc_board_common.vhd
-- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-02-22
-- Last update: 2017-05-29
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Wrapper for WR PTP core with common features shared between
-- the various supported boards. These include the core itself, as well as
-- a selection of fabric interfaces between the core and the application.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2017 CERN
--
-----------------------------------------------------------------------------
--
-- GNU LESSER GENERAL PUBLIC LICENSE
--
-- This source file is free software; you can redistribute it
...
...
board/fasec/wr_fasec_pkg.vhd
View file @
836bccd7
-------------------------------------------------------------------------------
-- Title : WRPC Wrapper for FASEC package
-- Project : WR PTP Core
-- URL : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
-------------------------------------------------------------------------------
-- File : wr_fasec_pkg.vhd
-- Author(s) : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-08-02
-- Last update: 2017-09-07
-- Standard : VHDL'93
-------------------------------------------------------------------------------
--
-- Copyright (c) 2017 CERN
--
-- GNU LESSER GENERAL PUBLIC LICENSE
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
...
...
board/spec/wr_spec_pkg.vhd
View file @
836bccd7
-------------------------------------------------------------------------------
-- Title : WRPC Wrapper for SPEC package
-- Project : WR PTP Core
-- URL : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
-------------------------------------------------------------------------------
-- File : wr_spec_pkg.vhd
-- Author(s) : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-02-17
-- Last update: 2017-07-04
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Copyright (c) 2017 CERN
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
...
...
board/svec/wr_svec_pkg.vhd
View file @
836bccd7
-------------------------------------------------------------------------------
-- Title : WRPC Wrapper for SVEC package
-- Project : WR PTP Core
-- URL : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
-------------------------------------------------------------------------------
-- File : wr_svec_pkg.vhd
-- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-02-16
-- Last update: 2017-07-04
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Copyright (c) 2017 CERN
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
...
...
board/vfchd/wr_vfchd_pkg.vhd
View file @
836bccd7
-------------------------------------------------------------------------------
-- Title : WRPC Wrapper for VFC-HD package
-- Project : WR PTP Core
-- URL : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
-------------------------------------------------------------------------------
-- File : wr_vfchd_pkg.vhd
-- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2016-07-26
-- Last update: 2017-07-04
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Copyright (c) 2016-2017 CERN
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
...
...
modules/fabric/wr_fabric_pkg.vhd
View file @
836bccd7
-------------------------------------------------------------------------------
-- Title : Wishbone Packet Fabric package
-- Project : WR Cores Collection
-------------------------------------------------------------------------------
-- File : wr_fabric_pkg.vhd
-- Author : Grzegorz Daniluk
-- Company : CERN BE-CO-HT
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012-2017 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
work
.
wishbone_pkg
.
all
;
...
...
modules/fabric/xwb_fabric_source.vhd
View file @
836bccd7
-------------------------------------------------------------------------------
-- Title : Wishbone Packet Fabric buffered packet source
-- Project : WR Cores Collection
-------------------------------------------------------------------------------
-- File : xwb_fabric_source.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2012-01-16
-- Last update: 2012-01-22
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
...
...
modules/fabric/xwrf_mux.vhd
View file @
836bccd7
...
...
@@ -2,7 +2,7 @@
-- Title : Simple Pipelined Wishbone MUX/DEMUX for WRPC
-- Project : WhiteRabbit
-------------------------------------------------------------------------------
-- File : wrf_mux.vhd
-- File :
x
wrf_mux.vhd
-- Author : Grzegorz Daniluk
-- Company : CERN BE-CO-HT
-- Created : 2011-08-11
...
...
@@ -18,7 +18,24 @@
-- has to be forwarded to Mini-NIC (if it is the PTP message) or to the
-- external interface (others).
-------------------------------------------------------------------------------
-- Copyright (c) 2012 - 2017 CERN
-- Copyright (c) 2012-2017 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
...
...
modules/fabric/xwrf_reg.vhd
View file @
836bccd7
-------------------------------------------------------------------------------
-- Title : Simple WB Fabric register
-- Project : WhiteRabbit
-------------------------------------------------------------------------------
-- File : xwrf_mux.vhd
-- Author : Grzegorz Daniluk
-- Company : CERN BE-CO-HT
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Copyright (c) 2014 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
...
...
modules/timing/multi_dmtd_with_deglitcher.vhd
View file @
836bccd7
-------------------------------------------------------------------------------
-- Title : Multi Digital DMTD Phase Measurement Unit
-- Project : White Rabbit
-------------------------------------------------------------------------------
-- File : multi_dmtd_with_deglitcher.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Platform : FPGA-generic
-- Standard : VHDL '93
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
NUMERIC_STD
.
all
;
...
...
modules/wr_dacs/spec_serial_dac.vhd
View file @
836bccd7
-------------------------------------------------------------------------------
-- Title : Serial DAC interface
-- Project : White Rabbit
Switch
-- Project : White Rabbit
-------------------------------------------------------------------------------
-- File : serial_dac.vhd
-- File : s
pec_s
erial_dac.vhd
-- Author : paas, slayer
-- Company : CERN BE-Co-HT
-- Created : 2010-02-25
...
...
@@ -10,10 +10,29 @@
-- Platform : fpga-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: The dac unit provides an interface to a 16 bit serial Digita to Analogue converter (max5441, SPI?/QSPI?/MICROWIRE? compatible)
-- Description: The dac unit provides an interface to a 16 bit serial Digital
-- to Analogue converter (max5441, SPI?/QSPI?/MICROWIRE? compatible)
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :1
-- Date Version Author Description
...
...
modules/wr_dacs/spec_serial_dac_arb.vhd
View file @
836bccd7
-------------------------------------------------------------------------------
-- Title : SPEC serial DAC interface with arbiter
-- Project : White Rabbit
-------------------------------------------------------------------------------
-- File : spec_serial_dac.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Platform : fpga-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
...
...
modules/wr_endpoint/endpoint_pkg.vhd
View file @
836bccd7
...
...
@@ -14,7 +14,7 @@
-- structures and component declarations.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011
-
2017 CERN / BE-CO-HT
-- Copyright (c) 2011
-
2017 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
...
...
modules/wr_endpoint/ep_crc32_pkg.vhd
View file @
836bccd7
-------------------------------------------------------------------------------
-- Title : CRC32 package
-- Project : White Rabbit
-------------------------------------------------------------------------------
-- File : ep_crc32_pkg.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Platform : FPGA-generic
-- Standard : VHDL '93
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012-2013 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
...
...
modules/wr_endpoint/ep_leds_controller.vhd
View file @
836bccd7
-------------------------------------------------------------------------------
-- Title : Endpoint LEDs controller
-- Project : White Rabbit
-------------------------------------------------------------------------------
-- File : ep_leds_controller.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Platform : FPGA-generic
-- Standard : VHDL '93
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012 - 2017 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
...
...
modules/wr_endpoint/ep_rtu_header_extract.vhd
View file @
836bccd7
-------------------------------------------------------------------------------
-- Title : RTU header extract
-- Project : White Rabbit
-------------------------------------------------------------------------------
-- File : ep_rtu_header_extract.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Platform : FPGA-generic
-- Standard : VHDL '93
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012 - 2017 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
work
.
endpoint_private_pkg
.
all
;
...
...
modules/wr_endpoint/ep_rx_crc_size_check.vhd
View file @
836bccd7
-------------------------------------------------------------------------------
-- Title : Rx CRC checker
-- Project : White Rabbit
-------------------------------------------------------------------------------
-- File : ep_rx_crc_size_check.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Platform : FPGA-generic
-- Standard : VHDL '93
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011 - 2017 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
...
...
modules/wr_endpoint/ep_rx_early_address_match.vhd
View file @
836bccd7
-------------------------------------------------------------------------------
-- Title : Rx Early Address Match
-- Project : White Rabbit
-------------------------------------------------------------------------------
-- File : ep_rx_early_address_match.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Platform : FPGA-generic
-- Standard : VHDL '93
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011 - 2015 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
...
...
modules/wr_endpoint/ep_rx_oob_insert.vhd
View file @
836bccd7
-------------------------------------------------------------------------------
-- Title : RX OOB inserter
-- Project : White Rabbit
-------------------------------------------------------------------------------
-- File : ep_rx_oob_insert.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Platform : FPGA-generic
-- Standard : VHDL '93
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011 - 2017 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
...
...
modules/wr_endpoint/ep_rx_status_reg_insert.vhd
View file @
836bccd7
-------------------------------------------------------------------------------
-- Title : RX Status Register Inserter
-- Project : White Rabbit
-------------------------------------------------------------------------------
-- File : ep_rx_status_reg_insert.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Platform : FPGA-generic
-- Standard : VHDL '93
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011 - 2017 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
...
...
modules/wr_endpoint/ep_rx_vlan_unit.vhd
View file @
836bccd7
-------------------------------------------------------------------------------
-- Title : RX VLAN unit
-- Project : White Rabbit
-------------------------------------------------------------------------------
-- File : ep_rx_vlan_unit.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Platform : FPGA-generic
-- Standard : VHDL '93
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011-2015 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
...
...
modules/wr_endpoint/ep_rx_wb_master.vhd
View file @
836bccd7
...
...
@@ -13,7 +13,25 @@
-- Description: RX Wishbone Master. Converts the internal fabric (DREQ-VALID
-- throttling) to Pipelined Wishbone (b4)
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011-2017 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
...
...
modules/wr_endpoint/ep_sync_detect.vhd
View file @
836bccd7
...
...
@@ -13,7 +13,25 @@
-- Description: Module implements a link synchronization detect state machine
-- compatible with 802.3x spec.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
...
...
modules/wr_endpoint/ep_sync_detect_16bit.vhd
View file @
836bccd7
...
...
@@ -13,7 +13,25 @@
-- Description: Module implements a link synchronization detect state machine
-- compatible with 802.3x spec.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
...
...
modules/wr_endpoint/ep_timestamping_unit.vhd
View file @
836bccd7
...
...
@@ -20,7 +20,25 @@
-- occur during sampling asynchronous timestamp strobes.
-- Both timestamps are taken using refclk_i.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2009 - 2012 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
...
...
modules/wr_endpoint/ep_ts_counter.vhd
View file @
836bccd7
...
...
@@ -15,7 +15,25 @@
-- rising edge counter. For space reasons only some LSBs of falling edge
-- counter are outputted.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2009 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
...
...
modules/wr_endpoint/ep_tx_framer.vhd
View file @
836bccd7
...
...
@@ -17,7 +17,25 @@
-- - strips 802.1q headers when necessary
-- - decodes TX OOB data and passes it to the timestamping unit
-------------------------------------------------------------------------------
--
-- Copyright (c) 2009 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
...
...
modules/wr_mini_nic/minic_packet_buffer.vhd
View file @
836bccd7
...
...
@@ -13,7 +13,25 @@
-- Description: RAM-based packet buffer for miNIC implementations which don't
-- use the DMA access to the system memory
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
...
...
modules/wr_mini_nic/wr_mini_nic.vhd
View file @
836bccd7
...
...
@@ -16,7 +16,25 @@
-- system memory via simple memory bus. WR endpoint-compatible TX timestamping
-- unit is also included.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010-2016 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
...
...
modules/wr_mini_nic/xwr_mini_nic.vhd
View file @
836bccd7
-------------------------------------------------------------------------------
-- Title : Mini Embedded DMA Network Interface Controller
-- Project : WhiteRabbit Core
-------------------------------------------------------------------------------
-- File : xwrsw_mini_nic.vhd
-- Author : Grzegorz Daniluk, Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-07-26
-- Last update: 2017-02-03
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010-2016 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
...
...
modules/wr_pps_gen/wr_pps_gen.vhd
View file @
836bccd7
...
...
@@ -2,7 +2,7 @@
-- Title : PPS Generator & UTC Realtime clock
-- Project : WhiteRabbit Switch
-------------------------------------------------------------------------------
-- File : wr
sw
_pps_gen.vhd
-- File : wr_pps_gen.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN (BE-CO-HT)
-- Created : 2010-09-02
...
...
@@ -12,7 +12,25 @@
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010-2017 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
...
...
modules/wr_pps_gen/xwr_pps_gen.vhd
View file @
836bccd7
...
...
@@ -12,7 +12,25 @@
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010-2017 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
...
...
modules/wr_softpll_ng/spll_aligner.vhd
View file @
836bccd7
-------------------------------------------------------------------------------
-- Title : White Rabbit Softcore PLL (new generation) - SoftPLL-ng
-- Project : White Rabbit
-------------------------------------------------------------------------------
-- File : spll_aligner.vhd
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012-2017 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
...
...
modules/wr_softpll_ng/spll_bangbang_pd.vhd
View file @
836bccd7
...
...
@@ -16,7 +16,25 @@
-- clk_fbck_i cycles. Divider counters can be synchronized at any moment
-- by pulsing the sync_p_i signal.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
...
...
modules/wr_softpll_ng/spll_period_detect.vhd
View file @
836bccd7
...
...
@@ -18,7 +18,25 @@
-- - positive when clk_fbck_i is slower than selected frequency setpoint
-- - negative when clk_fbck_i is faster than selected frequency setpoint
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
...
...
modules/wr_tbi_phy/wr_tbi_phy.vhd
View file @
836bccd7
...
...
@@ -11,7 +11,25 @@
-- Standard : VHDL
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
...
...
platform/altera/wr_altera_pkg.vhd
View file @
836bccd7
-------------------------------------------------------------------------------
-- Title : Altera-specific components required by WR PTP Core package
-- Project : WR PTP Core
-- URL : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
-------------------------------------------------------------------------------
-- File : wr_altera_pkg.vhd
-- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2016-11-21
-- Last update: 2017-04-27
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Copyright (c) 2016-2017 CERN
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
...
...
platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd
View file @
836bccd7
...
...
@@ -15,9 +15,23 @@
-------------------------------------------------------------------------------
--
-- Original EASE design (c) 2010 NIKHEF / Peter Jansweijer and Henk Peek
-- VHDL port (c) 2010 CERN
/ Tomasz Wlostowski
-- VHDL port (c) 2010 CERN
--
-- <license>
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
...
...
platform/xilinx/wr_gtp_phy/spartan6/gtp_phase_align.vhd
View file @
836bccd7
...
...
@@ -14,9 +14,23 @@
-------------------------------------------------------------------------------
--
-- Original EASE design (c) 2010 NIKHEF / Peter Jansweijer and Henk Peek
-- VHDL port (c) 2010 CERN
/ Tomasz Wlostowski
-- VHDL port (c) 2010 CERN
--
-- <license>
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
...
...
platform/xilinx/wr_gtp_phy/virtex6/gtp_phase_align_virtex6.vhd
View file @
836bccd7
...
...
@@ -14,9 +14,23 @@
-------------------------------------------------------------------------------
--
-- Original EASE design (c) 2010 NIKHEF / Peter Jansweijer and Henk Peek
-- VHDL port (c) 2010 CERN
/ Tomasz Wlostowski
-- VHDL port (c) 2010 CERN
--
-- <license>
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
...
...
platform/xilinx/wr_gtp_phy/virtex6/gtx_reset.vhd
View file @
836bccd7
-------------------------------------------------------------------------------
-- Title : GTX Reset Module
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : gtp_bitslide.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Module implements a manual bitslide alignment state machine and
-- provides the obtained bitslide value to the MAC.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
...
...
platform/xilinx/wr_xilinx_pkg.vhd
View file @
836bccd7
-------------------------------------------------------------------------------
-- Title : Platform-dependent components needed for WR PTP Core on Xilinx
-- Project : WR PTP Core
-- URL : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
-------------------------------------------------------------------------------
-- File : wr_xilinx_pkg.vhd
-- Author : Maciej Lipinski, Grzegorz Daniluk, Dimitrios Lampridis
-- Company : CERN
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
--
-- Copyright (c) 2016-2017 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
...
...
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