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White Rabbit core collection
Commits
8618fc1d
Commit
8618fc1d
authored
Nov 05, 2011
by
Grzegorz Daniluk
Browse files
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Plain Diff
wrcore_v2: importing the newest wr_endpoint (taken from wishbonized branch)
parent
9401beec
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Showing
13 changed files
with
410 additions
and
63 deletions
+410
-63
endpoint_pkg.vhd
modules/wr_endpoint/endpoint_pkg.vhd
+3
-0
ep_pcs_tbi_mdio_wb.vhd
modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd
+1
-1
ep_registers_pkg.vhd
modules/wr_endpoint/ep_registers_pkg.vhd
+17
-3
ep_rx_buffer.vhd
modules/wr_endpoint/ep_rx_buffer.vhd
+103
-23
ep_rx_bypass_queue.vhd
modules/wr_endpoint/ep_rx_bypass_queue.vhd
+2
-2
ep_rx_crc_size_check.vhd
modules/wr_endpoint/ep_rx_crc_size_check.vhd
+3
-2
ep_rx_oob_insert.vhd
modules/wr_endpoint/ep_rx_oob_insert.vhd
+46
-3
ep_rx_path.vhd
modules/wr_endpoint/ep_rx_path.vhd
+4
-1
ep_rx_wb_master.vhd
modules/wr_endpoint/ep_rx_wb_master.vhd
+22
-7
ep_wishbone_controller.vhd
modules/wr_endpoint/ep_wishbone_controller.vhd
+78
-17
ep_wishbone_controller.wb
modules/wr_endpoint/ep_wishbone_controller.wb
+49
-0
wr_endpoint.vhd
modules/wr_endpoint/wr_endpoint.vhd
+77
-3
xwr_endpoint.vhd
modules/wr_endpoint/xwr_endpoint.vhd
+5
-1
No files found.
modules/wr_endpoint/endpoint_pkg.vhd
View file @
8618fc1d
...
...
@@ -24,6 +24,7 @@ package endpoint_pkg is
port
(
clk_ref_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
clk_dmtd_i
:
in
std_logic
:
=
'0'
;
rst_n_i
:
in
std_logic
;
pps_csync_p1_i
:
in
std_logic
:
=
'0'
;
phy_rst_o
:
out
std_logic
;
...
...
@@ -56,6 +57,7 @@ package endpoint_pkg is
src_we_o
:
out
std_logic
;
src_stall_i
:
in
std_logic
;
src_ack_i
:
in
std_logic
;
src_err_i
:
in
std_logic
;
snk_dat_i
:
in
std_logic_vector
(
15
downto
0
);
snk_adr_i
:
in
std_logic_vector
(
1
downto
0
);
snk_sel_i
:
in
std_logic_vector
(
1
downto
0
);
...
...
@@ -110,6 +112,7 @@ package endpoint_pkg is
port
(
clk_ref_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
clk_dmtd_i
:
in
std_logic
:
=
'0'
;
rst_n_i
:
in
std_logic
;
pps_csync_p1_i
:
in
std_logic
:
=
'0'
;
phy_rst_o
:
out
std_logic
;
...
...
modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd
View file @
8618fc1d
...
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ep_pcs_tbi_mdio_wb.vhd
-- Author : auto-generated by wbgen2 from pcs_regs.wb
-- Created :
Wed Oct 26 22:05:09
2011
-- Created :
Sun Nov 6 00:20:16
2011
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pcs_regs.wb
...
...
modules/wr_endpoint/ep_registers_pkg.vhd
View file @
8618fc1d
...
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ep_registers_pkg.vhd
-- Author : auto-generated by wbgen2 from ep_wishbone_controller.wb
-- Created :
Wed Oct 26 22:05:09
2011
-- Created :
Sun Nov 6 00:20:16
2011
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ep_wishbone_controller.wb
...
...
@@ -30,6 +30,8 @@ package ep_wbgen2_pkg is
mdio_asr_ready_i
:
std_logic
;
dsr_lstatus_i
:
std_logic
;
dsr_lact_i
:
std_logic
;
dmsr_ps_val_i
:
std_logic_vector
(
23
downto
0
);
dmsr_ps_rdy_i
:
std_logic
;
end
record
;
constant
c_ep_in_registers_init_value
:
t_ep_in_registers
:
=
(
...
...
@@ -41,7 +43,9 @@ package ep_wbgen2_pkg is
mdio_asr_rdata_i
=>
(
others
=>
'0'
),
mdio_asr_ready_i
=>
'0'
,
dsr_lstatus_i
=>
'0'
,
dsr_lact_i
=>
'0'
dsr_lact_i
=>
'0'
,
dmsr_ps_val_i
=>
(
others
=>
'0'
),
dmsr_ps_rdy_i
=>
'0'
);
-- Output registers (WB slave -> user design)
...
...
@@ -90,6 +94,10 @@ package ep_wbgen2_pkg is
mdio_asr_phyad_o
:
std_logic_vector
(
7
downto
0
);
dsr_lact_o
:
std_logic
;
dsr_lact_load_o
:
std_logic
;
dmcr_en_o
:
std_logic
;
dmcr_n_avg_o
:
std_logic_vector
(
11
downto
0
);
dmsr_ps_rdy_o
:
std_logic
;
dmsr_ps_rdy_load_o
:
std_logic
;
end
record
;
constant
c_ep_out_registers_init_value
:
t_ep_out_registers
:
=
(
...
...
@@ -135,7 +143,11 @@ package ep_wbgen2_pkg is
mdio_cr_rw_o
=>
'0'
,
mdio_asr_phyad_o
=>
(
others
=>
'0'
),
dsr_lact_o
=>
'0'
,
dsr_lact_load_o
=>
'0'
dsr_lact_load_o
=>
'0'
,
dmcr_en_o
=>
'0'
,
dmcr_n_avg_o
=>
(
others
=>
'0'
),
dmsr_ps_rdy_o
=>
'0'
,
dmsr_ps_rdy_load_o
=>
'0'
);
function
"or"
(
left
,
right
:
t_ep_in_registers
)
return
t_ep_in_registers
;
function
f_x_to_zero
(
x
:
std_logic
)
return
std_logic
;
...
...
@@ -162,6 +174,8 @@ tmp.mdio_asr_rdata_i := left.mdio_asr_rdata_i or right.mdio_asr_rdata_i;
tmp
.
mdio_asr_ready_i
:
=
left
.
mdio_asr_ready_i
or
right
.
mdio_asr_ready_i
;
tmp
.
dsr_lstatus_i
:
=
left
.
dsr_lstatus_i
or
right
.
dsr_lstatus_i
;
tmp
.
dsr_lact_i
:
=
left
.
dsr_lact_i
or
right
.
dsr_lact_i
;
tmp
.
dmsr_ps_val_i
:
=
left
.
dmsr_ps_val_i
or
right
.
dmsr_ps_val_i
;
tmp
.
dmsr_ps_rdy_i
:
=
left
.
dmsr_ps_rdy_i
or
right
.
dmsr_ps_rdy_i
;
return
tmp
;
end
function
;
end
package
body
;
modules/wr_endpoint/ep_rx_buffer.vhd
View file @
8618fc1d
...
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-11-18
-- Last update: 2011-10-2
6
-- Last update: 2011-10-2
9
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
...
...
@@ -84,7 +84,7 @@ architecture behavioral of ep_rx_buffer is
dout
(
15
)
<=
fab
.
sof
;
dout
(
14
)
<=
fab
.
eof
;
dout
(
13
)
<=
fab
.
error
;
dout
(
12
downto
0
)
<=
(
others
=>
'
X
'
);
dout
(
12
downto
0
)
<=
(
others
=>
'
0
'
);
dout_valid
<=
'1'
;
elsif
(
fab
.
dvalid
=
'1'
)
then
...
...
@@ -97,7 +97,7 @@ architecture behavioral of ep_rx_buffer is
dout
(
15
downto
0
)
<=
fab
.
data
;
dout_valid
<=
'1'
;
else
dout
(
17
downto
0
)
<=
(
others
=>
'
X
'
);
dout
(
17
downto
0
)
<=
(
others
=>
'
0
'
);
dout_valid
<=
'0'
;
end
if
;
...
...
@@ -118,14 +118,14 @@ architecture behavioral of ep_rx_buffer is
if
(
din
(
17
downto
16
)
=
"10"
)
then
-- some fancy encoding is necessary here
case
cur_addr
(
1
downto
0
)
is
when
c_WRF_DATA
=>
fab
.
addr
<=
c_WRF_OOB
;
fab
.
addr
<=
c_WRF_OOB
after
1
ns
;
when
c_WRF_STATUS
=>
fab
.
addr
<=
c_WRF_DATA
;
when
others
=>
fab
.
addr
<=
"XX"
;
fab
.
addr
<=
c_WRF_DATA
after
1
ns
;
when
others
=>
fab
.
addr
<=
c_WRF_DATA
after
1
ns
;
end
case
;
else
fab
.
addr
<=
cur_addr
;
fab
.
addr
<=
cur_addr
after
1
ns
;
end
if
;
fab
.
dvalid
<=
not
din
(
17
)
or
(
din
(
17
)
and
not
din
(
16
));
...
...
@@ -135,14 +135,13 @@ architecture behavioral of ep_rx_buffer is
fab
.
bytesel
<=
not
din
(
17
)
and
din
(
16
);
else
fab
.
bytesel
<=
'X'
;
fab
.
addr
<=
(
others
=>
'X'
);
fab
.
dvalid
<=
'0'
;
fab
.
sof
<=
'0'
;
fab
.
eof
<=
'0'
;
fab
.
error
<=
'0'
;
fab
.
addr
<=
(
others
=>
'X'
);
fab
.
data
<=
(
others
=>
'X'
);
fab
.
bytesel
<=
'0'
;
fab
.
addr
<=
cur_addr
after
1
ns
;
fab
.
dvalid
<=
'0'
;
fab
.
sof
<=
'0'
;
fab
.
eof
<=
'0'
;
fab
.
error
<=
'0'
;
fab
.
data
<=
(
others
=>
'0'
);
end
if
;
end
f_unpack_rbuf_contents
;
...
...
@@ -164,7 +163,78 @@ architecture behavioral of ep_rx_buffer is
signal
in_prev_addr
:
std_logic_vector
(
1
downto
0
);
signal
out_cur_addr
:
std_logic_vector
(
1
downto
0
);
component
chipscope_ila
port
(
CONTROL
:
inout
std_logic_vector
(
35
downto
0
);
CLK
:
in
std_logic
;
TRIG0
:
in
std_logic_vector
(
31
downto
0
);
TRIG1
:
in
std_logic_vector
(
31
downto
0
);
TRIG2
:
in
std_logic_vector
(
31
downto
0
);
TRIG3
:
in
std_logic_vector
(
31
downto
0
));
end
component
;
component
chipscope_icon
port
(
CONTROL0
:
inout
std_logic_vector
(
35
downto
0
));
end
component
;
signal
CONTROL
:
std_logic_vector
(
35
downto
0
);
signal
CLK
:
std_logic
;
signal
TRIG0
:
std_logic_vector
(
31
downto
0
);
signal
TRIG1
:
std_logic_vector
(
31
downto
0
);
signal
TRIG2
:
std_logic_vector
(
31
downto
0
);
signal
TRIG3
:
std_logic_vector
(
31
downto
0
);
signal
crappify
:
unsigned
(
10
downto
0
);
begin
--chipscope_ila_1 : chipscope_ila
-- port map (
-- CONTROL => CONTROL,
-- CLK => clk_sys_i,
-- TRIG0 => TRIG0,
-- TRIG1 => TRIG1,
-- TRIG2 => TRIG2,
-- TRIG3 => TRIG3);
--chipscope_icon_1 : chipscope_icon
-- port map (
-- CONTROL0 => CONTROL);
TRIG0
(
15
downto
0
)
<=
snk_fab_i
.
data
;
trig0
(
16
)
<=
snk_fab_i
.
sof
;
trig0
(
17
)
<=
snk_fab_i
.
eof
;
trig0
(
18
)
<=
snk_fab_i
.
error
;
trig0
(
19
)
<=
snk_fab_i
.
bytesel
;
trig0
(
20
)
<=
snk_fab_i
.
has_rx_timestamp
;
trig0
(
21
)
<=
snk_fab_i
.
dvalid
;
trig0
(
24
downto
23
)
<=
snk_fab_i
.
addr
;
TRIG1
(
15
downto
0
)
<=
src_fab_int
.
data
;
trig1
(
16
)
<=
src_fab_int
.
sof
;
trig1
(
17
)
<=
src_fab_int
.
eof
;
trig1
(
18
)
<=
src_fab_int
.
error
;
trig1
(
19
)
<=
src_fab_int
.
bytesel
;
trig1
(
20
)
<=
src_fab_int
.
has_rx_timestamp
;
trig1
(
21
)
<=
src_fab_int
.
dvalid
;
trig1
(
24
downto
23
)
<=
src_fab_int
.
addr
;
trig2
(
17
downto
0
)
<=
q_in
;
trig2
(
18
)
<=
q_in_valid
;
trig3
(
17
downto
0
)
<=
q_out
;
trig3
(
18
)
<=
q_empty
;
trig3
(
19
)
<=
q_wr
;
trig3
(
20
)
<=
q_rd
;
trig3
(
21
)
<=
q_drop
;
trig3
(
22
)
<=
q_in_valid
;
trig3
(
23
)
<=
q_out_valid
;
trig3
(
25
downto
24
)
<=
in_prev_addr
;
trig3
(
27
downto
26
)
<=
out_cur_addr
;
p_fifo_write
:
process
(
clk_sys_i
)
begin
...
...
@@ -191,6 +261,7 @@ begin
case
state
is
when
WAIT_FRAME
=>
in_prev_addr
<=
c_WRF_STATUS
;
if
(
snk_fab_i
.
sof
=
'1'
and
q_drop
=
'0'
)
then
state
<=
DATA
;
end
if
;
...
...
@@ -206,7 +277,10 @@ begin
end
if
;
end
process
;
f_pack_rbuf_contents
(
fab_to_encode
,
in_prev_addr
,
q_in
,
q_in_valid
);
p_pack_rbuf
:
process
(
fab_to_encode
,
in_prev_addr
)
begin
f_pack_rbuf_contents
(
fab_to_encode
,
in_prev_addr
,
q_in
,
q_in_valid
);
end
process
;
p_encode_fifo_in
:
process
(
snk_fab_i
,
state
,
q_drop
)
...
...
@@ -227,7 +301,7 @@ begin
fab_to_encode
<=
fab_pre_encode
;
end
process
;
q_reset
<=
rst_n_i
or
regs_i
.
ecr_rx_en_o
;
q_reset
<=
rst_n_i
and
regs_i
.
ecr_rx_en_o
;
BUF_FIFO
:
generic_sync_fifo
generic
map
(
...
...
@@ -247,26 +321,32 @@ begin
almost_full_o
=>
open
,
count_o
=>
q_usedw
);
q_rd
<=
(
not
q_empty
)
and
src_dreq_i
;
rd_valid_gen
:
process
(
clk_sys_i
,
rst_n_i
)
q_rd
<=
(
not
q_empty
)
and
src_dreq_i
;
rd_valid_gen
:
process
(
clk_sys_i
)
begin
if
rising_edge
(
clk_sys_i
)
then
if
(
rst_n_i
=
'0'
)
then
q_out_valid
<=
'0'
;
out_cur_addr
<=
c_WRF_STATUS
;
else
q_out_valid
<=
q_rd
;
if
(
src_fab_int
.
sof
=
'1'
)
then
if
(
src_fab_int
.
sof
=
'1'
or
src_fab_int
.
eof
=
'1'
or
src_fab_int
.
error
=
'1'
)
then
out_cur_addr
<=
c_WRF_STATUS
;
end
if
;
if
(
src_fab_int
.
dvalid
=
'1'
)
then
else
out_cur_addr
<=
src_fab_int
.
addr
;
end
if
;
end
if
;
end
if
;
end
process
;
f_unpack_rbuf_contents
(
q_out
,
out_cur_addr
,
q_out_valid
,
src_fab_int
);
p_unpack
:
process
(
q_out
,
out_cur_addr
,
q_out_valid
)
begin
f_unpack_rbuf_contents
(
q_out
,
out_cur_addr
,
q_out_valid
,
src_fab_int
);
end
process
;
src_fab_o
<=
src_fab_int
;
snk_dreq_o
<=
'1'
;
...
...
modules/wr_endpoint/ep_rx_bypass_queue.vhd
View file @
8618fc1d
...
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-08-10
-- Last update: 2011-10-2
5
-- Last update: 2011-10-2
9
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
...
...
@@ -147,7 +147,7 @@ begin -- behavioral
end
if
;
end
process
;
dreq_o
<=
dreq_i
and
not
flushing
;
dreq_o
<=
dreq_i
and
not
(
flush_i
or
flushing
)
;
valid_int
<=
(
qfull
and
valid_i
)
or
(
not
qempty
and
flushing
and
valid_mask
);
valid_o
<=
valid_int
;
...
...
modules/wr_endpoint/ep_rx_crc_size_check.vhd
View file @
8618fc1d
...
...
@@ -68,7 +68,7 @@ architecture behavioral of ep_rx_crc_size_check is
signal
q_bytesel
:
std_logic
;
signal
q_dvalid_in
:
std_logic
;
signal
q_dvalid_out
:
std_logic
;
signal
q_dreq_out
:
std_logic
;
signal
dvalid_mask
:
std_logic_vector
(
1
downto
0
);
begin
-- behavioral
...
...
@@ -107,7 +107,7 @@ begin -- behavioral
clk_i
=>
clk_sys_i
,
d_i
=>
q_in
,
valid_i
=>
q_dvalid_in
,
dreq_o
=>
snk_dreq_o
,
dreq_o
=>
q_dreq_out
,
q_o
=>
q_out
,
valid_o
=>
q_dvalid_out
,
dreq_i
=>
src_dreq_i
,
...
...
@@ -115,6 +115,7 @@ begin -- behavioral
purge_i
=>
q_purge
,
empty_o
=>
q_empty
);
snk_dreq_o
<=
q_dreq_out
and
not
(
snk_fab_i
.
eof
or
snk_fab_i
.
error
);
p_count_bytes
:
process
(
clk_sys_i
,
rst_n_i
)
...
...
modules/wr_endpoint/ep_rx_oob_insert.vhd
View file @
8618fc1d
...
...
@@ -30,9 +30,52 @@ architecture behavioral of ep_rx_oob_insert is
signal
state
:
t_state
;
signal
src_dreq_d0
:
std_logic
;
component
chipscope_ila
port
(
CONTROL
:
inout
std_logic_vector
(
35
downto
0
);
CLK
:
in
std_logic
;
TRIG0
:
in
std_logic_vector
(
31
downto
0
);
TRIG1
:
in
std_logic_vector
(
31
downto
0
);
TRIG2
:
in
std_logic_vector
(
31
downto
0
);
TRIG3
:
in
std_logic_vector
(
31
downto
0
));
end
component
;
component
chipscope_icon
port
(
CONTROL0
:
inout
std_logic_vector
(
35
downto
0
));
end
component
;
begin
signal
CONTROL
:
std_logic_vector
(
35
downto
0
);
signal
CLK
:
std_logic
;
signal
TRIG0
:
std_logic_vector
(
31
downto
0
);
signal
TRIG1
:
std_logic_vector
(
31
downto
0
);
signal
TRIG2
:
std_logic_vector
(
31
downto
0
);
signal
TRIG3
:
std_logic_vector
(
31
downto
0
);
begin
--chipscope_ila_1 : chipscope_ila
-- port map (
-- CONTROL => CONTROL,
-- CLK => clk_sys_i,
-- TRIG0 => TRIG0,
-- TRIG1 => TRIG1,
-- TRIG2 => TRIG2,
-- TRIG3 => TRIG3);
--chipscope_icon_1 : chipscope_icon
-- port map (
-- CONTROL0 => CONTROL);
TRIG0
(
15
downto
0
)
<=
snk_fab_i
.
data
;
trig0
(
16
)
<=
snk_fab_i
.
sof
;
trig0
(
17
)
<=
snk_fab_i
.
eof
;
trig0
(
18
)
<=
snk_fab_i
.
error
;
trig0
(
19
)
<=
snk_fab_i
.
bytesel
;
trig0
(
20
)
<=
snk_fab_i
.
has_rx_timestamp
;
trig0
(
21
)
<=
snk_fab_i
.
dvalid
;
trig0
(
22
)
<=
'1'
when
state
=
WAIT_OOB
else
'0'
;
trig0
(
24
downto
23
)
<=
snk_fab_i
.
addr
;
snk_dreq_o
<=
src_dreq_i
;
src_fab_o
.
sof
<=
snk_fab_i
.
sof
;
...
...
@@ -40,7 +83,7 @@ begin
src_fab_o
.
error
<=
snk_fab_i
.
error
;
src_fab_o
.
bytesel
<=
snk_fab_i
.
bytesel
;
p_comb_src
:
process
(
state
,
snk_fab_i
,
src_dreq_i
)
p_comb_src
:
process
(
state
,
snk_fab_i
,
src_dreq_i
,
regs_i
)
begin
if
(
snk_fab_i
.
has_rx_timestamp
=
'1'
)
then
...
...
@@ -65,7 +108,7 @@ begin
state
<=
WAIT_OOB
;
else
if
(
snk_fab_i
.
error
=
'1'
)
then
if
(
snk_fab_i
.
error
=
'1'
or
snk_fab_i
.
sof
=
'1'
)
then
state
<=
WAIT_OOB
;
else
...
...
modules/wr_endpoint/ep_rx_path.vhd
View file @
8618fc1d
...
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2009-06-22
-- Last update: 2011-10-2
7
-- Last update: 2011-10-2
9
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
...
...
@@ -320,6 +320,9 @@ begin -- behavioral
gen_without_packet_filter
:
if
(
not
g_with_dpi_classifier
)
generate
fab_pipe
(
2
)
<=
fab_pipe
(
1
);
pfilter_drop
<=
'0'
;
pfilter_done
<=
'1'
;
pfilter_pclass
<=
(
others
=>
'0'
);
end
generate
gen_without_packet_filter
;
...
...
modules/wr_endpoint/ep_rx_wb_master.vhd
View file @
8618fc1d
...
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2009-06-22
-- Last update: 2011-10-
27
-- Last update: 2011-10-
30
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
...
...
@@ -30,6 +30,8 @@ use work.endpoint_private_pkg.all;
use
work
.
wr_fabric_pkg
.
all
;
entity
ep_rx_wb_master
is
generic
(
g_ignore_ack
:
boolean
:
=
true
);
port
(
clk_sys_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
...
...
@@ -59,7 +61,7 @@ architecture behavioral of ep_rx_wb_master is
begin
-- behavioral
snk_dreq_o
<=
'1'
when
(
src_wb_i
.
stall
=
'0'
and
state
/=
FINISH_CYCLE
and
snk_fab_i
.
eof
=
'0'
and
snk_fab_i
.
error
=
'0'
)
else
'0'
;
snk_dreq_o
<=
'1'
when
(
src_wb_i
.
stall
=
'0'
and
state
/=
FINISH_CYCLE
and
snk_fab_i
.
eof
=
'0'
and
snk_fab_i
.
error
=
'0'
and
snk_fab_i
.
sof
=
'0'
)
else
'0'
;
p_count_acks
:
process
(
clk_sys_i
)
begin
...
...
@@ -92,8 +94,9 @@ begin -- behavioral
case
state
is
when
IDLE
=>
src_out_int
.
adr
<=
snk_fab_i
.
addr
;
src_out_int
.
dat
<=
snk_fab_i
.
data
;
if
(
s
rc_wb_i
.
stall
=
'0'
and
snk_fab_i
.
sof
=
'1
'
)
then
if
(
s
nk_fab_i
.
sof
=
'1'
and
src_wb_i
.
err
=
'0
'
)
then
src_out_int
.
cyc
<=
'1'
;
state
<=
DATA
;
end
if
;
...
...
@@ -108,7 +111,11 @@ begin -- behavioral
end
if
;
if
(
snk_fab_i
.
error
=
'1'
)
then
if
(
src_wb_i
.
err
=
'1'
)
then
state
<=
IDLE
;
src_out_int
.
cyc
<=
'0'
;
src_out_int
.
stb
<=
'0'
;
elsif
(
snk_fab_i
.
error
=
'1'
)
then
state
<=
THROW_ERROR
;
elsif
(
src_wb_i
.
stall
=
'1'
and
snk_fab_i
.
dvalid
=
'1'
)
then
state
<=
FLUSH_STALL
;
...
...
@@ -125,7 +132,11 @@ begin -- behavioral
tmp_sel
<=
snk_fab_i
.
bytesel
;
when
FLUSH_STALL
=>
if
(
src_wb_i
.
stall
=
'0'
)
then
if
(
src_wb_i
.
err
=
'1'
)
then
state
<=
IDLE
;
src_out_int
.
cyc
<=
'0'
;
src_out_int
.
stb
<=
'0'
;
elsif
(
src_wb_i
.
stall
=
'0'
)
then
src_out_int
.
dat
<=
tmp_dat
;
src_out_int
.
adr
<=
tmp_adr
;
src_out_int
.
stb
<=
'1'
;
...
...
@@ -135,7 +146,11 @@ begin -- behavioral
end
if
;
when
THROW_ERROR
=>
if
(
src_wb_i
.
stall
=
'0'
)
then
if
(
src_wb_i
.
err
=
'1'
)
then
state
<=
IDLE
;
src_out_int
.
cyc
<=
'0'
;
src_out_int
.
stb
<=
'0'
;
elsif
(
src_wb_i
.
stall
=
'0'
)
then
stat
.
error
:
=
'1'
;
src_out_int
.
adr
<=
c_WRF_STATUS
;
src_out_int
.
dat
<=
f_marshall_wrf_status
(
stat
);
...
...
@@ -149,7 +164,7 @@ begin -- behavioral
src_out_int
.
stb
<=
'0'
;
end
if
;
if
(
ack_count
=
0
and
src_out_int
.
stb
=
'0'
)
then
if
(
((
ack_count
=
0
)
or
g_ignore_ack
)
and
src_out_int
.
stb
=
'0'
)
then
src_out_int
.
cyc
<=
'0'
;
state
<=
IDLE
;
end
if
;
...
...
modules/wr_endpoint/ep_wishbone_controller.vhd
View file @
8618fc1d
...
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ep_wishbone_controller.vhd
-- Author : auto-generated by wbgen2 from ep_wishbone_controller.wb
-- Created :
Wed Oct 26 22:05:09
2011
-- Created :
Sun Nov 6 00:20:16
2011
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ep_wishbone_controller.wb
...
...
@@ -84,6 +84,8 @@ signal ep_macl_int : std_logic_vector(31 downto 0);
signal
ep_mdio_cr_addr_int
:
std_logic_vector
(
7
downto
0
);
signal
ep_mdio_cr_rw_int
:
std_logic
;
signal
ep_mdio_asr_phyad_int
:
std_logic_vector
(
7
downto
0
);
signal
ep_dmcr_en_int
:
std_logic
;
signal
ep_dmcr_n_avg_int
:
std_logic_vector
(
11
downto
0
);
signal
ep_rmon_ram_rddata_int
:
std_logic_vector
(
31
downto
0
);
signal
ep_rmon_ram_rd_int
:
std_logic
;
signal
ep_rmon_ram_wr_int
:
std_logic
;
...
...
@@ -153,6 +155,9 @@ begin
ep_mdio_cr_rw_int
<=
'0'
;
ep_mdio_asr_phyad_int
<=
"00000000"
;
regs_o
.
dsr_lact_load_o
<=
'0'
;
ep_dmcr_en_int
<=
'0'
;
ep_dmcr_n_avg_int
<=
"000000000000"
;
regs_o
.
dmsr_ps_rdy_load_o
<=
'0'
;
elsif
rising_edge
(
bus_clock_int
)
then
-- advance the ACK generator shift register
ack_sreg
(
8
downto
0
)
<=
ack_sreg
(
9
downto
1
);
...
...
@@ -167,6 +172,7 @@ begin
regs_o
.
pfcr0_mm_data_msb_wr_o
<=
'0'
;
regs_o
.
mdio_cr_data_wr_o
<=
'0'
;
regs_o
.
dsr_lact_load_o
<=
'0'
;
regs_o
.
dmsr_ps_rdy_load_o
<=
'0'
;
ack_in_progress
<=
'0'
;
else
ep_tscr_cs_start_int
<=
ep_tscr_cs_start_int_delay
;
...
...
@@ -178,13 +184,14 @@ begin
regs_o
.
pfcr0_mm_data_msb_wr_o
<=
'0'
;
regs_o
.
mdio_cr_data_wr_o
<=
'0'
;
regs_o
.
dsr_lact_load_o
<=
'0'
;
regs_o
.
dmsr_ps_rdy_load_o
<=
'0'
;
end
if
;
else
if
((
wb_cyc_i
=
'1'
)
and
(
wb_stb_i
=
'1'
))
then
case
rwaddr_reg
(
5
)
is
when
'0'
=>
case
rwaddr_reg
(
3
downto
0
)
is
when
"0000"
=>
case
rwaddr_reg
(
4
downto
0
)
is
when
"0000
0
"
=>
if
(
wb_we_i
=
'1'
)
then
ep_ecr_portid_int
<=
wrdata_reg
(
4
downto
0
);
ep_ecr_rst_cnt_int
<=
wrdata_reg
(
5
);
...
...
@@ -229,7 +236,7 @@ begin
end
if
;
ack_sreg
(
2
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"0001"
=>
when
"000
0
1"
=>
if
(
wb_we_i
=
'1'
)
then
rddata_reg
(
0
)
<=
'X'
;
ep_tscr_en_txts_int
<=
wrdata_reg
(
0
);
...
...
@@ -275,7 +282,7 @@ begin
end
if
;
ack_sreg
(
4
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"0010"
=>
when
"00
0
10"
=>
if
(
wb_we_i
=
'1'
)
then
rddata_reg
(
0
)
<=
'X'
;
ep_rfcr_a_runt_int
<=
wrdata_reg
(
0
);
...
...
@@ -303,7 +310,7 @@ begin
end
if
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"0011"
=>
when
"00
0
11"
=>
if
(
wb_we_i
=
'1'
)
then
ep_vcr0_qmode_int
<=
wrdata_reg
(
1
downto
0
);
rddata_reg
(
2
)
<=
'X'
;
...
...
@@ -332,7 +339,7 @@ begin
end
if
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"0100"
=>
when
"0
0
100"
=>
if
(
wb_we_i
=
'1'
)
then
regs_o
.
vcr1_vid_wr_o
<=
'1'
;
regs_o
.
vcr1_value_wr_o
<=
'1'
;
...
...
@@ -372,7 +379,7 @@ begin
end
if
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"0101"
=>
when
"0
0
101"
=>
if
(
wb_we_i
=
'1'
)
then
regs_o
.
pfcr0_mm_addr_wr_o
<=
'1'
;
regs_o
.
pfcr0_mm_write_wr_o
<=
'1'
;
...
...
@@ -415,7 +422,7 @@ begin
end
if
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"0110"
=>
when
"0
0
110"
=>
if
(
wb_we_i
=
'1'
)
then
ep_pfcr1_mm_data_lsb_int
<=
wrdata_reg
(
11
downto
0
);
else
...
...
@@ -443,7 +450,7 @@ begin
end
if
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"0111"
=>
when
"0
0
111"
=>
if
(
wb_we_i
=
'1'
)
then
ep_tcar_pcp_map_int
<=
wrdata_reg
(
23
downto
0
);
else
...
...
@@ -459,7 +466,7 @@ begin
end
if
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"1000"
=>
when
"
0
1000"
=>
if
(
wb_we_i
=
'1'
)
then
rddata_reg
(
0
)
<=
'X'
;
ep_fcr_rxpause_int
<=
wrdata_reg
(
0
);
...
...
@@ -481,7 +488,7 @@ begin
end
if
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"1001"
=>
when
"
0
1001"
=>
if
(
wb_we_i
=
'1'
)
then
ep_mach_int
<=
wrdata_reg
(
15
downto
0
);
else
...
...
@@ -505,7 +512,7 @@ begin
end
if
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"1010"
=>
when
"
0
1010"
=>
if
(
wb_we_i
=
'1'
)
then
ep_macl_int
<=
wrdata_reg
(
31
downto
0
);
else
...
...
@@ -513,7 +520,7 @@ begin
end
if
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"1011"
=>
when
"
0
1011"
=>
if
(
wb_we_i
=
'1'
)
then
regs_o
.
mdio_cr_data_wr_o
<=
'1'
;
ep_mdio_cr_addr_int
<=
wrdata_reg
(
23
downto
16
);
...
...
@@ -548,7 +555,7 @@ begin
end
if
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"1100"
=>
when
"
0
1100"
=>
if
(
wb_we_i
=
'1'
)
then
ep_mdio_asr_phyad_int
<=
wrdata_reg
(
23
downto
16
);
rddata_reg
(
31
)
<=
'X'
;
...
...
@@ -566,14 +573,14 @@ begin
end
if
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"1101"
=>
when
"
0
1101"
=>
if
(
wb_we_i
=
'1'
)
then
else
rddata_reg
(
31
downto
0
)
<=
"11001010111111101011101010111110"
;
end
if
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"1110"
=>
when
"
0
1110"
=>
if
(
wb_we_i
=
'1'
)
then
rddata_reg
(
0
)
<=
'X'
;
rddata_reg
(
1
)
<=
'X'
;
...
...
@@ -614,6 +621,53 @@ begin
end
if
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"01111"
=>
if
(
wb_we_i
=
'1'
)
then
rddata_reg
(
0
)
<=
'X'
;
ep_dmcr_en_int
<=
wrdata_reg
(
0
);
ep_dmcr_n_avg_int
<=
wrdata_reg
(
27
downto
16
);
else
rddata_reg
(
0
)
<=
ep_dmcr_en_int
;
rddata_reg
(
27
downto
16
)
<=
ep_dmcr_n_avg_int
;
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
end
if
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"10000"
=>
if
(
wb_we_i
=
'1'
)
then
rddata_reg
(
24
)
<=
'X'
;
regs_o
.
dmsr_ps_rdy_load_o
<=
'1'
;
else
rddata_reg
(
23
downto
0
)
<=
regs_i
.
dmsr_ps_val_i
;
rddata_reg
(
24
)
<=
regs_i
.
dmsr_ps_rdy_i
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
end
if
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
others
=>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress
<=
'1'
;
...
...
@@ -787,6 +841,13 @@ begin
-- Link status
-- Link activity
regs_o
.
dsr_lact_o
<=
wrdata_reg
(
1
);
-- DMTD Phase measurement enable
regs_o
.
dmcr_en_o
<=
ep_dmcr_en_int
;
-- DMTD averaging samples
regs_o
.
dmcr_n_avg_o
<=
ep_dmcr_n_avg_int
;
-- DMTD Phase shift value
-- DMTD Phase shift value ready
regs_o
.
dmsr_ps_rdy_o
<=
wrdata_reg
(
24
);
-- extra code for reg/fifo/mem: Event counters memory
-- RAM block instantiation for memory: Event counters memory
ep_rmon_ram_raminst
:
wbgen2_dpssram
...
...
modules/wr_endpoint/ep_wishbone_controller.wb
View file @
8618fc1d
...
...
@@ -585,6 +585,55 @@ peripheral {
};
};
reg {
name = "DMTD Control Register";
prefix = "DMCR";
field {
name = "DMTD Phase measurement enable";
description = "1: enables DMTD phase measurement";
type = BIT;
prefix = "EN";
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
field {
name = "DMTD averaging samples";
description = "Number of raw DMTD phase samples averaged in every measurement cycle";
prefix = "N_AVG";
type = SLV;
size = 12;
align = 16;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
};
reg {
name = "DMTD Status register";
prefix = "DMSR";
field {
name = "DMTD Phase shift value";
prefix = "PS_VAL";
size = 24;
type = SLV;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "DMTD Phase shift value ready";
prefix = "PS_RDY";
type = BIT;
load = LOAD_EXT;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
};
};
ram {
name = "Event counters memory";
description = "RMON event counters:\
...
...
modules/wr_endpoint/wr_endpoint.vhd
View file @
8618fc1d
...
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-04-26
-- Last update: 2011-10-
25
-- Last update: 2011-10-
30
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
...
...
@@ -67,7 +67,9 @@ entity wr_endpoint is
-- reference clock / 2 (62.5 MHz, in-phase with refclk)
clk_sys_i
:
in
std_logic
;
--
clk_dmtd_i
:
in
std_logic
;
-- sync reset (clk_sys_i domain), active LO
rst_n_i
:
in
std_logic
;
...
...
@@ -121,6 +123,7 @@ entity wr_endpoint is
src_we_o
:
out
std_logic
;
src_stall_i
:
in
std_logic
;
src_ack_i
:
in
std_logic
;
src_err_i
:
in
std_logic
;
snk_dat_i
:
in
std_logic_vector
(
15
downto
0
);
snk_adr_i
:
in
std_logic_vector
(
1
downto
0
);
...
...
@@ -212,6 +215,23 @@ architecture syn of wr_endpoint is
constant
c_zeros
:
std_logic_vector
(
63
downto
0
)
:
=
(
others
=>
'0'
);
constant
c_ones
:
std_logic_vector
(
63
downto
0
)
:
=
(
others
=>
'0'
);
-------------------------------------------------------------------------------
component
dmtd_phase_meas
generic
(
g_deglitcher_threshold
:
integer
;
g_counter_bits
:
integer
);
port
(
rst_n_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
clk_a_i
:
in
std_logic
;
clk_b_i
:
in
std_logic
;
clk_dmtd_i
:
in
std_logic
;
en_i
:
in
std_logic
;
navg_i
:
in
std_logic_vector
(
11
downto
0
);
phase_meas_o
:
out
std_logic_vector
(
31
downto
0
);
phase_meas_p_o
:
out
std_logic
);
end
component
;
component
ep_tx_framer
generic
(
g_with_vlans
:
boolean
;
...
...
@@ -441,6 +461,11 @@ architecture syn of wr_endpoint is
signal
wb_out
:
t_wishbone_slave_out
;
signal
extended_ADDR
:
std_logic_vector
(
c_wishbone_address_width
-1
downto
0
);
signal
phase_meas
:
std_logic_vector
(
31
downto
0
);
signal
phase_meas_p
:
std_logic
;
signal
validity_cntr
:
unsigned
(
1
downto
0
);
begin
...
...
@@ -605,7 +630,7 @@ begin
src_we_o
<=
src_out
.
we
;
src_in
.
stall
<=
src_stall_i
;
src_in
.
ack
<=
src_ack_i
;
src_in
.
err
<=
src_err_i
;
---------------------------------------------------------------------------------
---- RX buffer
---------------------------------------------------------------------------------
...
...
@@ -799,6 +824,55 @@ begin
end
if
;
end
process
;
-------------------------------------------------------------------------------
-- DMTD phase meter
------------------------------------------------------------------------------
U_DMTD
:
dmtd_phase_meas
generic
map
(
g_counter_bits
=>
14
,
g_deglitcher_threshold
=>
1000
)
port
map
(
clk_sys_i
=>
clk_sys_i
,
clk_a_i
=>
phy_ref_clk_i
,
clk_b_i
=>
phy_rx_clk_i
,
clk_dmtd_i
=>
clk_dmtd_i
,
rst_n_i
=>
rst_n_i
,
en_i
=>
regs_fromwb
.
dmcr_en_o
,
navg_i
=>
regs_fromwb
.
dmcr_n_avg_o
,
phase_meas_o
=>
phase_meas
,
phase_meas_p_o
=>
phase_meas_p
);
p_dmtd_update
:
process
(
clk_sys_i
)
begin
if
rising_edge
(
clk_sys_i
)
then
if
rst_n_i
=
'0'
then
validity_cntr
<=
(
others
=>
'0'
);
regs_towb_ep
.
dmsr_ps_rdy_i
<=
'0'
;
else
if
(
regs_fromwb
.
dmcr_en_o
=
'0'
)
then
validity_cntr
<=
(
others
=>
'0'
);
regs_towb_ep
.
dmsr_ps_rdy_i
<=
'0'
;
elsif
(
regs_fromwb
.
dmsr_ps_rdy_o
=
'1'
and
regs_fromwb
.
dmsr_ps_rdy_load_o
=
'1'
)
then
regs_towb_ep
.
dmsr_ps_rdy_i
<=
'0'
;
elsif
(
phase_meas_p
=
'1'
)
then
if
(
validity_cntr
=
"11"
)
then
regs_towb_ep
.
dmsr_ps_rdy_i
<=
'1'
;
regs_towb_ep
.
dmsr_ps_val_i
<=
phase_meas
(
23
downto
0
);
-- discard few
else
regs_towb_ep
.
dmsr_ps_rdy_i
<=
'0'
;
validity_cntr
<=
validity_cntr
+
1
;
end
if
;
end
if
;
end
if
;
end
if
;
end
process
;
end
syn
;
...
...
modules/wr_endpoint/xwr_endpoint.vhd
View file @
8618fc1d
...
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-04-26
-- Last update: 2011-10-
18
-- Last update: 2011-10-
30
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
...
...
@@ -54,6 +54,8 @@ entity xwr_endpoint is
-- reference clock / 2 (62.5 MHz, in-phase with refclk)
clk_sys_i
:
in
std_logic
;
clk_dmtd_i
:
in
std_logic
;
-- sync reset (clk_sys_i domain), active LO
rst_n_i
:
in
std_logic
;
...
...
@@ -194,6 +196,7 @@ begin
port
map
(
clk_ref_i
=>
clk_ref_i
,
clk_sys_i
=>
clk_sys_i
,
clk_dmtd_i
=>
clk_dmtd_i
,
rst_n_i
=>
rst_n_i
,
pps_csync_p1_i
=>
pps_csync_p1_i
,
phy_rst_o
=>
phy_rst_o
,
...
...
@@ -226,6 +229,7 @@ begin
src_we_o
=>
src_o
.
we
,
src_stall_i
=>
src_i
.
stall
,
src_ack_i
=>
src_i
.
ack
,
src_err_i
=>
src_i
.
err
,
snk_dat_i
=>
snk_i
.
dat
,
snk_adr_i
=>
snk_i
.
adr
,
snk_sel_i
=>
snk_i
.
sel
,
...
...
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