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White Rabbit core collection
Commit 87bdf89b authored by Tomasz Wlostowski's avatar Tomasz Wlostowski Committed by Grzegorz Daniluk
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top/spec_1_1/wr_core_demo: improved host- and host-less carrier reset, removed obsolete files 

Signed-off-by: Grzegorz Daniluk's avatarGrzegorz Daniluk <grzegorz.daniluk@cern.ch>
parent 20851203
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Showing with 98 additions and 208 deletions
top/spec_1_1/wr_core_demo/Manifest.py
View file @ 87bdf89b
files = ["spec_top.vhd", "spec_top.ucf", "wb_gpio_port_notristates.vhd"]
files = ["spec_top.vhd", "spec_top.ucf", "spec_reset_gen.vhd"]
fetchto = "../../../ip_cores"
......
top/spec_1_1/wr_core_demo/spec_reset_gen.vhd 0 → 100644
View file @ 87bdf89b
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
use work.gencores_pkg.all;
entity spec_reset_gen is
port (
clk_sys_i : in std_logic;
rst_pcie_n_a_i : in std_logic;
rst_button_n_a_i : in std_logic;
rst_n_o : out std_logic
);
end spec_reset_gen;
architecture behavioral of spec_reset_gen is
signal powerup_cnt : unsigned(7 downto 0) := x"00";
signal button_synced_n : std_logic;
signal pcie_synced_n : std_logic;
signal powerup_n : std_logic := '0';
begin -- behavioral
U_EdgeDet_PCIe : gc_sync_ffs port map (
clk_i => clk_sys_i,
rst_n_i => '1',
data_i => rst_pcie_n_a_i,
ppulse_o => pcie_synced_n);
U_Sync_Button : gc_sync_ffs port map (
clk_i => clk_sys_i,
rst_n_i => '1',
data_i => rst_button_n_a_i,
synced_o => button_synced_n);
p_powerup_reset : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if(powerup_cnt /= x"ff") then
powerup_cnt <= powerup_cnt + 1;
powerup_n <= '0';
else
powerup_n <= '1';
end if;
end if;
end process;
rst_n_o <= powerup_n and button_synced_n and (not pcie_synced_n);
end behavioral;
top/spec_1_1/wr_core_demo/spec_top.ucf
View file @ 87bdf89b
......@@ -631,7 +631,7 @@ PIN "clk_125m_pllref_BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2011/06/09
NET "U_GTP/ch1_gtp_clkout_int<1>" TNM_NET = U_GTP/ch1_gtp_clkout_int<1>;
TIMESPEC TS_U_GTP_ch1_gtp_clkout_int_1_ = PERIOD "U_GTP/ch1_gtp_clkout_int<1>" 8 ns HIGH 50%;
PIN "cmp_clk_dmtd_buf.O" CLOCK_DEDICATED_ROUTE = FALSE;
# PIN "cmp_clk_dmtd_buf.O" CLOCK_DEDICATED_ROUTE = FALSE;
##Created by Constraints Editor (xc6slx45t-fgg484-3) - 2012/08/07
INST "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/clk_in" TNM = skew_limit;
INST "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].DMTD_FB/clk_in" TNM = skew_limit;
......
top/spec_1_1/wr_core_demo/spec_top.vhd
View file @ 87bdf89b
......@@ -84,8 +84,8 @@ entity spec_top is
fpga_scl_b : inout std_logic;
fpga_sda_b : inout std_logic;
button1_i : in std_logic;
button2_i : in std_logic;
button1_i : in std_logic := 'H';
button2_i : in std_logic := 'H';
thermo_id : inout std_logic; -- 1-Wire interface to DS18B20
......@@ -232,6 +232,14 @@ architecture rtl of spec_top is
);
end component; -- gn4124_core
component spec_reset_gen
port (
clk_sys_i : in std_logic;
rst_pcie_n_a_i : in std_logic;
rst_button_n_a_i : in std_logic;
rst_n_o : out std_logic);
end component;
--component chipscope_ila
-- port (
-- CONTROL : inout std_logic_vector(35 downto 0);
......@@ -325,8 +333,8 @@ architecture rtl of spec_top is
signal dac_hpll_data : std_logic_vector(15 downto 0);
signal dac_dpll_data : std_logic_vector(15 downto 0);
signal pps : std_logic;
signal pps_led : std_logic;
signal pps : std_logic;
signal pps_led : std_logic;
signal phy_tx_data : std_logic_vector(7 downto 0);
signal phy_tx_k : std_logic;
......@@ -347,10 +355,10 @@ architecture rtl of spec_top is
signal local_reset_n : std_logic;
signal button1_synced : std_logic_vector(2 downto 0);
signal genum_wb_out : t_wishbone_master_out;
signal genum_wb_in : t_wishbone_master_in;
signal genum_wb_out : t_wishbone_master_out;
signal genum_wb_in : t_wishbone_master_in;
signal genum_csr_ack_i : std_logic;
signal wrc_slave_i : t_wishbone_slave_in;
signal wrc_slave_o : t_wishbone_slave_out;
......@@ -359,16 +367,16 @@ architecture rtl of spec_top is
signal wb_adr : std_logic_vector(31 downto 0); --c_BAR0_APERTURE-priv_log2_ceil(c_CSR_WB_SLAVES_NB+1)-1 downto 0);
signal etherbone_rst_n : std_logic;
signal etherbone_src_out : t_wrf_source_out;
signal etherbone_src_in : t_wrf_source_in;
signal etherbone_snk_out : t_wrf_sink_out;
signal etherbone_snk_in : t_wrf_sink_in;
signal etherbone_wb_out : t_wishbone_master_out;
signal etherbone_wb_in : t_wishbone_master_in;
signal etherbone_cfg_in : t_wishbone_slave_in;
signal etherbone_cfg_out : t_wishbone_slave_out;
signal etherbone_rst_n : std_logic;
signal etherbone_src_out : t_wrf_source_out;
signal etherbone_src_in : t_wrf_source_in;
signal etherbone_snk_out : t_wrf_sink_out;
signal etherbone_snk_in : t_wrf_sink_in;
signal etherbone_wb_out : t_wishbone_master_out;
signal etherbone_wb_in : t_wishbone_master_in;
signal etherbone_cfg_in : t_wishbone_slave_in;
signal etherbone_cfg_out : t_wishbone_slave_out;
begin
cmp_sys_clk_pll : PLL_BASE
......@@ -411,10 +419,10 @@ begin
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 50,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 16, -- 62.5 MHz
CLKOUT0_DIVIDE => 16, -- 62.5 MHz
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 16, -- 62.5 MHz
CLKOUT1_DIVIDE => 16, -- 62.5 MHz
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 8,
......@@ -435,26 +443,12 @@ begin
CLKFBIN => pllout_clk_fb_dmtd,
CLKIN => clk_20m_vcxo_buf);
--p_gen_reset : process(clk_sys)
--begin
-- if rising_edge(clk_sys) then
-- button1_synced(0) <= button1_i;
-- button1_synced(1) <= button1_synced(0);
-- button1_synced(2) <= button1_synced(1);
-- if(L_RST_N = '0') then
-- local_reset_n <= '0';
-- elsif (button1_synced(2) = '0') then
-- local_reset_n <= '0';
-- else
-- local_reset_n <= '1';
-- end if;
-- end if;
--end process;
local_reset_n <= L_RST_N;
U_Reset_Gen : spec_reset_gen
port map (
clk_sys_i => clk_sys,
rst_pcie_n_a_i => L_RST_N,
rst_button_n_a_i => button1_i,
rst_n_o => local_reset_n);
cmp_clk_sys_buf : BUFG
port map (
......@@ -509,7 +503,7 @@ begin
O => gtp_dedicated_clk,
I => fpga_pll_ref_clk_101_p_i,
IB => fpga_pll_ref_clk_101_n_i
);
);
------------------------------------------------------------------------------
......@@ -597,9 +591,9 @@ begin
--dma_stall_i => dma_stall
);
genum_csr_ack_i <= genum_wb_in.ack or genum_wb_in.err;
genum_wb_out.adr( 1 downto 0) <= (others => '0');
genum_wb_out.adr(18 downto 2) <= wb_adr(16 downto 0);
genum_csr_ack_i <= genum_wb_in.ack or genum_wb_in.err;
genum_wb_out.adr(1 downto 0) <= (others => '0');
genum_wb_out.adr(18 downto 2) <= wb_adr(16 downto 0);
genum_wb_out.adr(31 downto 19) <= (others => '0');
process(clk_sys, rst)
......@@ -683,7 +677,7 @@ begin
slave_i => wrc_slave_i,
slave_o => wrc_slave_o,
aux_master_o => etherbone_cfg_in,
aux_master_i => etherbone_cfg_out,
......@@ -700,7 +694,7 @@ begin
tm_utc_o => open,
tm_cycles_o => open,
pps_p_o => pps,
pps_led_o => pps_led,
pps_led_o => pps_led,
dio_o => dio_out(4 downto 1),
rst_aux_n_o => etherbone_rst_n
......@@ -708,7 +702,7 @@ begin
Etherbone : EB_CORE
generic map (
g_sdb_address => x"0000000000030000")
g_sdb_address => x"0000000000030000")
port map (
clk_i => clk_sys,
nRst_i => etherbone_rst_n,
......@@ -738,7 +732,7 @@ begin
slave_o(1) => etherbone_wb_in,
master_i(0) => wrc_slave_o,
master_o(0) => wrc_slave_i);
---------------------
U_GTP : wr_gtp_phy_spartan6
......@@ -862,25 +856,6 @@ begin
sfp_tx_disable_o <= '0';
--chipscope_ila_1 : chipscope_ila
-- port map (
-- CONTROL => CONTROL,
-- CLK => clk_125m_pllref,
-- TRIG0 => TRIG0,
-- TRIG1 => TRIG1,
-- TRIG2 => TRIG2,
-- TRIG3 => TRIG3);
--chipscope_icon_1 : chipscope_icon
-- port map (
-- CONTROL0 => CONTROL
-- );
--TRIG0(7 downto 0)<=phy_tx_data;
--TRIG0(8) <= phy_tx_k;
--TRIG0(9) <= phy_tx_disparity;
--TRIG0(10) <= phy_tx_enc_err;
end rtl;
top/spec_1_1/wr_core_demo/wb_gpio_port_notristates.vhd deleted 100644 → 0
View file @ 20851203
------------------------------------------------------------------------------
-- Title : Wishbone GPIO port
-- Project : White Rabbit Switch
------------------------------------------------------------------------------
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-05-18
-- Last update: 2011-04-06
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: Bidirectional GPIO port of configurable width (1 to 32 bits).
-------------------------------------------------------------------------------
-- Copyright (c) 2010 Tomasz Wlostowski
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-05-18 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
library work;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
entity wb_gpio_port_notristates is
generic(g_num_pins : natural := 8 -- number of GPIO pins
);
port(
-- System reset, active low
sys_rst_n_i : in std_logic;
-------------------------------------------------------------------------------
-- Wishbone bus
-------------------------------------------------------------------------------
wb_clk_i : in std_logic;
wb_sel_i : in std_logic;
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_addr_i : in std_logic_vector(2 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_ack_o : out std_logic;
-- GPIO pin vector
gpio_o : out std_logic_vector(g_num_pins-1 downto 0);
gpio_i : in std_logic_vector(g_num_pins-1 downto 0);
gpio_dir_o : out std_logic_vector(g_num_pins-1 downto 0)
);
end wb_gpio_port_notristates;
architecture behavioral of wb_gpio_port_notristates is
constant c_GPIO_REG_CODR : std_logic_vector(2 downto 0) := "000"; -- *reg* clear output register
constant c_GPIO_REG_SODR : std_logic_vector(2 downto 0) := "001"; -- *reg* set output register
constant c_GPIO_REG_DDR : std_logic_vector(2 downto 0) := "010"; -- *reg* data direction register
constant c_GPIO_REG_PSR : std_logic_vector(2 downto 0) := "011"; -- *reg* pin state register
signal out_reg, in_reg, dir_reg : std_logic_vector(g_num_pins-1 downto 0);
signal gpio_in_synced : std_logic_vector(g_num_pins-1 downto 0);
signal ack_int : std_logic;
begin
GEN_SYNC_FFS : for i in 0 to g_num_pins-1 generate
INPUT_SYNC : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
rst_n_i => sys_rst_n_i,
clk_i => wb_clk_i,
data_i => gpio_i(i),
synced_o => gpio_in_synced(i),
npulse_o => open
);
end generate GEN_SYNC_FFS;
process (wb_clk_i, sys_rst_n_i)
begin
if sys_rst_n_i = '0' then
dir_reg <= (others => '0');
out_reg <= (others => '0');
ack_int <= '0';
wb_data_o(g_num_pins-1 downto 0) <= (others => '0');
elsif rising_edge(wb_clk_i) then
if(ack_int = '1') then
ack_int <= '0';
elsif(wb_cyc_i = '1') and (wb_sel_i = '1') and (wb_stb_i = '1') then
if(wb_we_i = '1') then
case wb_addr_i(2 downto 0) is
when c_GPIO_REG_SODR =>
out_reg <= out_reg or wb_data_i(g_num_pins-1 downto 0);
ack_int <= '1';
when c_GPIO_REG_CODR =>
out_reg <= out_reg and (not wb_data_i(g_num_pins-1 downto 0));
ack_int <= '1';
when c_GPIO_REG_DDR =>
dir_reg <= wb_data_i(g_num_pins-1 downto 0);
ack_int <= '1';
when others =>
ack_int <= '1';
end case;
else
case wb_addr_i(2 downto 0) is
when c_GPIO_REG_DDR =>
wb_data_o(g_num_pins-1 downto 0) <= dir_reg;
ack_int <= '1';
when c_GPIO_REG_PSR =>
wb_data_o(g_num_pins-1 downto 0) <= gpio_in_synced;
ack_int <= '1';
when others =>
ack_int <= '1';
end case;
end if;
else
ack_int <= '0';
end if;
end if;
end process;
gpio_dir_o <= dir_reg;
gpio_o <= out_reg;
wb_ack_o <= ack_int;
end behavioral;
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