pps_gen: adding xwb module

8969dbb0 · Grzegorz Daniluk · bd46dc5b · 8969dbb0 · 8969dbb0
Commit 8969dbb0 authored Oct 26, 2011 by Grzegorz Daniluk
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Manifest.py modules/wrsw_pps_gen/Manifest.py +2 -1

xwb_pps_gen.vhd modules/wrsw_pps_gen/xwb_pps_gen.vhd +120 -0

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--- a/modules/wrsw_pps_gen/Manifest.py
+++ b/modules/wrsw_pps_gen/Manifest.py
 files = ["pps_gen_wb.vhd",
-				 "wrsw_pps_gen.vhd"];
\ No newline at end of file
+				 "wrsw_pps_gen.vhd",
+         "xwb_pps_gen.vhd"];
--- a/modules/wrsw_pps_gen/xwb_pps_gen.vhd
+++ b/modules/wrsw_pps_gen/xwb_pps_gen.vhd
+-------------------------------------------------------------------------------
+-- Title      : PPS Generator & UTC Realtime clock
+-- Project    : WhiteRabbit Switch
+-------------------------------------------------------------------------------
+-- File       : xwb_pps_gen.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-Co-HT
+-- Created    : 2010-09-02
+-- Last update: 2011-10-26
+-- Platform   : FPGA-generics
+-- Standard   : VHDL
+-------------------------------------------------------------------------------
+-- Description:
+-------------------------------------------------------------------------------
+-- Copyright (c) 2010 Tomasz Wlostowski
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2010-09-02  1.0      twlostow        Created
+-- 2011-05-09  1.1      twlostow        Added external PPS input
+-- 2011-10-26  1.2      greg.d          xwb module
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.gencores_pkg.all;
+use work.wishbone_pkg.all;
+
+entity xwb_pps_gen is
+  generic(
+    g_interface_mode      : t_wishbone_interface_mode      := CLASSIC;
+    g_address_granularity : t_wishbone_address_granularity := WORD
+  );
+  port (
+    clk_ref_i : in std_logic;
+    clk_sys_i : in std_logic;
+
+    rst_n_i   : in std_logic;
+
+    slave_i   : in  t_wishbone_slave_in;
+    slave_o   : out t_wishbone_slave_out;
+
+    pps_in_i : in std_logic;
+
+    -- Single-pulse PPS output for synchronizing endpoints to
+    pps_csync_o : out std_logic;
+    pps_out_o   : out std_logic;
+
+    pps_val_o   : out std_logic;
+    tc_utc_o    : out std_logic_vector(39 downto 0);
+    tc_nsec_o   : out std_logic_vector(27 downto 0);
+    tc_val_o    : out std_logic
+
+  );
+end xwb_pps_gen;
+
+architecture behavioral of xwb_pps_gen is
+
+  component wrsw_pps_gen is
+    generic(
+      g_interface_mode      : t_wishbone_interface_mode;
+      g_address_granularity : t_wishbone_address_granularity
+    );
+    port (
+      clk_ref_i : in std_logic;
+      clk_sys_i : in std_logic;
+      rst_n_i   : in std_logic;
+      wb_addr_i : in  std_logic_vector(3 downto 0);
+      wb_data_i : in  std_logic_vector(31 downto 0);
+      wb_data_o : out std_logic_vector(31 downto 0);
+      wb_cyc_i  : in  std_logic;
+      wb_sel_i  : in  std_logic_vector(3 downto 0);
+      wb_stb_i  : in  std_logic;
+      wb_we_i   : in  std_logic;
+      wb_ack_o  : out std_logic;
+      wb_stall_o : out std_logic;
+      pps_in_i : in std_logic;
+      pps_csync_o : out std_logic;
+      pps_out_o   : out std_logic;
+      pps_val_o   : out std_logic;
+      tc_utc_o    : out std_logic_vector(39 downto 0);
+      tc_nsec_o   : out std_logic_vector(27 downto 0);
+      tc_val_o    : out std_logic
+    );
+  end component;
+  
+begin  -- behavioral
+
+  WRAPPED_PPSGEN: wrsw_pps_gen 
+    generic map(
+      g_interface_mode      => g_interface_mode,
+      g_address_granularity => g_address_granularity
+    )
+    port map(
+      clk_ref_i => clk_ref_i,
+      clk_sys_i => clk_sys_i,
+      rst_n_i   => rst_n_i,
+      wb_addr_i => slave_i.adr(3 downto 0),
+      wb_data_i => slave_i.dat,
+      wb_data_o => slave_o.dat,
+      wb_cyc_i  => slave_i.cyc,
+      wb_sel_i  => slave_i.sel,
+      wb_stb_i  => slave_i.stb,
+      wb_we_i   => slave_i.we,
+      wb_ack_o  => slave_o.ack,
+      wb_stall_o => slave_o.stall,
+      pps_in_i    => pps_in_i,
+      pps_csync_o => pps_csync_o,
+      pps_out_o   => pps_out_o,
+      pps_val_o   => pps_val_o,
+      tc_utc_o    => tc_utc_o,
+      tc_nsec_o   => tc_nsec_o,
+      tc_val_o    => tc_val_o
+    );
+
+  
+end behavioral;