modules/wrc_core: expose PPS csync signal to top-level modules

PPS csync is asserted one 125MHz ref clock cycle before the actual PPS. It can be used for aligning another signal to the PPS.

modules/wrc_core: expose PPS csync signal to top-level modules
PPS csync is asserted one 125MHz ref clock cycle before the actual PPS. It can be used for aligning another signal to the PPS.
8b4c2d9f · Dimitris Lampridis · Grzegorz Daniluk · ae0028ff · 8b4c2d9f · 8b4c2d9f
Commit 8b4c2d9f authored May 29, 2017 by Dimitris Lampridis Committed by Grzegorz Daniluk Jul 04, 2017
5 changed files
--- a/board/common/wr_board_pkg.vhd
+++ b/board/common/wr_board_pkg.vhd
@@ -166,6 +166,7 @@ package wr_board_pkg is
      led_link_o           : out std_logic;
      btn1_i               : in  std_logic                                        := '1';
      btn2_i               : in  std_logic                                        := '1';
+      pps_csync_o          : out std_logic;
      pps_p_o              : out std_logic;
      pps_led_o            : out std_logic;
      link_ok_o            : out std_logic);

--- a/board/common/xwrc_board_common.vhd
+++ b/board/common/xwrc_board_common.vhd
@@ -7,7 +7,7 @@
 -- Author(s)  : Dimitrios Lampridis  <dimitrios.lampridis@cern.ch>
 -- Company    : CERN (BE-CO-HT)
 -- Created    : 2017-02-22
-- Last update: 2017-03-10
+-- Last update: 2017-05-29
 -- Standard   : VHDL'93
 -------------------------------------------------------------------------------
 -- Description: Wrapper for WR PTP core with common features shared between
@@ -246,10 +246,11 @@ entity xwrc_board_common is
    btn1_i     : in  std_logic := '1';
    btn2_i     : in  std_logic := '1';
    -- 1PPS output
-    pps_p_o    : out std_logic;
-    pps_led_o  : out std_logic;
+    pps_csync_o : out std_logic;
+    pps_p_o     : out std_logic;
+    pps_led_o   : out std_logic;
    -- Link ok indication
-    link_ok_o  : out std_logic
+    link_ok_o : out std_logic
    );

 end entity xwrc_board_common;
@@ -285,7 +286,7 @@ architecture struct of xwrc_board_common is
  -- Application diagnostic words are added after streamer's diagnostics in the array that
  -- goes to/from WRPC

-  constant c_streamers_diag_id  : integer := 1;   -- id reserved for streamers
+  constant c_streamers_diag_id  : integer := 1;  -- id reserved for streamers
  constant c_streamers_diag_ver : integer := 2;  -- version that will be probably increased
  -- when more diagnostics is added to streamers

@@ -423,6 +424,7 @@ begin  -- architecture struct
      tm_time_valid_o      => tm_time_valid,
      tm_tai_o             => tm_tai,
      tm_cycles_o          => tm_cycles,
+      pps_csync_o          => pps_csync_o,
      pps_p_o              => pps_p_o,
      pps_led_o            => pps_led_o,
      rst_aux_n_o          => aux_rst_n,

--- a/modules/wrc_core/wr_core.vhd
+++ b/modules/wrc_core/wr_core.vhd
@@ -5,7 +5,7 @@
 -- Author     : Grzegorz Daniluk
 -- Company    : Elproma
 -- Created    : 2011-02-02
-- Last update: 2017-04-25
+-- Last update: 2017-05-29
 -- Platform   : FPGA-generics
 -- Standard   : VHDL
 -------------------------------------------------------------------------------
@@ -297,6 +297,7 @@ entity wr_core is
    tm_tai_o             : out std_logic_vector(39 downto 0);
    tm_cycles_o          : out std_logic_vector(27 downto 0);
    -- 1PPS output
+    pps_csync_o          : out std_logic;
    pps_p_o              : out std_logic;
    pps_led_o            : out std_logic;

@@ -625,6 +626,7 @@ begin
      tm_time_valid_o => tm_time_valid_o
      );
  ppsg_link_ok <= not phy_rst;
+  pps_csync_o  <= s_pps_csync;

  -----------------------------------------------------------------------------
  -- Software PLL

--- a/modules/wrc_core/wrcore_pkg.vhd
+++ b/modules/wrc_core/wrcore_pkg.vhd
@@ -462,6 +462,7 @@ package wrcore_pkg is
      tm_time_valid_o      : out std_logic;
      tm_tai_o             : out std_logic_vector(39 downto 0);
      tm_cycles_o          : out std_logic_vector(27 downto 0);
+      pps_csync_o          : out std_logic;
      pps_p_o              : out std_logic;
      pps_led_o            : out std_logic;

@@ -696,6 +697,7 @@ package wrcore_pkg is
      tm_tai_o             : out std_logic_vector(39 downto 0);
      tm_cycles_o          : out std_logic_vector(27 downto 0);
      -- 1PPS output
+      pps_csync_o          : out std_logic;
      pps_p_o              : out std_logic;
      pps_led_o            : out std_logic;


--- a/modules/wrc_core/xwr_core.vhd
+++ b/modules/wrc_core/xwr_core.vhd
@@ -6,7 +6,7 @@
 -- Author     : Grzegorz Daniluk
 -- Company    : Elproma
 -- Created    : 2011-02-02
-- Last update: 2017-04-01
+-- Last update: 2017-05-29
 -- Platform   : FPGA-generics
 -- Standard   : VHDL
 -------------------------------------------------------------------------------
@@ -247,6 +247,7 @@ entity xwr_core is
    tm_tai_o             : out std_logic_vector(39 downto 0);
    tm_cycles_o          : out std_logic_vector(27 downto 0);
    -- 1PPS output
+    pps_csync_o          : out std_logic;
    pps_p_o              : out std_logic;
    pps_led_o            : out std_logic;

@@ -416,6 +417,7 @@ begin
      tm_time_valid_o      => tm_time_valid_o,
      tm_tai_o             => tm_tai_o,
      tm_cycles_o          => tm_cycles_o,
+      pps_csync_o          => pps_csync_o,
      pps_p_o              => pps_p_o,
      pps_led_o            => pps_led_o,