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White Rabbit core collection
Commit 8bdb4344 authored by Maciej Lipinski's avatar Maciej Lipinski Committed by Grzegorz Daniluk
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[wr_streamers] bugfix: extended all conters to 50 bits (max 64) 

32-bit counters would overflow after few hours of btrain traffic.
So, I increased counters to have max 64 bits and configured them
to have 50 bits, which should be sufficient for 50 years of traffic
with 500kHz.

Conflicts:

	modules/wr_streamers/xrtx_streamers_stats.vhd
parent fef6235a
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Showing with 469 additions and 224 deletions
board/common/xwrc_board_common.vhd
View file @ 8bdb4344
......@@ -279,15 +279,15 @@ architecture struct of xwrc_board_common is
-- goes to/from WRPC
constant c_streamers_diag_id : integer := 1; -- id reserved for streamers
constant c_streamers_diag_ver : integer := 1; -- version that will be probably increased
constant c_streamers_diag_ver : integer := 2; -- version that will be probably increased
-- when more diagnostics is added to streamers
-- final values that go to WRPC generics (depend on configuration)
constant c_diag_id : integer := f_pick_diag_val(g_fabric_iface, c_streamers_diag_id, g_diag_id);
constant c_diag_ver : integer := f_pick_diag_val(g_fabric_iface, c_streamers_diag_id, g_diag_id);
constant c_diag_ver : integer := f_pick_diag_val(g_fabric_iface, c_streamers_diag_ver, g_diag_id);
constant c_diag_ro_size : integer := f_pick_diag_size(g_fabric_iface, c_WR_TRANS_ARR_SIZE_OUT, g_diag_ro_size);
constant c_diag_rw_size : integer := f_pick_diag_size(g_fabric_iface, c_WR_TRANS_ARR_SIZE_IN, g_diag_rw_size);
constant c_diag_ro_size : integer := f_pick_diag_size(g_fabric_iface, c_WR_STREAMERS_ARR_SIZE_OUT, g_diag_ro_size);
constant c_diag_rw_size : integer := f_pick_diag_size(g_fabric_iface, c_WR_STREAMERS_ARR_SIZE_IN, g_diag_rw_size);
-- WR SNMP
signal aux_diag_in : t_generic_word_array(c_diag_ro_size-1 downto 0);
......@@ -457,8 +457,8 @@ begin -- architecture struct
link_ok_i => link_ok,
wb_slave_i => aux_master_out,
wb_slave_o => aux_master_in,
snmp_array_o => aux_diag_in(c_WR_TRANS_ARR_SIZE_OUT-1 downto 0),
snmp_array_i => aux_diag_out(c_WR_TRANS_ARR_SIZE_IN-1 downto 0),
snmp_array_o => aux_diag_in(c_WR_STREAMERS_ARR_SIZE_OUT-1 downto 0),
snmp_array_i => aux_diag_out(c_WR_STREAMERS_ARR_SIZE_IN-1 downto 0),
tx_streamer_cfg_i=> wrs_tx_cfg_i,
rx_streamer_cfg_i=> wrs_rx_cfg_i);
......@@ -469,8 +469,8 @@ begin -- architecture struct
aux_master_o <= cc_dummy_master_out;
wb_eth_master_o <= cc_dummy_master_out;
aux_diag_in(c_diag_ro_size-1 downto c_WR_TRANS_ARR_SIZE_OUT) <= aux_diag_i;
aux_diag_o <= aux_diag_out(c_diag_rw_size-1 downto c_WR_TRANS_ARR_SIZE_IN);
aux_diag_in(c_diag_ro_size-1 downto c_WR_STREAMERS_ARR_SIZE_OUT) <= aux_diag_i;
aux_diag_o <= aux_diag_out(c_diag_rw_size-1 downto c_WR_STREAMERS_ARR_SIZE_IN);
end generate gen_wr_streamers;
......
modules/wr_streamers/streamers_pkg.vhd
View file @ 8bdb4344
......@@ -233,13 +233,13 @@ package streamers_pkg is
rx_streamer_cfg_i : in t_rx_streamer_cfg := c_rx_streamer_cfg_default);
end component;
constant c_STREAMERS_ARR_SIZE_OUT : integer := 14;
constant c_STREAMERS_ARR_SIZE_IN : integer := 1;
constant c_WRS_STATS_ARR_SIZE_OUT : integer := 18;
constant c_WRS_STATS_ARR_SIZE_IN : integer := 1;
component xrtx_streamers_stats is
generic (
g_streamers_op_mode : t_streamers_op_mode := TX_AND_RX;
g_cnt_width : integer := 32;
g_cnt_width : integer := 50;
g_acc_width : integer := 64
);
port (
......@@ -269,13 +269,13 @@ package streamers_pkg is
latency_acc_o : out std_logic_vector(g_acc_width-1 downto 0);
latency_max_o : out std_logic_vector(27 downto 0);
latency_min_o : out std_logic_vector(27 downto 0);
snmp_array_o : out t_generic_word_array(c_STREAMERS_ARR_SIZE_OUT-1 downto 0);
snmp_array_i : in t_generic_word_array(c_STREAMERS_ARR_SIZE_IN -1 downto 0) := (others => (others=>'0'))
snmp_array_o : out t_generic_word_array(c_WRS_STATS_ARR_SIZE_OUT-1 downto 0);
snmp_array_i : in t_generic_word_array(c_WRS_STATS_ARR_SIZE_IN -1 downto 0) := (others => (others=>'0'))
);
end component;
constant c_WR_TRANS_ARR_SIZE_OUT : integer := c_STREAMERS_ARR_SIZE_OUT+3;
constant c_WR_TRANS_ARR_SIZE_IN : integer := c_STREAMERS_ARR_SIZE_IN;
constant c_WR_STREAMERS_ARR_SIZE_OUT : integer := c_WRS_STATS_ARR_SIZE_OUT+2;
constant c_WR_STREAMERS_ARR_SIZE_IN : integer := c_WRS_STATS_ARR_SIZE_IN;
component xwr_streamers is
generic (
......@@ -284,7 +284,7 @@ package streamers_pkg is
g_tx_streamer_params : t_tx_streamer_params := c_tx_streamer_params_defaut;
g_rx_streamer_params : t_rx_streamer_params := c_rx_streamer_params_defaut;
-- stats
g_stats_cnt_width : integer := 32;
g_stats_cnt_width : integer := 50;
g_stats_acc_width : integer := 64;
-- WB i/f
g_slave_mode : t_wishbone_interface_mode := CLASSIC;
......@@ -320,8 +320,8 @@ package streamers_pkg is
link_ok_i : in std_logic := '1';
wb_slave_i : in t_wishbone_slave_in := cc_dummy_slave_in;
wb_slave_o : out t_wishbone_slave_out;
snmp_array_o : out t_generic_word_array(c_WR_TRANS_ARR_SIZE_OUT-1 downto 0);
snmp_array_i : in t_generic_word_array(c_WR_TRANS_ARR_SIZE_IN -1 downto 0);
snmp_array_o : out t_generic_word_array(c_WR_STREAMERS_ARR_SIZE_OUT-1 downto 0);
snmp_array_i : in t_generic_word_array(c_WR_STREAMERS_ARR_SIZE_IN -1 downto 0);
-- Transmission (tx) configuration
tx_streamer_cfg_i : in t_tx_streamer_cfg := c_tx_streamer_cfg_default;
rx_streamer_cfg_i : in t_rx_streamer_cfg := c_rx_streamer_cfg_default
......
modules/wr_streamers/streamers_priv_pkg.vhd
View file @ 8bdb4344
......@@ -86,7 +86,7 @@ package streamers_priv_pkg is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_adr_i : in std_logic_vector(5 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
......
modules/wr_streamers/wr_streamers_wb.vhd
View file @ 8bdb4344
This diff is collapsed.
modules/wr_streamers/wr_streamers_wb.wb
View file @ 8bdb4344
......@@ -90,13 +90,65 @@ peripheral {
access_dev = WRITE_ONLY;
};
};
reg {
name = "Statistics status and ctrl register";
prefix = "SSCR3";
field {
name = "Reset timestamp 8 MSB of TAI";
prefix = "RST_TS_TAI_MSB";
description = "Timestamp of the last reset of stats (RST_STAT) -- MSB 8 bits of TAI";
type = SLV;
size = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Rx statistics";
prefix = "RX_STAT0";
field {
name = "WR Streamer frame latency";
description = "Maximum latency of received frames since reset";
prefix = "RX_LATENCY_MAX";
type = SLV;
size = 28;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Rx statistics";
prefix = "RX_STAT1";
field {
name = "WR Streamer frame latency";
description = "Minimum latency of received frames since reset";
prefix = "RX_LATENCY_MIN";
type = SLV;
size = 28;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Tx statistics";
prefix = "TX_STAT2";
field {
name = "WR Streamer frame sent count (LSB)";
description = "Number of sent wr streamer frames since reset";
prefix = "TX_SENT_CNT_LSB";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Tx statistics";
prefix = "TX_STAT";
prefix = "TX_STAT3";
field {
name = "WR Streamer frame sent count";
name = "WR Streamer frame sent count (MSB)";
description = "Number of sent wr streamer frames since reset";
prefix = "TX_SENT_CNT";
prefix = "TX_SENT_CNT_MSB";
type = SLV;
size = 32;
access_bus = READ_ONLY;
......@@ -105,24 +157,38 @@ peripheral {
};
reg {
name = "Rx statistics";
prefix = "RX_STAT1";
prefix = "RX_STAT4";
field {
name = "WR Streamer frame received count (LSB)";
description = "Number of received wr streamer frames since reset";
prefix = "RX_RCVD_CNT_LSB";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Rx statistics";
prefix = "RX_STAT5";
field {
name = "WR Streamer frame received count";
name = "WR Streamer frame received count (MSB)";
description = "Number of received wr streamer frames since reset";
prefix = "RX_RCVD_CNT";
prefix = "RX_RCVD_CNT_MSB";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Rx statistics";
prefix = "RX_STAT2";
prefix = "RX_STAT6";
field {
name = "WR Streamer frame loss count";
name = "WR Streamer frame loss count (LSB)";
description = "Number of lost wr streamer frames since reset";
prefix = "RX_LOSS_CNT";
prefix = "RX_LOSS_CNT_LSB";
type = SLV;
size = 32;
access_bus = READ_ONLY;
......@@ -131,36 +197,51 @@ peripheral {
};
reg {
name = "Rx statistics";
prefix = "RX_STAT3";
prefix = "RX_STAT7";
field {
name = "WR Streamer frame latency";
description = "Maximum latency of received frames since reset";
prefix = "RX_LATENCY_MAX";
name = "WR Streamer frame loss count (MSB)";
description = "Number of lost wr streamer frames since reset";
prefix = "RX_LOSS_CNT_MSB";
type = SLV;
size = 28;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Rx statistics";
prefix = "RX_STAT4";
prefix = "RX_STAT8";
field {
name = "WR Streamer frame latency";
description = "Minimum latency of received frames since reset";
prefix = "RX_LATENCY_MIN";
name = "WR Streamer block loss count (LSB)";
description = "Number of indications that one or more blocks in a frame were lost (probably CRC\
error) since reset";
prefix = "RX_LOST_BLOCK_CNT_LSB";
type = SLV;
size = 28;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Rx statistics";
prefix = "RX_STAT5";
prefix = "RX_STAT9";
field {
name = "WR Streamer frame latency";
description = "Accumulated latency (LSB) of received frames since reset";
name = "WR Streamer block loss count (MSB)";
description = "Number of indications that one or more blocks in a frame were lost (probably CRC\
error) since reset";
prefix = "RX_LOST_BLOCK_CNT_MSB";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Rx statistics";
prefix = "RX_STAT10";
field {
name = "WR Streamer frame latency (LSB)";
description = "Accumulated latency of received frames since reset";
prefix = "RX_LATENCY_ACC_LSB";
type = SLV;
size = 32;
......@@ -170,10 +251,10 @@ peripheral {
};
reg {
name = "Rx statistics";
prefix = "RX_STAT6";
prefix = "RX_STAT11";
field {
name = "WR Streamer frame latency";
description = "Accumulated latency (MSB) of received frames since reset";
name = "WR Streamer frame latency (MSB)";
description = "Accumulated latency of received frames since reset";
prefix = "RX_LATENCY_ACC_MSB";
type = SLV;
size = 32;
......@@ -183,11 +264,11 @@ peripheral {
};
reg {
name = "Rx statistics";
prefix = "RX_STAT7";
prefix = "RX_STAT12";
field {
name = "WR Streamer frame latency counter";
name = "WR Streamer frame latency counter (LSB)";
description = "Counter of the accumulated frequency (so avg can be calculated in SW) since reset";
prefix = "RX_LATENCY_ACC_CNT";
prefix = "RX_LATENCY_ACC_CNT_LSB";
type = SLV;
size = 32;
access_bus = READ_ONLY;
......@@ -196,18 +277,18 @@ peripheral {
};
reg {
name = "Rx statistics";
prefix = "RX_STAT8";
prefix = "RX_STAT13";
field {
name = "WR Streamer block loss count";
description = "Number of indications that one or more blocks in a frame were lost (probably CRC\
error) since reset";
prefix = "RX_LOST_BLOCK_CNT";
name = "WR Streamer frame latency counter (MSB)";
description = "Counter of the accumulated frequency (so avg can be calculated in SW) since reset";
prefix = "RX_LATENCY_ACC_CNT_MSB";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Tx Config Reg 0";
prefix = "TX_CFG0";
......
modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd
View file @ 8bdb4344
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wr_streamers_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from wr_streamers_wb.wb
-- Created : Mon May 8 18:32:46 2017
-- Created : Tue May 16 18:11:13 2017
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_streamers_wb.wb
......@@ -23,15 +23,21 @@ package wr_streamers_wbgen2_pkg is
sscr1_rx_latency_acc_overflow_i : std_logic;
sscr1_rst_ts_cyc_i : std_logic_vector(27 downto 0);
sscr2_rst_ts_tai_lsb_i : std_logic_vector(31 downto 0);
tx_stat_tx_sent_cnt_i : std_logic_vector(31 downto 0);
rx_stat1_rx_rcvd_cnt_i : std_logic_vector(31 downto 0);
rx_stat2_rx_loss_cnt_i : std_logic_vector(31 downto 0);
rx_stat3_rx_latency_max_i : std_logic_vector(27 downto 0);
rx_stat4_rx_latency_min_i : std_logic_vector(27 downto 0);
rx_stat5_rx_latency_acc_lsb_i : std_logic_vector(31 downto 0);
rx_stat6_rx_latency_acc_msb_i : std_logic_vector(31 downto 0);
rx_stat7_rx_latency_acc_cnt_i : std_logic_vector(31 downto 0);
rx_stat8_rx_lost_block_cnt_i : std_logic_vector(31 downto 0);
sscr3_rst_ts_tai_msb_i : std_logic_vector(7 downto 0);
rx_stat0_rx_latency_max_i : std_logic_vector(27 downto 0);
rx_stat1_rx_latency_min_i : std_logic_vector(27 downto 0);
tx_stat2_tx_sent_cnt_lsb_i : std_logic_vector(31 downto 0);
tx_stat3_tx_sent_cnt_msb_i : std_logic_vector(31 downto 0);
rx_stat4_rx_rcvd_cnt_lsb_i : std_logic_vector(31 downto 0);
rx_stat5_rx_rcvd_cnt_msb_i : std_logic_vector(31 downto 0);
rx_stat6_rx_loss_cnt_lsb_i : std_logic_vector(31 downto 0);
rx_stat7_rx_loss_cnt_msb_i : std_logic_vector(31 downto 0);
rx_stat8_rx_lost_block_cnt_lsb_i : std_logic_vector(31 downto 0);
rx_stat9_rx_lost_block_cnt_msb_i : std_logic_vector(31 downto 0);
rx_stat10_rx_latency_acc_lsb_i : std_logic_vector(31 downto 0);
rx_stat11_rx_latency_acc_msb_i : std_logic_vector(31 downto 0);
rx_stat12_rx_latency_acc_cnt_lsb_i : std_logic_vector(31 downto 0);
rx_stat13_rx_latency_acc_cnt_msb_i : std_logic_vector(31 downto 0);
dbg_data_i : std_logic_vector(31 downto 0);
dummy_dummy_i : std_logic_vector(31 downto 0);
end record;
......@@ -40,15 +46,21 @@ package wr_streamers_wbgen2_pkg is
sscr1_rx_latency_acc_overflow_i => '0',
sscr1_rst_ts_cyc_i => (others => '0'),
sscr2_rst_ts_tai_lsb_i => (others => '0'),
tx_stat_tx_sent_cnt_i => (others => '0'),
rx_stat1_rx_rcvd_cnt_i => (others => '0'),
rx_stat2_rx_loss_cnt_i => (others => '0'),
rx_stat3_rx_latency_max_i => (others => '0'),
rx_stat4_rx_latency_min_i => (others => '0'),
rx_stat5_rx_latency_acc_lsb_i => (others => '0'),
rx_stat6_rx_latency_acc_msb_i => (others => '0'),
rx_stat7_rx_latency_acc_cnt_i => (others => '0'),
rx_stat8_rx_lost_block_cnt_i => (others => '0'),
sscr3_rst_ts_tai_msb_i => (others => '0'),
rx_stat0_rx_latency_max_i => (others => '0'),
rx_stat1_rx_latency_min_i => (others => '0'),
tx_stat2_tx_sent_cnt_lsb_i => (others => '0'),
tx_stat3_tx_sent_cnt_msb_i => (others => '0'),
rx_stat4_rx_rcvd_cnt_lsb_i => (others => '0'),
rx_stat5_rx_rcvd_cnt_msb_i => (others => '0'),
rx_stat6_rx_loss_cnt_lsb_i => (others => '0'),
rx_stat7_rx_loss_cnt_msb_i => (others => '0'),
rx_stat8_rx_lost_block_cnt_lsb_i => (others => '0'),
rx_stat9_rx_lost_block_cnt_msb_i => (others => '0'),
rx_stat10_rx_latency_acc_lsb_i => (others => '0'),
rx_stat11_rx_latency_acc_msb_i => (others => '0'),
rx_stat12_rx_latency_acc_cnt_lsb_i => (others => '0'),
rx_stat13_rx_latency_acc_cnt_msb_i => (others => '0'),
dbg_data_i => (others => '0'),
dummy_dummy_i => (others => '0')
);
......@@ -154,15 +166,21 @@ begin
tmp.sscr1_rx_latency_acc_overflow_i := f_x_to_zero(left.sscr1_rx_latency_acc_overflow_i) or f_x_to_zero(right.sscr1_rx_latency_acc_overflow_i);
tmp.sscr1_rst_ts_cyc_i := f_x_to_zero(left.sscr1_rst_ts_cyc_i) or f_x_to_zero(right.sscr1_rst_ts_cyc_i);
tmp.sscr2_rst_ts_tai_lsb_i := f_x_to_zero(left.sscr2_rst_ts_tai_lsb_i) or f_x_to_zero(right.sscr2_rst_ts_tai_lsb_i);
tmp.tx_stat_tx_sent_cnt_i := f_x_to_zero(left.tx_stat_tx_sent_cnt_i) or f_x_to_zero(right.tx_stat_tx_sent_cnt_i);
tmp.rx_stat1_rx_rcvd_cnt_i := f_x_to_zero(left.rx_stat1_rx_rcvd_cnt_i) or f_x_to_zero(right.rx_stat1_rx_rcvd_cnt_i);
tmp.rx_stat2_rx_loss_cnt_i := f_x_to_zero(left.rx_stat2_rx_loss_cnt_i) or f_x_to_zero(right.rx_stat2_rx_loss_cnt_i);
tmp.rx_stat3_rx_latency_max_i := f_x_to_zero(left.rx_stat3_rx_latency_max_i) or f_x_to_zero(right.rx_stat3_rx_latency_max_i);
tmp.rx_stat4_rx_latency_min_i := f_x_to_zero(left.rx_stat4_rx_latency_min_i) or f_x_to_zero(right.rx_stat4_rx_latency_min_i);
tmp.rx_stat5_rx_latency_acc_lsb_i := f_x_to_zero(left.rx_stat5_rx_latency_acc_lsb_i) or f_x_to_zero(right.rx_stat5_rx_latency_acc_lsb_i);
tmp.rx_stat6_rx_latency_acc_msb_i := f_x_to_zero(left.rx_stat6_rx_latency_acc_msb_i) or f_x_to_zero(right.rx_stat6_rx_latency_acc_msb_i);
tmp.rx_stat7_rx_latency_acc_cnt_i := f_x_to_zero(left.rx_stat7_rx_latency_acc_cnt_i) or f_x_to_zero(right.rx_stat7_rx_latency_acc_cnt_i);
tmp.rx_stat8_rx_lost_block_cnt_i := f_x_to_zero(left.rx_stat8_rx_lost_block_cnt_i) or f_x_to_zero(right.rx_stat8_rx_lost_block_cnt_i);
tmp.sscr3_rst_ts_tai_msb_i := f_x_to_zero(left.sscr3_rst_ts_tai_msb_i) or f_x_to_zero(right.sscr3_rst_ts_tai_msb_i);
tmp.rx_stat0_rx_latency_max_i := f_x_to_zero(left.rx_stat0_rx_latency_max_i) or f_x_to_zero(right.rx_stat0_rx_latency_max_i);
tmp.rx_stat1_rx_latency_min_i := f_x_to_zero(left.rx_stat1_rx_latency_min_i) or f_x_to_zero(right.rx_stat1_rx_latency_min_i);
tmp.tx_stat2_tx_sent_cnt_lsb_i := f_x_to_zero(left.tx_stat2_tx_sent_cnt_lsb_i) or f_x_to_zero(right.tx_stat2_tx_sent_cnt_lsb_i);
tmp.tx_stat3_tx_sent_cnt_msb_i := f_x_to_zero(left.tx_stat3_tx_sent_cnt_msb_i) or f_x_to_zero(right.tx_stat3_tx_sent_cnt_msb_i);
tmp.rx_stat4_rx_rcvd_cnt_lsb_i := f_x_to_zero(left.rx_stat4_rx_rcvd_cnt_lsb_i) or f_x_to_zero(right.rx_stat4_rx_rcvd_cnt_lsb_i);
tmp.rx_stat5_rx_rcvd_cnt_msb_i := f_x_to_zero(left.rx_stat5_rx_rcvd_cnt_msb_i) or f_x_to_zero(right.rx_stat5_rx_rcvd_cnt_msb_i);
tmp.rx_stat6_rx_loss_cnt_lsb_i := f_x_to_zero(left.rx_stat6_rx_loss_cnt_lsb_i) or f_x_to_zero(right.rx_stat6_rx_loss_cnt_lsb_i);
tmp.rx_stat7_rx_loss_cnt_msb_i := f_x_to_zero(left.rx_stat7_rx_loss_cnt_msb_i) or f_x_to_zero(right.rx_stat7_rx_loss_cnt_msb_i);
tmp.rx_stat8_rx_lost_block_cnt_lsb_i := f_x_to_zero(left.rx_stat8_rx_lost_block_cnt_lsb_i) or f_x_to_zero(right.rx_stat8_rx_lost_block_cnt_lsb_i);
tmp.rx_stat9_rx_lost_block_cnt_msb_i := f_x_to_zero(left.rx_stat9_rx_lost_block_cnt_msb_i) or f_x_to_zero(right.rx_stat9_rx_lost_block_cnt_msb_i);
tmp.rx_stat10_rx_latency_acc_lsb_i := f_x_to_zero(left.rx_stat10_rx_latency_acc_lsb_i) or f_x_to_zero(right.rx_stat10_rx_latency_acc_lsb_i);
tmp.rx_stat11_rx_latency_acc_msb_i := f_x_to_zero(left.rx_stat11_rx_latency_acc_msb_i) or f_x_to_zero(right.rx_stat11_rx_latency_acc_msb_i);
tmp.rx_stat12_rx_latency_acc_cnt_lsb_i := f_x_to_zero(left.rx_stat12_rx_latency_acc_cnt_lsb_i) or f_x_to_zero(right.rx_stat12_rx_latency_acc_cnt_lsb_i);
tmp.rx_stat13_rx_latency_acc_cnt_msb_i := f_x_to_zero(left.rx_stat13_rx_latency_acc_cnt_msb_i) or f_x_to_zero(right.rx_stat13_rx_latency_acc_cnt_msb_i);
tmp.dbg_data_i := f_x_to_zero(left.dbg_data_i) or f_x_to_zero(right.dbg_data_i);
tmp.dummy_dummy_i := f_x_to_zero(left.dummy_dummy_i) or f_x_to_zero(right.dummy_dummy_i);
return tmp;
......
modules/wr_streamers/xrtx_streamers_stats.vhd
View file @ 8bdb4344
......@@ -67,7 +67,7 @@ entity xrtx_streamers_stats is
-- RX_ONLY or TX_ONLY mode to save resources.
g_streamers_op_mode : t_streamers_op_mode := TX_AND_RX;
-- Width of frame counters
g_cnt_width : integer := 32; -- minimum 15 bits, max 32
g_cnt_width : integer := 50; -- min:15, max:64, 50 bits should be ok for 50 years
g_acc_width : integer := 64 -- max value 64
);
port (
......@@ -107,8 +107,8 @@ entity xrtx_streamers_stats is
latency_max_o : out std_logic_vector(27 downto 0);
latency_min_o : out std_logic_vector(27 downto 0);
snmp_array_o : out t_generic_word_array(c_STREAMERS_ARR_SIZE_OUT-1 downto 0);
snmp_array_i : in t_generic_word_array(c_STREAMERS_ARR_SIZE_IN -1 downto 0)
snmp_array_o : out t_generic_word_array(c_WRS_STATS_ARR_SIZE_OUT-1 downto 0);
snmp_array_i : in t_generic_word_array(c_WRS_STATS_ARR_SIZE_IN -1 downto 0)
);
end xrtx_streamers_stats;
......@@ -282,7 +282,7 @@ begin
-- to be made available to the user of SNMP
-------------------------------------------------------------------------------------------
-- check sanity of values
assert (c_cw <= 32)
assert (c_cw <= 64)
report "g_cnt_width value not suppported by f_pack_streamers_statistics" severity error;
assert (c_aw <= 64)
report "g_cnt_width value not suppported by f_pack_streamers_statistics" severity error;
......@@ -293,34 +293,70 @@ begin
snmp_array_o(0)( 0) <= reset_stats; -- loop back for diagnostics
snmp_array_o(0)( 1) <= latency_acc_overflow_out;
snmp_array_o(0) (31 downto 2) <= (others => '0');
snmp_array_o(1)( 31 downto 0) <= x"0" & reset_time_cycles( 27 downto 0);
snmp_array_o(2)( 31 downto 0) <= reset_time_tai( 31 downto 0);
snmp_array_o(3)( 31 downto 0) <= x"000000" & reset_time_tai( 39 downto 32);
-- translate meaningful signals (statistics values) to generic output vectors
snmp_array_o(4 )(c_cw-1 downto 0) <= sent_frame_cnt_out;
snmp_array_o(5 )(c_cw-1 downto 0) <= rcvd_frame_cnt_out;
snmp_array_o(6 )(c_cw-1 downto 0) <= lost_frame_cnt_out;
snmp_array_o(7 )(c_cw-1 downto 0) <= lost_block_cnt_out;
snmp_array_o(8 )(c_cw-1 downto 0) <= latency_cnt_out;
snmp_array_o(9 )(31 downto 0) <= x"0" & latency_max_out(27 downto 0);
snmp_array_o(10)(31 downto 0) <= x"0" & latency_min_out(27 downto 0);
snmp_array_o(4 )(31 downto 0) <= x"0" & latency_max_out(27 downto 0);
snmp_array_o(5 )(31 downto 0) <= x"0" & latency_min_out(27 downto 0);
snmp_array_o(0) (31 downto 2) <= (others => '0');
snmp_array_o(4 )(31 downto c_cw) <= (others => '0');
snmp_array_o(5 )(31 downto c_cw) <= (others => '0');
snmp_array_o(6 )(31 downto c_cw) <= (others => '0');
snmp_array_o(7 )(31 downto c_cw) <= (others => '0');
snmp_array_o(8 )(31 downto c_cw) <= (others => '0');
CNT_SINGLE_WORD_gen: if(c_aw < 33) generate
snmp_array_o(11)(c_aw-1 downto 0) <= latency_acc_out;
snmp_array_o(11)(31 downto c_aw) <= (others => '0');
CNT_SINGLE_WORD_gen: if(c_cw < 33) generate
snmp_array_o(6 )(c_cw-1 downto 0) <= sent_frame_cnt_out;
snmp_array_o(6 )(31 downto c_cw) <= (others => '0');
snmp_array_o(7 )(31 downto 0) <= (others => '0');
snmp_array_o(8 )(c_cw-1 downto 0) <= rcvd_frame_cnt_out;
snmp_array_o(8 )(31 downto c_cw) <= (others => '0');
snmp_array_o(9 )(31 downto 0) <= (others => '0');
snmp_array_o(10)(c_cw-1 downto 0) <= lost_frame_cnt_out;
snmp_array_o(10)(31 downto c_cw) <= (others => '0');
snmp_array_o(11)(31 downto 0) <= (others => '0');
snmp_array_o(12)(c_cw-1 downto 0) <= lost_block_cnt_out;
snmp_array_o(12)(31 downto c_cw) <= (others => '0');
snmp_array_o(13)(31 downto 0) <= (others => '0');
snmp_array_o(14)(c_cw-1 downto 0) <= latency_cnt_out;
snmp_array_o(14)(31 downto c_cw) <= (others => '0');
snmp_array_o(15)(31 downto 0) <= (others => '0');
end generate;
CNT_TWO_WORDs_gen: if(c_aw > 32) generate
snmp_array_o(11)(31 downto 0) <= latency_acc_out(31 downto 0);
snmp_array_o(12)(c_aw-32-1 downto 0) <= latency_acc_out(c_aw-1 downto 32) ;
snmp_array_o(12)(31 downto c_aw-32) <= (others => '0');
ACC_SINGLE_WORD_gen: if(c_aw < 33) generate
snmp_array_o(16)(c_aw-1 downto 0) <= latency_acc_out;
snmp_array_o(16)(31 downto c_aw) <= (others => '0');
snmp_array_o(17)(31 downto 0) <= (others => '0');
end generate;
---
CNT_TWO_WORDs_gen: if(c_cw > 32) generate
snmp_array_o(6 )(31 downto 0) <= sent_frame_cnt_out(31 downto 0);
snmp_array_o(7 )(c_cw-32-1 downto 0) <= sent_frame_cnt_out(c_cw-1 downto 32);
snmp_array_o(7 )(31 downto c_cw-32) <= (others => '0');
snmp_array_o(8 )(31 downto 0) <= rcvd_frame_cnt_out(31 downto 0);
snmp_array_o(9 )(c_cw-32-1 downto 0) <= rcvd_frame_cnt_out(c_cw-1 downto 32);
snmp_array_o(9 )(31 downto c_cw-32) <= (others => '0');
snmp_array_o(10)(31 downto 0) <= lost_frame_cnt_out(31 downto 0);
snmp_array_o(11)(c_cw-32-1 downto 0) <= lost_frame_cnt_out(c_cw-1 downto 32);
snmp_array_o(11 )(31 downto c_cw-32) <= (others => '0');
snmp_array_o(12)(31 downto 0) <= lost_block_cnt_out(31 downto 0);
snmp_array_o(13)(c_cw-32-1 downto 0) <= lost_block_cnt_out(c_cw-1 downto 32);
snmp_array_o(13 )(31 downto c_cw-32) <= (others => '0');
snmp_array_o(14)(31 downto 0) <= latency_cnt_out(31 downto 0);
snmp_array_o(15)(c_cw-32-1 downto 0) <= latency_cnt_out(c_cw-1 downto 32);
snmp_array_o(15 )(31 downto c_cw-32) <= (others => '0');
end generate;
ACC_TWO_WORDs_gen: if(c_aw > 32) generate
snmp_array_o(16)(31 downto 0) <= latency_acc_out(31 downto 0);
snmp_array_o(17)(c_aw-32-1 downto 0) <= latency_acc_out(c_aw-1 downto 32) ;
snmp_array_o(17)(31 downto c_aw-32) <= (others => '0');
end generate;
end rtl;
modules/wr_streamers/xrx_streamers_stats.vhd
View file @ 8bdb4344
......@@ -49,7 +49,7 @@ entity xrx_streamers_stats is
generic (
-- Width of frame counters
g_cnt_width : integer := 32; -- minimum 15 bits, max 32
g_cnt_width : integer := 50; -- min:15, max:64, 50 bits should be ok for 50 years
g_acc_width : integer := 64 -- max value 64
);
port (
......
modules/wr_streamers/xwr_streamers.vhd
View file @ 8bdb4344
......@@ -80,8 +80,8 @@ entity xwr_streamers is
-- Statistics config
-----------------------------------------------------------------------------------------
-- width of counters: frame rx/tx/lost, block lost, counter of accumuted latency
-- (minimum 15 bits, max 32)
g_stats_cnt_width : integer := 32;
-- (min:15, max:64, 50 bits should be ok for 50 years)
g_stats_cnt_width : integer := 50;
-- width of latency accumulator (max value 64)
g_stats_acc_width : integer := 64;
-----------------------------------------------------------------------------------------
......@@ -157,8 +157,8 @@ entity xwr_streamers is
wb_slave_i : in t_wishbone_slave_in := cc_dummy_slave_in;
wb_slave_o : out t_wishbone_slave_out;
snmp_array_o : out t_generic_word_array(c_WR_TRANS_ARR_SIZE_OUT-1 downto 0);
snmp_array_i : in t_generic_word_array(c_WR_TRANS_ARR_SIZE_IN -1 downto 0);
snmp_array_o : out t_generic_word_array(c_WR_STREAMERS_ARR_SIZE_OUT-1 downto 0);
snmp_array_i : in t_generic_word_array(c_WR_STREAMERS_ARR_SIZE_IN -1 downto 0);
-----------------------------------------------------------------------------------------
-- Transmission and Reception configuration
......@@ -180,7 +180,12 @@ architecture rtl of xwr_streamers is
signal wb_regs_slave_out : t_wishbone_slave_out;
signal tx_frame : std_logic;
signal reset_time_tai : std_logic_vector(39 downto 0);
signal latency_acc : std_logic_vector(63 downto 0);
signal latency_acc : std_logic_vector(g_stats_acc_width-1 downto 0);
signal latency_cnt : std_logic_vector(g_stats_cnt_width-1 downto 0);
signal sent_frame_cnt_out : std_logic_vector(g_stats_cnt_width-1 downto 0);
signal rcvd_frame_cnt_out : std_logic_vector(g_stats_cnt_width-1 downto 0);
signal lost_frame_cnt_out : std_logic_vector(g_stats_cnt_width-1 downto 0);
signal lost_block_cnt_out : std_logic_vector(g_stats_cnt_width-1 downto 0);
signal rx_valid : std_logic;
signal rx_latency_valid : std_logic;
......@@ -193,6 +198,9 @@ architecture rtl of xwr_streamers is
signal tx_streamer_cfg : t_tx_streamer_cfg;
signal rx_streamer_cfg : t_rx_streamer_cfg;
-- for code cleanness
constant c_cw : integer := g_stats_cnt_width;
constant c_aw : integer := g_stats_acc_width;
begin
-------------------------------------------------------------------------------------------
......@@ -302,22 +310,39 @@ begin
snapshot_ena_i => from_wb.sscr1_snapshot_stats_o,
reset_time_tai_o => reset_time_tai,
reset_time_cycles_o => to_wb.sscr1_rst_ts_cyc_i,
sent_frame_cnt_o => to_wb.tx_stat_tx_sent_cnt_i,
rcvd_frame_cnt_o => to_wb.rx_stat1_rx_rcvd_cnt_i,
lost_frame_cnt_o => to_wb.rx_stat2_rx_loss_cnt_i,
lost_block_cnt_o => to_wb.rx_stat8_rx_lost_block_cnt_i,
latency_cnt_o => to_wb.rx_stat7_rx_latency_acc_cnt_i,
sent_frame_cnt_o => sent_frame_cnt_out,
rcvd_frame_cnt_o => rcvd_frame_cnt_out,
lost_frame_cnt_o => lost_frame_cnt_out,
lost_block_cnt_o => lost_block_cnt_out,
latency_cnt_o => latency_cnt,
latency_acc_o => latency_acc,
latency_max_o => to_wb.rx_stat3_rx_latency_max_i,
latency_min_o => to_wb.rx_stat4_rx_latency_min_i,
latency_max_o => to_wb.rx_stat0_rx_latency_max_i,
latency_min_o => to_wb.rx_stat1_rx_latency_min_i,
latency_acc_overflow_o => to_wb.sscr1_rx_latency_acc_overflow_i,
snmp_array_o => snmp_array_o(c_STREAMERS_ARR_SIZE_OUT-1 downto 0),
snmp_array_o => snmp_array_o(c_WRS_STATS_ARR_SIZE_OUT-1 downto 0),
snmp_array_i => snmp_array_i
);
to_wb.sscr2_rst_ts_tai_lsb_i <= reset_time_tai(31 downto 0);
to_wb.rx_stat5_rx_latency_acc_lsb_i <= latency_acc(31 downto 0);
to_wb.rx_stat6_rx_latency_acc_msb_i <= latency_acc(63 downto 32);
to_wb.sscr2_rst_ts_tai_lsb_i <= reset_time_tai(31 downto 0);
to_wb.sscr3_rst_ts_tai_msb_i <= reset_time_tai(39 downto 32);
assert (g_stats_acc_width <= 64 and g_stats_acc_width > 32)
report "g_stats_acc_width (c_aw) must be between 33 and 64" severity error;
assert (g_stats_cnt_width <= 64 and g_stats_cnt_width > 32)
report "g_stats_cnt_width (c_cw) must be between 33 and 64" severity error;
to_wb.tx_stat2_tx_sent_cnt_lsb_i <= sent_frame_cnt_out(31 downto 0);
to_wb.tx_stat3_tx_sent_cnt_msb_i (c_cw-32-1 downto 0) <= sent_frame_cnt_out(c_cw-1 downto 32);
to_wb.rx_stat4_rx_rcvd_cnt_lsb_i <= rcvd_frame_cnt_out(31 downto 0);
to_wb.rx_stat5_rx_rcvd_cnt_msb_i (c_cw-32-1 downto 0) <= rcvd_frame_cnt_out(c_cw-1 downto 32);
to_wb.rx_stat6_rx_loss_cnt_lsb_i <= lost_frame_cnt_out(31 downto 0);
to_wb.rx_stat7_rx_loss_cnt_msb_i (c_cw-32-1 downto 0) <= lost_frame_cnt_out(c_cw-1 downto 32);
to_wb.rx_stat8_rx_lost_block_cnt_lsb_i <= lost_block_cnt_out(31 downto 0);
to_wb.rx_stat9_rx_lost_block_cnt_msb_i (c_cw-32-1 downto 0) <= lost_block_cnt_out(c_cw-1 downto 32);
to_wb.rx_stat10_rx_latency_acc_lsb_i <= latency_acc (31 downto 0);
to_wb.rx_stat11_rx_latency_acc_msb_i (c_aw-32-1 downto 0) <= latency_acc (c_aw-1 downto 32);
to_wb.rx_stat12_rx_latency_acc_cnt_lsb_i <= latency_cnt (31 downto 0);
to_wb.rx_stat13_rx_latency_acc_cnt_msb_i(c_cw-32-1 downto 0) <= latency_cnt (c_cw-1 downto 32);
rx_data_o <= rx_data;
rx_valid_o <= rx_valid;
......@@ -345,7 +370,7 @@ begin
port map (
rst_n_i => rst_n_i,
clk_sys_i => clk_sys_i,
wb_adr_i => wb_regs_slave_in.adr(4 downto 0),
wb_adr_i => wb_regs_slave_in.adr(5 downto 0),
wb_dat_i => wb_regs_slave_in.dat,
wb_dat_o => wb_regs_slave_out.dat,
wb_cyc_i => wb_regs_slave_in.cyc,
......@@ -387,7 +412,8 @@ begin
end if;
end process;
snmp_array_o(c_STREAMERS_ARR_SIZE_OUT) <= dbg_word;
snmp_array_o(c_WRS_STATS_ARR_SIZE_OUT) <= dbg_word;
snmp_array_o(c_WRS_STATS_ARR_SIZE_OUT+1) <= x"DEADBEEF";
to_wb.dbg_data_i <= dbg_word;
to_wb.dummy_dummy_i <= x"DEADBEEF";
......
sim/wr_streamers_wb.svh
View file @ 8bdb4344
`define ADDR_WR_STREAMERS_SSCR1 7'h0
`define ADDR_WR_STREAMERS_SSCR1 8'h0
`define WR_STREAMERS_SSCR1_RST_STATS_OFFSET 0
`define WR_STREAMERS_SSCR1_RST_STATS 32'h00000001
`define WR_STREAMERS_SSCR1_RST_SEQ_ID_OFFSET 1
......@@ -9,81 +9,99 @@
`define WR_STREAMERS_SSCR1_RX_LATENCY_ACC_OVERFLOW 32'h00000008
`define WR_STREAMERS_SSCR1_RST_TS_CYC_OFFSET 4
`define WR_STREAMERS_SSCR1_RST_TS_CYC 32'hfffffff0
`define ADDR_WR_STREAMERS_SSCR2 7'h4
`define ADDR_WR_STREAMERS_SSCR2 8'h4
`define WR_STREAMERS_SSCR2_RST_TS_TAI_LSB_OFFSET 0
`define WR_STREAMERS_SSCR2_RST_TS_TAI_LSB 32'hffffffff
`define ADDR_WR_STREAMERS_TX_STAT 7'h8
`define WR_STREAMERS_TX_STAT_TX_SENT_CNT_OFFSET 0
`define WR_STREAMERS_TX_STAT_TX_SENT_CNT 32'hffffffff
`define ADDR_WR_STREAMERS_RX_STAT1 7'hc
`define WR_STREAMERS_RX_STAT1_RX_RCVD_CNT_OFFSET 0
`define WR_STREAMERS_RX_STAT1_RX_RCVD_CNT 32'hffffffff
`define ADDR_WR_STREAMERS_RX_STAT2 7'h10
`define WR_STREAMERS_RX_STAT2_RX_LOSS_CNT_OFFSET 0
`define WR_STREAMERS_RX_STAT2_RX_LOSS_CNT 32'hffffffff
`define ADDR_WR_STREAMERS_RX_STAT3 7'h14
`define WR_STREAMERS_RX_STAT3_RX_LATENCY_MAX_OFFSET 0
`define WR_STREAMERS_RX_STAT3_RX_LATENCY_MAX 32'h0fffffff
`define ADDR_WR_STREAMERS_RX_STAT4 7'h18
`define WR_STREAMERS_RX_STAT4_RX_LATENCY_MIN_OFFSET 0
`define WR_STREAMERS_RX_STAT4_RX_LATENCY_MIN 32'h0fffffff
`define ADDR_WR_STREAMERS_RX_STAT5 7'h1c
`define WR_STREAMERS_RX_STAT5_RX_LATENCY_ACC_LSB_OFFSET 0
`define WR_STREAMERS_RX_STAT5_RX_LATENCY_ACC_LSB 32'hffffffff
`define ADDR_WR_STREAMERS_RX_STAT6 7'h20
`define WR_STREAMERS_RX_STAT6_RX_LATENCY_ACC_MSB_OFFSET 0
`define WR_STREAMERS_RX_STAT6_RX_LATENCY_ACC_MSB 32'hffffffff
`define ADDR_WR_STREAMERS_RX_STAT7 7'h24
`define WR_STREAMERS_RX_STAT7_RX_LATENCY_ACC_CNT_OFFSET 0
`define WR_STREAMERS_RX_STAT7_RX_LATENCY_ACC_CNT 32'hffffffff
`define ADDR_WR_STREAMERS_RX_STAT8 7'h28
`define WR_STREAMERS_RX_STAT8_RX_LOST_BLOCK_CNT_OFFSET 0
`define WR_STREAMERS_RX_STAT8_RX_LOST_BLOCK_CNT 32'hffffffff
`define ADDR_WR_STREAMERS_TX_CFG0 7'h2c
`define ADDR_WR_STREAMERS_SSCR3 8'h8
`define WR_STREAMERS_SSCR3_RST_TS_TAI_MSB_OFFSET 0
`define WR_STREAMERS_SSCR3_RST_TS_TAI_MSB 32'h000000ff
`define ADDR_WR_STREAMERS_RX_STAT0 8'hc
`define WR_STREAMERS_RX_STAT0_RX_LATENCY_MAX_OFFSET 0
`define WR_STREAMERS_RX_STAT0_RX_LATENCY_MAX 32'h0fffffff
`define ADDR_WR_STREAMERS_RX_STAT1 8'h10
`define WR_STREAMERS_RX_STAT1_RX_LATENCY_MIN_OFFSET 0
`define WR_STREAMERS_RX_STAT1_RX_LATENCY_MIN 32'h0fffffff
`define ADDR_WR_STREAMERS_TX_STAT2 8'h14
`define WR_STREAMERS_TX_STAT2_TX_SENT_CNT_LSB_OFFSET 0
`define WR_STREAMERS_TX_STAT2_TX_SENT_CNT_LSB 32'hffffffff
`define ADDR_WR_STREAMERS_TX_STAT3 8'h18
`define WR_STREAMERS_TX_STAT3_TX_SENT_CNT_MSB_OFFSET 0
`define WR_STREAMERS_TX_STAT3_TX_SENT_CNT_MSB 32'hffffffff
`define ADDR_WR_STREAMERS_RX_STAT4 8'h1c
`define WR_STREAMERS_RX_STAT4_RX_RCVD_CNT_LSB_OFFSET 0
`define WR_STREAMERS_RX_STAT4_RX_RCVD_CNT_LSB 32'hffffffff
`define ADDR_WR_STREAMERS_RX_STAT5 8'h20
`define WR_STREAMERS_RX_STAT5_RX_RCVD_CNT_MSB_OFFSET 0
`define WR_STREAMERS_RX_STAT5_RX_RCVD_CNT_MSB 32'hffffffff
`define ADDR_WR_STREAMERS_RX_STAT6 8'h24
`define WR_STREAMERS_RX_STAT6_RX_LOSS_CNT_LSB_OFFSET 0
`define WR_STREAMERS_RX_STAT6_RX_LOSS_CNT_LSB 32'hffffffff
`define ADDR_WR_STREAMERS_RX_STAT7 8'h28
`define WR_STREAMERS_RX_STAT7_RX_LOSS_CNT_MSB_OFFSET 0
`define WR_STREAMERS_RX_STAT7_RX_LOSS_CNT_MSB 32'hffffffff
`define ADDR_WR_STREAMERS_RX_STAT8 8'h2c
`define WR_STREAMERS_RX_STAT8_RX_LOST_BLOCK_CNT_LSB_OFFSET 0
`define WR_STREAMERS_RX_STAT8_RX_LOST_BLOCK_CNT_LSB 32'hffffffff
`define ADDR_WR_STREAMERS_RX_STAT9 8'h30
`define WR_STREAMERS_RX_STAT9_RX_LOST_BLOCK_CNT_MSB_OFFSET 0
`define WR_STREAMERS_RX_STAT9_RX_LOST_BLOCK_CNT_MSB 32'hffffffff
`define ADDR_WR_STREAMERS_RX_STAT10 8'h34
`define WR_STREAMERS_RX_STAT10_RX_LATENCY_ACC_LSB_OFFSET 0
`define WR_STREAMERS_RX_STAT10_RX_LATENCY_ACC_LSB 32'hffffffff
`define ADDR_WR_STREAMERS_RX_STAT11 8'h38
`define WR_STREAMERS_RX_STAT11_RX_LATENCY_ACC_MSB_OFFSET 0
`define WR_STREAMERS_RX_STAT11_RX_LATENCY_ACC_MSB 32'hffffffff
`define ADDR_WR_STREAMERS_RX_STAT12 8'h3c
`define WR_STREAMERS_RX_STAT12_RX_LATENCY_ACC_CNT_LSB_OFFSET 0
`define WR_STREAMERS_RX_STAT12_RX_LATENCY_ACC_CNT_LSB 32'hffffffff
`define ADDR_WR_STREAMERS_RX_STAT13 8'h40
`define WR_STREAMERS_RX_STAT13_RX_LATENCY_ACC_CNT_MSB_OFFSET 0
`define WR_STREAMERS_RX_STAT13_RX_LATENCY_ACC_CNT_MSB 32'hffffffff
`define ADDR_WR_STREAMERS_TX_CFG0 8'h44
`define WR_STREAMERS_TX_CFG0_ETHERTYPE_OFFSET 0
`define WR_STREAMERS_TX_CFG0_ETHERTYPE 32'h0000ffff
`define ADDR_WR_STREAMERS_TX_CFG1 7'h30
`define ADDR_WR_STREAMERS_TX_CFG1 8'h48
`define WR_STREAMERS_TX_CFG1_MAC_LOCAL_LSB_OFFSET 0
`define WR_STREAMERS_TX_CFG1_MAC_LOCAL_LSB 32'hffffffff
`define ADDR_WR_STREAMERS_TX_CFG2 7'h34
`define ADDR_WR_STREAMERS_TX_CFG2 8'h4c
`define WR_STREAMERS_TX_CFG2_MAC_LOCAL_MSB_OFFSET 0
`define WR_STREAMERS_TX_CFG2_MAC_LOCAL_MSB 32'h0000ffff
`define ADDR_WR_STREAMERS_TX_CFG3 7'h38
`define ADDR_WR_STREAMERS_TX_CFG3 8'h50
`define WR_STREAMERS_TX_CFG3_MAC_TARGET_LSB_OFFSET 0
`define WR_STREAMERS_TX_CFG3_MAC_TARGET_LSB 32'hffffffff
`define ADDR_WR_STREAMERS_TX_CFG4 7'h3c
`define ADDR_WR_STREAMERS_TX_CFG4 8'h54
`define WR_STREAMERS_TX_CFG4_MAC_TARGET_MSB_OFFSET 0
`define WR_STREAMERS_TX_CFG4_MAC_TARGET_MSB 32'h0000ffff
`define ADDR_WR_STREAMERS_TX_CFG5 7'h40
`define ADDR_WR_STREAMERS_TX_CFG5 8'h58
`define WR_STREAMERS_TX_CFG5_QTAG_ENA_OFFSET 0
`define WR_STREAMERS_TX_CFG5_QTAG_ENA 32'h00000001
`define WR_STREAMERS_TX_CFG5_QTAG_VID_OFFSET 8
`define WR_STREAMERS_TX_CFG5_QTAG_VID 32'h000fff00
`define WR_STREAMERS_TX_CFG5_QTAG_PRIO_OFFSET 24
`define WR_STREAMERS_TX_CFG5_QTAG_PRIO 32'h07000000
`define ADDR_WR_STREAMERS_RX_CFG0 7'h44
`define ADDR_WR_STREAMERS_RX_CFG0 8'h5c
`define WR_STREAMERS_RX_CFG0_ETHERTYPE_OFFSET 0
`define WR_STREAMERS_RX_CFG0_ETHERTYPE 32'h0000ffff
`define WR_STREAMERS_RX_CFG0_ACCEPT_BROADCAST_OFFSET 16
`define WR_STREAMERS_RX_CFG0_ACCEPT_BROADCAST 32'h00010000
`define WR_STREAMERS_RX_CFG0_FILTER_REMOTE_OFFSET 17
`define WR_STREAMERS_RX_CFG0_FILTER_REMOTE 32'h00020000
`define ADDR_WR_STREAMERS_RX_CFG1 7'h48
`define ADDR_WR_STREAMERS_RX_CFG1 8'h60
`define WR_STREAMERS_RX_CFG1_MAC_LOCAL_LSB_OFFSET 0
`define WR_STREAMERS_RX_CFG1_MAC_LOCAL_LSB 32'hffffffff
`define ADDR_WR_STREAMERS_RX_CFG2 7'h4c
`define ADDR_WR_STREAMERS_RX_CFG2 8'h64
`define WR_STREAMERS_RX_CFG2_MAC_LOCAL_MSB_OFFSET 0
`define WR_STREAMERS_RX_CFG2_MAC_LOCAL_MSB 32'h0000ffff
`define ADDR_WR_STREAMERS_RX_CFG3 7'h50
`define ADDR_WR_STREAMERS_RX_CFG3 8'h68
`define WR_STREAMERS_RX_CFG3_MAC_REMOTE_LSB_OFFSET 0
`define WR_STREAMERS_RX_CFG3_MAC_REMOTE_LSB 32'hffffffff
`define ADDR_WR_STREAMERS_RX_CFG4 7'h54
`define ADDR_WR_STREAMERS_RX_CFG4 8'h6c
`define WR_STREAMERS_RX_CFG4_MAC_REMOTE_MSB_OFFSET 0
`define WR_STREAMERS_RX_CFG4_MAC_REMOTE_MSB 32'h0000ffff
`define ADDR_WR_STREAMERS_RX_CFG5 7'h58
`define ADDR_WR_STREAMERS_RX_CFG5 8'h70
`define WR_STREAMERS_RX_CFG5_FIXED_LATENCY_OFFSET 0
`define WR_STREAMERS_RX_CFG5_FIXED_LATENCY 32'h0fffffff
`define ADDR_WR_STREAMERS_CFG 7'h5c
`define ADDR_WR_STREAMERS_CFG 8'h74
`define WR_STREAMERS_CFG_OR_TX_ETHTYPE_OFFSET 0
`define WR_STREAMERS_CFG_OR_TX_ETHTYPE 32'h00000001
`define WR_STREAMERS_CFG_OR_TX_MAC_LOC_OFFSET 1
......@@ -104,12 +122,12 @@
`define WR_STREAMERS_CFG_OR_RX_FTR_REMOTE 32'h00100000
`define WR_STREAMERS_CFG_OR_RX_FIX_LAT_OFFSET 21
`define WR_STREAMERS_CFG_OR_RX_FIX_LAT 32'h00200000
`define ADDR_WR_STREAMERS_DBG_CTRL 7'h60
`define ADDR_WR_STREAMERS_DBG_CTRL 8'h78
`define WR_STREAMERS_DBG_CTRL_MUX_OFFSET 0
`define WR_STREAMERS_DBG_CTRL_MUX 32'h00000001
`define WR_STREAMERS_DBG_CTRL_START_BYTE_OFFSET 8
`define WR_STREAMERS_DBG_CTRL_START_BYTE 32'h0000ff00
`define ADDR_WR_STREAMERS_DBG_DATA 7'h64
`define ADDR_WR_STREAMERS_DUMMY 7'h68
`define ADDR_WR_STREAMERS_DBG_DATA 8'h7c
`define ADDR_WR_STREAMERS_DUMMY 8'h80
`define WR_STREAMERS_DUMMY_DUMMY_OFFSET 0
`define WR_STREAMERS_DUMMY_DUMMY 32'hffffffff
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