Commit 8e00d090 authored by Maciej Lipinski's avatar Maciej Lipinski Committed by Grzegorz Daniluk

[wrpc/diags] added writing of WRPC diagnostics to dedicated WB registers

this is an hdl part of new (additional) diagnostics for WR PTP Core.
It allows to access diagnostics values through WB registers (e.g. PCI
bus). This is useful for integration of WR with CERN cotrols infrastructure,
such as FESA. It allows the host machine (of SPEC/SVEC/etc) to easily
access information about the health of WR PTP Core.
parent 3e2985c4
......@@ -6,5 +6,8 @@ files = [ "xwr_core.vhd",
"wb_reset.vhd",
"wrc_syscon_wb.vhd",
"wrc_syscon_pkg.vhd",
"xwr_syscon_wb.vhd"];
"xwr_syscon_wb.vhd",
"wrc_diags_wb.vhd",
"wrc_diags_pkg.vhd",
"xwrc_diags_wb.vhd"];
......@@ -2,3 +2,4 @@
mkdir -p doc
wbgen2 -D ./doc/wrc_syscon.html -p wrc_syscon_pkg.vhd -H record -V wrc_syscon_wb.vhd -C wrc_syscon_regs.h --cstyle defines --lang vhdl -K ../../sim/wrc_syscon_regs.vh wrc_syscon_wb.wb
wbgen2 -D ./doc/wrc_diags.html -p wrc_diags_pkg.vhd -H record -V wrc_diags_wb.vhd -C wrc_diags_regs.h --cstyle defines --lang vhdl -K ../../sim/wrc_diags_regs.vh wrc_diags_wb.wb
\ No newline at end of file
......@@ -5,7 +5,7 @@
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-02-02
-- Last update: 2017-03-10
-- Last update: 2017-04-25
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -396,15 +396,15 @@ architecture struct of wr_core is
-----------------------------------------------------------------------------
--WB Peripherials
-----------------------------------------------------------------------------
signal periph_slave_i : t_wishbone_slave_in_array(0 to 2);
signal periph_slave_o : t_wishbone_slave_out_array(0 to 2);
signal periph_slave_i : t_wishbone_slave_in_array(0 to 3);
signal periph_slave_o : t_wishbone_slave_out_array(0 to 3);
signal sysc_in_regs : t_sysc_in_registers;
signal sysc_out_regs : t_sysc_out_registers;
-----------------------------------------------------------------------------
--WB Secondary Crossbar
-----------------------------------------------------------------------------
constant c_secbar_layout : t_sdb_record_array(7 downto 0) :=
constant c_secbar_layout : t_sdb_record_array(8 downto 0) :=
(0 => f_sdb_embed_device(c_xwr_mini_nic_sdb, x"00000000"),
1 => f_sdb_embed_device(c_xwr_endpoint_sdb, x"00000100"),
2 => f_sdb_embed_device(c_xwr_softpll_ng_sdb, x"00000200"),
......@@ -412,15 +412,16 @@ architecture struct of wr_core is
4 => f_sdb_embed_device(c_wrc_periph0_sdb, x"00000400"), -- Syscon
5 => f_sdb_embed_device(c_wrc_periph1_sdb, x"00000500"), -- UART
6 => f_sdb_embed_device(c_wrc_periph2_sdb, x"00000600"), -- 1-Wire
7 => f_sdb_embed_device(g_aux_sdb, x"00000700") -- aux WB bus
7 => f_sdb_embed_device(g_aux_sdb, x"00000700"), -- aux WB bus
8 => f_sdb_embed_device(c_wrc_periph4_sdb, x"00000800") -- WRPC diag registers
);
constant c_secbar_sdb_address : t_wishbone_address := x"00000800";
constant c_secbar_sdb_address : t_wishbone_address := x"00000C00";
constant c_secbar_bridge_sdb : t_sdb_bridge :=
f_xwb_bridge_layout_sdb(true, c_secbar_layout, c_secbar_sdb_address);
signal secbar_master_i : t_wishbone_master_in_array(7 downto 0);
signal secbar_master_o : t_wishbone_master_out_array(7 downto 0);
signal secbar_master_i : t_wishbone_master_in_array(8 downto 0);
signal secbar_master_o : t_wishbone_master_out_array(8 downto 0);
-----------------------------------------------------------------------------
--WB intercon
......@@ -1017,7 +1018,7 @@ begin
WB_SECONDARY_CON : xwb_sdb_crossbar
generic map(
g_num_masters => 1,
g_num_slaves => 8,
g_num_slaves => 9,
g_registered => true,
g_wraparound => true,
g_layout => c_secbar_layout,
......@@ -1046,9 +1047,11 @@ begin
secbar_master_i(4) <= periph_slave_o(0);
secbar_master_i(5) <= periph_slave_o(1);
secbar_master_i(6) <= periph_slave_o(2);
secbar_master_i(8) <= periph_slave_o(3);
periph_slave_i(0) <= secbar_master_o(4);
periph_slave_i(1) <= secbar_master_o(5);
periph_slave_i(2) <= secbar_master_o(6);
periph_slave_i(3) <= secbar_master_o(8);
aux_adr_o <= secbar_master_o(7).adr;
......
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for WR Core Diagnostics
---------------------------------------------------------------------------------------
-- File : wrc_diags_pkg.vhd
-- Author : auto-generated by wbgen2 from wrc_diags_wb.wb
-- Created : Tue Apr 25 12:14:42 2017
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_diags_wb.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package wrc_diags_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_wrc_diags_in_registers is record
ctrl_data_valid_i : std_logic;
wdiag_sstat_wr_mode_i : std_logic;
wdiag_sstat_servostate_i : std_logic_vector(3 downto 0);
wdiag_pstat_link_i : std_logic;
wdiag_pstat_locked_i : std_logic;
wdiag_ptpstat_ptpstate_i : std_logic_vector(7 downto 0);
wdiag_astat_aux_i : std_logic_vector(7 downto 0);
wdiag_txfcnt_i : std_logic_vector(31 downto 0);
wdiag_rxfcnt_i : std_logic_vector(31 downto 0);
wdiag_sec_msb_i : std_logic_vector(31 downto 0);
wdiag_sec_lsb_i : std_logic_vector(31 downto 0);
wdiag_ns_i : std_logic_vector(31 downto 0);
wdiag_mu_msb_i : std_logic_vector(31 downto 0);
wdiag_mu_lsb_i : std_logic_vector(31 downto 0);
wdiag_dms_msb_i : std_logic_vector(31 downto 0);
wdiag_dms_lsb_i : std_logic_vector(31 downto 0);
wdiag_asym_i : std_logic_vector(31 downto 0);
wdiag_cko_i : std_logic_vector(31 downto 0);
wdiag_setp_i : std_logic_vector(31 downto 0);
wdiag_ucnt_i : std_logic_vector(31 downto 0);
wdiag_temp_i : std_logic_vector(31 downto 0);
end record;
constant c_wrc_diags_in_registers_init_value: t_wrc_diags_in_registers := (
ctrl_data_valid_i => '0',
wdiag_sstat_wr_mode_i => '0',
wdiag_sstat_servostate_i => (others => '0'),
wdiag_pstat_link_i => '0',
wdiag_pstat_locked_i => '0',
wdiag_ptpstat_ptpstate_i => (others => '0'),
wdiag_astat_aux_i => (others => '0'),
wdiag_txfcnt_i => (others => '0'),
wdiag_rxfcnt_i => (others => '0'),
wdiag_sec_msb_i => (others => '0'),
wdiag_sec_lsb_i => (others => '0'),
wdiag_ns_i => (others => '0'),
wdiag_mu_msb_i => (others => '0'),
wdiag_mu_lsb_i => (others => '0'),
wdiag_dms_msb_i => (others => '0'),
wdiag_dms_lsb_i => (others => '0'),
wdiag_asym_i => (others => '0'),
wdiag_cko_i => (others => '0'),
wdiag_setp_i => (others => '0'),
wdiag_ucnt_i => (others => '0'),
wdiag_temp_i => (others => '0')
);
-- Output registers (WB slave -> user design)
type t_wrc_diags_out_registers is record
ctrl_data_snapshot_o : std_logic;
end record;
constant c_wrc_diags_out_registers_init_value: t_wrc_diags_out_registers := (
ctrl_data_snapshot_o => '0'
);
function "or" (left, right: t_wrc_diags_in_registers) return t_wrc_diags_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;
package body wrc_diags_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if x = '1' then
return '1';
else
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_wrc_diags_in_registers) return t_wrc_diags_in_registers is
variable tmp: t_wrc_diags_in_registers;
begin
tmp.ctrl_data_valid_i := f_x_to_zero(left.ctrl_data_valid_i) or f_x_to_zero(right.ctrl_data_valid_i);
tmp.wdiag_sstat_wr_mode_i := f_x_to_zero(left.wdiag_sstat_wr_mode_i) or f_x_to_zero(right.wdiag_sstat_wr_mode_i);
tmp.wdiag_sstat_servostate_i := f_x_to_zero(left.wdiag_sstat_servostate_i) or f_x_to_zero(right.wdiag_sstat_servostate_i);
tmp.wdiag_pstat_link_i := f_x_to_zero(left.wdiag_pstat_link_i) or f_x_to_zero(right.wdiag_pstat_link_i);
tmp.wdiag_pstat_locked_i := f_x_to_zero(left.wdiag_pstat_locked_i) or f_x_to_zero(right.wdiag_pstat_locked_i);
tmp.wdiag_ptpstat_ptpstate_i := f_x_to_zero(left.wdiag_ptpstat_ptpstate_i) or f_x_to_zero(right.wdiag_ptpstat_ptpstate_i);
tmp.wdiag_astat_aux_i := f_x_to_zero(left.wdiag_astat_aux_i) or f_x_to_zero(right.wdiag_astat_aux_i);
tmp.wdiag_txfcnt_i := f_x_to_zero(left.wdiag_txfcnt_i) or f_x_to_zero(right.wdiag_txfcnt_i);
tmp.wdiag_rxfcnt_i := f_x_to_zero(left.wdiag_rxfcnt_i) or f_x_to_zero(right.wdiag_rxfcnt_i);
tmp.wdiag_sec_msb_i := f_x_to_zero(left.wdiag_sec_msb_i) or f_x_to_zero(right.wdiag_sec_msb_i);
tmp.wdiag_sec_lsb_i := f_x_to_zero(left.wdiag_sec_lsb_i) or f_x_to_zero(right.wdiag_sec_lsb_i);
tmp.wdiag_ns_i := f_x_to_zero(left.wdiag_ns_i) or f_x_to_zero(right.wdiag_ns_i);
tmp.wdiag_mu_msb_i := f_x_to_zero(left.wdiag_mu_msb_i) or f_x_to_zero(right.wdiag_mu_msb_i);
tmp.wdiag_mu_lsb_i := f_x_to_zero(left.wdiag_mu_lsb_i) or f_x_to_zero(right.wdiag_mu_lsb_i);
tmp.wdiag_dms_msb_i := f_x_to_zero(left.wdiag_dms_msb_i) or f_x_to_zero(right.wdiag_dms_msb_i);
tmp.wdiag_dms_lsb_i := f_x_to_zero(left.wdiag_dms_lsb_i) or f_x_to_zero(right.wdiag_dms_lsb_i);
tmp.wdiag_asym_i := f_x_to_zero(left.wdiag_asym_i) or f_x_to_zero(right.wdiag_asym_i);
tmp.wdiag_cko_i := f_x_to_zero(left.wdiag_cko_i) or f_x_to_zero(right.wdiag_cko_i);
tmp.wdiag_setp_i := f_x_to_zero(left.wdiag_setp_i) or f_x_to_zero(right.wdiag_setp_i);
tmp.wdiag_ucnt_i := f_x_to_zero(left.wdiag_ucnt_i) or f_x_to_zero(right.wdiag_ucnt_i);
tmp.wdiag_temp_i := f_x_to_zero(left.wdiag_temp_i) or f_x_to_zero(right.wdiag_temp_i);
return tmp;
end function;
end package body;
This diff is collapsed.
-- -*- Mode: LUA; tab-width: 2 -*-
peripheral {
name = "WR Core Diagnostics";
description = "Diagnostics information accessible via WR";
prefix = "wrc_diags";
hdl_entity = "wrc_diags_wb";
reg {
name = "Ctrl";
prefix = "CTRL";
field {
name = "WR DIAG data valid";
prefix = "DATA_VALID";
description = "0: valid\1:transcient";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "WR DIAG data snapshot";
prefix = "DATA_SNAPSHOT";
description = "1: snapshot data (data in registers will not change aveter VALID becomes true)";
type = BIT;
access_bus = WRITE_READ;
access_dev = READ_ONLY;
align = 8;
};
};
reg {
name = "WRPC Diag: servo status";
prefix = "WDIAG_SSTAT";
field {
name = "WR valid";
prefix = "wr_mode";
description = "0: not valid\1:valid";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Servo State";
prefix = "servostate";
description = "0: Uninitialized\
1: SYNC_NSEC\
2: SYNC_TAI\
3: SYNC_PHASE\
4: TRACK_PHASE\
5: WAIT_OFFSET_STABLE";
type = SLV;
size = 4;
align = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "WRPC Diag: Port status";
prefix = "WDIAG_PSTAT";
field {
name = "Link Status";
prefix = "link";
description = "0: link down\
1: link up";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "PLL Locked";
prefix = "locked";
description = "0: not locked\
1: locked";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "WRPC Diag: PTP state";
prefix = "WDIAG_PTPSTAT";
field {
name = "PTP State";
prefix = "ptpstate";
description = "0: NONE\
1: PPS_INITIALIZING\
2: PPS_FAULTY\
3: disabled\
4: PPS_LISTENING\
5: PPS_PRE_MASTER\
6: PPS_MASTER\
7: PPS_PASSIVE\
8: PPS_UNCALIBRATED\
9: PPS_SLAVE\
100-116: WR STATES\
see: ppsi/proto-ext-whiterabbit/wr-constants.h\
ppsi/include/ppsi/ieee1588_types.h";
type = SLV;
size = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "WRPC Diag: AUX state";
prefix = "WDIAG_ASTAT";
field {
name = "AUX channel";
prefix = "aux";
description = "A vector of bits, one bit per channel\
0: not valid\
1:valid";
type = SLV;
size = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "WRPC Diag: Tx PTP Frame cnts";
prefix = "WDIAG_TXFCNT";
description = "Number of transmitted PTP Frames";
field {
name = "Data";
size = 32;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "WRPC Diag: Rx PTP Frame cnts";
description = "Number of received PTP Frames";
prefix = "WDIAG_RXFCNT";
field {
name = "Data";
size = 32;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "WRPC Diag:local time [msb of s]";
prefix = "WDIAG_SEC_MSB";
description = "Local Time expressed in seconds since epoch (TAI)";
field {
name = "Data";
size = 32;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "WRPC Diag: local time [lsb of s]";
description = "Local Time expressed in seconds since epoch (TAI)";
prefix = "WDIAG_SEC_LSB";
field {
name = "Data";
size = 32;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "WRPC Diag: local time [ns]";
description = "Nanoseconds part of the Local Time expressed in seconds since epoch (TAI)";
prefix = "WDIAG_NS";
field {
name = "Data";
size = 32;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "WRPC Diag: Round trip (mu) [msb of ps]";
prefix = "WDIAG_MU_MSB";
field {
name = "Data";
size = 32;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "WRPC Diag: Round trip (mu) [lsb of ps]";
prefix = "WDIAG_MU_LSB";
field {
name = "Data";
size = 32;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "WRPC Diag: Master-slave delay (dms) [msb of ps]";
prefix = "WDIAG_DMS_MSB";
field {
name = "Data";
size = 32;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "WRPC Diag: Master-slave delay (dms) [lsb of ps]";
prefix = "WDIAG_DMS_LSB";
field {
name = "Data";
size = 32;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "WRPC Diag: Total link asymmetry [ps]";
prefix = "WDIAG_ASYM";
field {
name = "Data";
size = 32;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "WRPC Diag: Clock offset (cko) [ps]";
prefix = "WDIAG_CKO";
field {
name = "Data";
size = 32;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "WRPC Diag: Phase setpoint (setp) [ps]";
prefix = "WDIAG_SETP";
field {
name = "Data";
size = 32;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "WRPC Diag: Update counter (ucnt)";
prefix = "WDIAG_UCNT";
field {
name = "Data";
size = 32;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "WRPC Diag: Board temperature [C degree]";
prefix = "WDIAG_TEMP";
field {
name = "Data";
size = 32;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
};
......@@ -6,12 +6,12 @@
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-04-04
-- Last update: 2017-02-03
-- Last update: 2017-04-25
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- WRC_PERIPH integrates WRC_SYSCON, UART/VUART, 1-Wire Master
-- WRC_PERIPH integrates WRC_SYSCON, UART/VUART, 1-Wire Master, WRPC_DIAGS
--
-------------------------------------------------------------------------------
-- Copyright (c) 2011 Grzegorz Daniluk
......@@ -30,6 +30,7 @@ library work;
use work.wrcore_pkg.all;
use work.wishbone_pkg.all;
use work.sysc_wbgen2_pkg.all;
use work.wrc_diags_wbgen2_pkg.all;
entity wrc_periph is
generic(
......@@ -69,8 +70,8 @@ entity wrc_periph is
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic;
slave_i : in t_wishbone_slave_in_array(0 to 2);
slave_o : out t_wishbone_slave_out_array(0 to 2);
slave_i : in t_wishbone_slave_in_array(0 to 3);
slave_o : out t_wishbone_slave_out_array(0 to 3);
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
......@@ -108,7 +109,8 @@ architecture struct of wrc_periph is
signal diag_dat : std_logic_vector(31 downto 0);
signal diag_out_regs : t_generic_word_array(g_diag_rw_size - 1 downto 0);
signal diag_in : t_generic_word_array(g_diag_ro_size + g_diag_rw_size-1 downto 0);
signal wrpc_diag_regs_in : t_wrc_diags_in_registers;
signal wrpc_diag_regs_out : t_wrc_diags_out_registers;
begin
......@@ -423,4 +425,56 @@ begin
owr_i => owr_i
);
--------------------------------------
-- WRPC Diags
--------------------------------------
-- access through WB (PCI/VME/application) to diagnostics of WRPC
DIAGS: xwr_diags_wb
generic map(
g_interface_mode => PIPELINED,
g_address_granularity => BYTE
)
port map(
rst_n_i => rst_n_i,
clk_sys_i => clk_sys_i,
slave_i => slave_i(3),
slave_o => slave_o(3),
regs_i => wrpc_diag_regs_in,
regs_o => wrpc_diag_regs_out
);
-- the information written to syscon WB registers by LM32 are available to the
-- user via diag WB registers
-- It might look strange that we use two WB modules for that. Since both LM32
-- and user application need to access these registers through the same
-- wishbone interface we would needed these registers to be R/W. By creating
-- another module (xwr_diags_wb) we make read-only registers to be read by
-- the external tool. We want to minimize the possibility of user application
-- overwriting these values, thus we want them to be read-only.
sysc_regs_i.wdiag_ctrl_data_snapshot_i <= wrpc_diag_regs_out.ctrl_data_snapshot_o;
wrpc_diag_regs_in.ctrl_data_valid_i <= sysc_regs_o.wdiag_ctrl_data_valid_o;
wrpc_diag_regs_in.wdiag_sstat_wr_mode_i <= sysc_regs_o.wdiag_sstat_wr_mode_o;
wrpc_diag_regs_in.wdiag_sstat_servostate_i <= sysc_regs_o.wdiag_sstat_servostate_o;
wrpc_diag_regs_in.wdiag_pstat_link_i <= sysc_regs_o.wdiag_pstat_link_o;
wrpc_diag_regs_in.wdiag_pstat_locked_i <= sysc_regs_o.wdiag_pstat_locked_o;
wrpc_diag_regs_in.wdiag_ptpstat_ptpstate_i <= sysc_regs_o.wdiag_ptpstat_ptpstate_o;
wrpc_diag_regs_in.wdiag_astat_aux_i <= sysc_regs_o.wdiag_astat_aux_o;
wrpc_diag_regs_in.wdiag_txfcnt_i <= sysc_regs_o.wdiag_txfcnt_o;
wrpc_diag_regs_in.wdiag_rxfcnt_i <= sysc_regs_o.wdiag_rxfcnt_o;
wrpc_diag_regs_in.wdiag_sec_msb_i <= sysc_regs_o.wdiag_sec_msb_o;
wrpc_diag_regs_in.wdiag_sec_lsb_i <= sysc_regs_o.wdiag_sec_lsb_o;
wrpc_diag_regs_in.wdiag_ns_i <= sysc_regs_o.wdiag_ns_o;
wrpc_diag_regs_in.wdiag_mu_msb_i <= sysc_regs_o.wdiag_mu_msb_o;
wrpc_diag_regs_in.wdiag_mu_lsb_i <= sysc_regs_o.wdiag_mu_lsb_o;
wrpc_diag_regs_in.wdiag_dms_msb_i <= sysc_regs_o.wdiag_dms_msb_o;
wrpc_diag_regs_in.wdiag_dms_lsb_i <= sysc_regs_o.wdiag_dms_lsb_o;
wrpc_diag_regs_in.wdiag_asym_i <= sysc_regs_o.wdiag_asym_o;
wrpc_diag_regs_in.wdiag_cko_i <= sysc_regs_o.wdiag_cko_o;
wrpc_diag_regs_in.wdiag_setp_i <= sysc_regs_o.wdiag_setp_o;
wrpc_diag_regs_in.wdiag_ucnt_i <= sysc_regs_o.wdiag_ucnt_o;
wrpc_diag_regs_in.wdiag_temp_i <= sysc_regs_o.wdiag_temp_o;
end struct;
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wrc_syscon_pkg.vhd
-- Author : auto-generated by wbgen2 from wrc_syscon_wb.wb
-- Created : Mon Jul 11 14:59:51 2016
-- Created : Tue Apr 25 12:14:41 2017
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
......@@ -40,6 +40,7 @@ package sysc_wbgen2_pkg is
diag_nw_ro_i : std_logic_vector(15 downto 0);
diag_cr_adr_i : std_logic_vector(15 downto 0);
diag_dat_i : std_logic_vector(31 downto 0);
wdiag_ctrl_data_snapshot_i : std_logic;
end record;
constant c_sysc_in_registers_init_value: t_sysc_in_registers := (
......@@ -62,7 +63,8 @@ package sysc_wbgen2_pkg is
diag_nw_rw_i => (others => '0'),
diag_nw_ro_i => (others => '0'),
diag_cr_adr_i => (others => '0'),
diag_dat_i => (others => '0')
diag_dat_i => (others => '0'),
wdiag_ctrl_data_snapshot_i => '0'
);
-- Output registers (WB slave -> user design)
......@@ -103,6 +105,27 @@ package sysc_wbgen2_pkg is
diag_cr_rw_o : std_logic;
diag_dat_o : std_logic_vector(31 downto 0);
diag_dat_load_o : std_logic;
wdiag_ctrl_data_valid_o : std_logic;
wdiag_sstat_wr_mode_o : std_logic;
wdiag_sstat_servostate_o : std_logic_vector(3 downto 0);
wdiag_pstat_link_o : std_logic;
wdiag_pstat_locked_o : std_logic;
wdiag_ptpstat_ptpstate_o : std_logic_vector(7 downto 0);
wdiag_astat_aux_o : std_logic_vector(7 downto 0);
wdiag_txfcnt_o : std_logic_vector(31 downto 0);
wdiag_rxfcnt_o : std_logic_vector(31 downto 0);
wdiag_sec_msb_o : std_logic_vector(31 downto 0);
wdiag_sec_lsb_o : std_logic_vector(31 downto 0);
wdiag_ns_o : std_logic_vector(31 downto 0);
wdiag_mu_msb_o : std_logic_vector(31 downto 0);
wdiag_mu_lsb_o : std_logic_vector(31 downto 0);
wdiag_dms_msb_o : std_logic_vector(31 downto 0);
wdiag_dms_lsb_o : std_logic_vector(31 downto 0);
wdiag_asym_o : std_logic_vector(31 downto 0);
wdiag_cko_o : std_logic_vector(31 downto 0);
wdiag_setp_o : std_logic_vector(31 downto 0);
wdiag_ucnt_o : std_logic_vector(31 downto 0);
wdiag_temp_o : std_logic_vector(31 downto 0);
end record;
constant c_sysc_out_registers_init_value: t_sysc_out_registers := (
......@@ -140,7 +163,28 @@ package sysc_wbgen2_pkg is
diag_cr_adr_load_o => '0',
diag_cr_rw_o => '0',
diag_dat_o => (others => '0'),
diag_dat_load_o => '0'
diag_dat_load_o => '0',
wdiag_ctrl_data_valid_o => '0',
wdiag_sstat_wr_mode_o => '0',
wdiag_sstat_servostate_o => (others => '0'),
wdiag_pstat_link_o => '0',
wdiag_pstat_locked_o => '0',
wdiag_ptpstat_ptpstate_o => (others => '0'),
wdiag_astat_aux_o => (others => '0'),
wdiag_txfcnt_o => (others => '0'),
wdiag_rxfcnt_o => (others => '0'),
wdiag_sec_msb_o => (others => '0'),
wdiag_sec_lsb_o => (others => '0'),
wdiag_ns_o => (others => '0'),
wdiag_mu_msb_o => (others => '0'),
wdiag_mu_lsb_o => (others => '0'),
wdiag_dms_msb_o => (others => '0'),
wdiag_dms_lsb_o => (others => '0'),
wdiag_asym_o => (others => '0'),
wdiag_cko_o => (others => '0'),
wdiag_setp_o => (others => '0'),
wdiag_ucnt_o => (others => '0'),
wdiag_temp_o => (others => '0')
);
function "or" (left, right: t_sysc_in_registers) return t_sysc_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
......@@ -160,10 +204,10 @@ function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if x(i) = '1' then
tmp(i):= '1';
else
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
......@@ -191,6 +235,7 @@ tmp.diag_nw_rw_i := f_x_to_zero(left.diag_nw_rw_i) or f_x_to_zero(right.diag_nw_
tmp.diag_nw_ro_i := f_x_to_zero(left.diag_nw_ro_i) or f_x_to_zero(right.diag_nw_ro_i);
tmp.diag_cr_adr_i := f_x_to_zero(left.diag_cr_adr_i) or f_x_to_zero(right.diag_cr_adr_i);
tmp.diag_dat_i := f_x_to_zero(left.diag_dat_i) or f_x_to_zero(right.diag_dat_i);
tmp.wdiag_ctrl_data_snapshot_i := f_x_to_zero(left.wdiag_ctrl_data_snapshot_i) or f_x_to_zero(right.wdiag_ctrl_data_snapshot_i);
return tmp;
end function;
end package body;
......@@ -3,7 +3,7 @@
* File : wrc_syscon_regs.h
* Author : auto-generated by wbgen2 from wrc_syscon_wb.wb
* Created : Mon Jul 11 14:59:51 2016
* Created : Tue Apr 25 12:14:41 2017
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
......@@ -14,7 +14,11 @@
#ifndef __WBGEN2_REGDEFS_WRC_SYSCON_WB_WB
#define __WBGEN2_REGDEFS_WRC_SYSCON_WB_WB
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <inttypes.h>
#endif
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
......@@ -176,6 +180,77 @@
#define SYSC_DIAG_CR_RW WBGEN2_GEN_MASK(31, 1)
/* definitions for register: User Diag: data to read/write */
/* definitions for register: WRPC Diag: ctrl */
/* definitions for field: WR DIAG data valid in reg: WRPC Diag: ctrl */
#define SYSC_WDIAG_CTRL_DATA_VALID WBGEN2_GEN_MASK(0, 1)
/* definitions for field: WR DIAG data snapshot in reg: WRPC Diag: ctrl */
#define SYSC_WDIAG_CTRL_DATA_SNAPSHOT WBGEN2_GEN_MASK(8, 1)
/* definitions for register: WRPC Diag: servo status */
/* definitions for field: WR valid in reg: WRPC Diag: servo status */
#define SYSC_WDIAG_SSTAT_WR_MODE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Servo State in reg: WRPC Diag: servo status */
#define SYSC_WDIAG_SSTAT_SERVOSTATE_MASK WBGEN2_GEN_MASK(8, 4)
#define SYSC_WDIAG_SSTAT_SERVOSTATE_SHIFT 8
#define SYSC_WDIAG_SSTAT_SERVOSTATE_W(value) WBGEN2_GEN_WRITE(value, 8, 4)
#define SYSC_WDIAG_SSTAT_SERVOSTATE_R(reg) WBGEN2_GEN_READ(reg, 8, 4)
/* definitions for register: WRPC Diag: Port status */
/* definitions for field: Link Status in reg: WRPC Diag: Port status */
#define SYSC_WDIAG_PSTAT_LINK WBGEN2_GEN_MASK(0, 1)
/* definitions for field: PLL Locked in reg: WRPC Diag: Port status */
#define SYSC_WDIAG_PSTAT_LOCKED WBGEN2_GEN_MASK(1, 1)
/* definitions for register: WRPC Diag: PTP state */
/* definitions for field: PTP State in reg: WRPC Diag: PTP state */
#define SYSC_WDIAG_PTPSTAT_PTPSTATE_MASK WBGEN2_GEN_MASK(0, 8)
#define SYSC_WDIAG_PTPSTAT_PTPSTATE_SHIFT 0
#define SYSC_WDIAG_PTPSTAT_PTPSTATE_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define SYSC_WDIAG_PTPSTAT_PTPSTATE_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* definitions for register: WRPC Diag: AUX state */
/* definitions for field: AUX channel in reg: WRPC Diag: AUX state */
#define SYSC_WDIAG_ASTAT_AUX_MASK WBGEN2_GEN_MASK(0, 8)
#define SYSC_WDIAG_ASTAT_AUX_SHIFT 0
#define SYSC_WDIAG_ASTAT_AUX_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define SYSC_WDIAG_ASTAT_AUX_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* definitions for register: WRPC Diag: Tx PTP Frame cnts */
/* definitions for register: WRPC Diag: Rx PTP Frame cnts */
/* definitions for register: WRPC Diag:local time [msb of s] */
/* definitions for register: WRPC Diag: local time [lsb of s] */
/* definitions for register: WRPC Diag: local time [ns] */
/* definitions for register: WRPC Diag: Round trip (mu) [msb of ps] */
/* definitions for register: WRPC Diag: Round trip (mu) [lsb of ps] */
/* definitions for register: WRPC Diag: Master-slave delay (dms) [msb of ps] */
/* definitions for register: WRPC Diag: Master-slave delay (dms) [lsb of ps] */
/* definitions for register: WRPC Diag: Total link asymmetry [ps] */
/* definitions for register: WRPC Diag: Clock offset (cko) [ps] */
/* definitions for register: WRPC Diag: Phase setpoint (setp) [ps] */
/* definitions for register: WRPC Diag: Update counter (ucnt) */
/* definitions for register: WRPC Diag: Board temperature [C degree] */
/* [0x0]: REG Syscon reset register */
#define SYSC_REG_RSTR 0x00000000
/* [0x4]: REG GPIO Set/Readback Register */
......@@ -196,4 +271,42 @@
#define SYSC_REG_DIAG_CR 0x00000020
/* [0x24]: REG User Diag: data to read/write */
#define SYSC_REG_DIAG_DAT 0x00000024
/* [0x28]: REG WRPC Diag: ctrl */
#define SYSC_REG_WDIAG_CTRL 0x00000028
/* [0x2c]: REG WRPC Diag: servo status */
#define SYSC_REG_WDIAG_SSTAT 0x0000002c
/* [0x30]: REG WRPC Diag: Port status */
#define SYSC_REG_WDIAG_PSTAT 0x00000030
/* [0x34]: REG WRPC Diag: PTP state */
#define SYSC_REG_WDIAG_PTPSTAT 0x00000034
/* [0x38]: REG WRPC Diag: AUX state */
#define SYSC_REG_WDIAG_ASTAT 0x00000038
/* [0x3c]: REG WRPC Diag: Tx PTP Frame cnts */
#define SYSC_REG_WDIAG_TXFCNT 0x0000003c
/* [0x40]: REG WRPC Diag: Rx PTP Frame cnts */
#define SYSC_REG_WDIAG_RXFCNT 0x00000040
/* [0x44]: REG WRPC Diag:local time [msb of s] */
#define SYSC_REG_WDIAG_SEC_MSB 0x00000044
/* [0x48]: REG WRPC Diag: local time [lsb of s] */
#define SYSC_REG_WDIAG_SEC_LSB 0x00000048
/* [0x4c]: REG WRPC Diag: local time [ns] */
#define SYSC_REG_WDIAG_NS 0x0000004c
/* [0x50]: REG WRPC Diag: Round trip (mu) [msb of ps] */
#define SYSC_REG_WDIAG_MU_MSB 0x00000050
/* [0x54]: REG WRPC Diag: Round trip (mu) [lsb of ps] */
#define SYSC_REG_WDIAG_MU_LSB 0x00000054
/* [0x58]: REG WRPC Diag: Master-slave delay (dms) [msb of ps] */
#define SYSC_REG_WDIAG_DMS_MSB 0x00000058
/* [0x5c]: REG WRPC Diag: Master-slave delay (dms) [lsb of ps] */
#define SYSC_REG_WDIAG_DMS_LSB 0x0000005c
/* [0x60]: REG WRPC Diag: Total link asymmetry [ps] */
#define SYSC_REG_WDIAG_ASYM 0x00000060
/* [0x64]: REG WRPC Diag: Clock offset (cko) [ps] */
#define SYSC_REG_WDIAG_CKO 0x00000064
/* [0x68]: REG WRPC Diag: Phase setpoint (setp) [ps] */
#define SYSC_REG_WDIAG_SETP 0x00000068
/* [0x6c]: REG WRPC Diag: Update counter (ucnt) */
#define SYSC_REG_WDIAG_UCNT 0x0000006c
/* [0x70]: REG WRPC Diag: Board temperature [C degree] */
#define SYSC_REG_WDIAG_TEMP 0x00000070
#endif
This diff is collapsed.
......@@ -393,6 +393,276 @@ peripheral {
load = LOAD_EXT;
};
};
reg {
name = "WRPC Diag: ctrl";
prefix = "WDIAG_CTRL";
field {
name = "WR DIAG data valid";
prefix = "DATA_VALID";
description = "0: valid\
1: transcient";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "WR DIAG data snapshot";
prefix = "DATA_SNAPSHOT";
description = "1: snapshot data (data in registers will not change aveter VALID becomes true)";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
align = 8;
};
};
reg {
name = "WRPC Diag: servo status";
prefix = "WDIAG_SSTAT";
field {
name = "WR valid";
prefix = "wr_mode";
description = "0: not valid\1:valid";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Servo State";
prefix = "servostate";
description = "0: Uninitialized\
1: SYNC_NSEC\
2: SYNC_TAI\
3: SYNC_PHASE\
4: TRACK_PHASE\
5: WAIT_OFFSET_STABLE";
type = SLV;
size = 4;
align = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "WRPC Diag: Port status";
prefix = "WDIAG_PSTAT";
field {
name = "Link Status";
prefix = "link";
description = "0: link down\
1: link up";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "PLL Locked";
prefix = "locked";
description = "0: not locked\
1: locked";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "WRPC Diag: PTP state";
prefix = "WDIAG_PTPSTAT";
field {
name = "PTP State";
prefix = "ptpstate";
description = "0: NONE\
1: PPS_INITIALIZING\
2: PPS_FAULTY\
3: disabled\
4: PPS_LISTENING\
5: PPS_PRE_MASTER\
6: PPS_MASTER\
7: PPS_PASSIVE\
8: PPS_UNCALIBRATED\
9: PPS_SLAVE\
100-116: WR STATES\
see: ppsi/proto-ext-whiterabbit/wr-constants.h\
ppsi/include/ppsi/ieee1588_types.h";
type = SLV;
size = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "WRPC Diag: AUX state";
prefix = "WDIAG_ASTAT";
field {
name = "AUX channel";
prefix = "aux";
description = "A vector of bits, one bit per channel\
0: not valid\
1:valid";
type = SLV;
size = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "WRPC Diag: Tx PTP Frame cnts";
prefix = "WDIAG_TXFCNT";
description = "Number of transmitted PTP Frames";
field {
name = "Data";
size = 32;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "WRPC Diag: Rx PTP Frame cnts";
description = "Number of received PTP Frames";
prefix = "WDIAG_RXFCNT";
field {
name = "Data";
size = 32;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "WRPC Diag:local time [msb of s]";
prefix = "WDIAG_SEC_MSB";
description = "Local Time expressed in seconds since epoch (TAI)";
field {
name = "Data";
size = 32;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "WRPC Diag: local time [lsb of s]";
description = "Local Time expressed in seconds since epoch (TAI)";
prefix = "WDIAG_SEC_LSB";
field {
name = "Data";
size = 32;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "WRPC Diag: local time [ns]";
description = "Nanoseconds part of the Local Time expressed in seconds since epoch (TAI)";
prefix = "WDIAG_NS";
field {
name = "Data";
size = 32;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "WRPC Diag: Round trip (mu) [msb of ps]";
prefix = "WDIAG_MU_MSB";
field {
name = "Data";
size = 32;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "WRPC Diag: Round trip (mu) [lsb of ps]";
prefix = "WDIAG_MU_LSB";
field {
name = "Data";
size = 32;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "WRPC Diag: Master-slave delay (dms) [msb of ps]";
prefix = "WDIAG_DMS_MSB";
field {
name = "Data";
size = 32;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "WRPC Diag: Master-slave delay (dms) [lsb of ps]";
prefix = "WDIAG_DMS_LSB";
field {
name = "Data";
size = 32;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "WRPC Diag: Total link asymmetry [ps]";
prefix = "WDIAG_ASYM";
field {
name = "Data";
size = 32;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "WRPC Diag: Clock offset (cko) [ps]";
prefix = "WDIAG_CKO";
field {
name = "Data";
size = 32;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "WRPC Diag: Phase setpoint (setp) [ps]";
prefix = "WDIAG_SETP";
field {
name = "Data";
size = 32;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "WRPC Diag: Update counter (ucnt)";
prefix = "WDIAG_UCNT";
field {
name = "Data";
size = 32;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "WRPC Diag: Board temperature [C degree]";
prefix = "WDIAG_TEMP";
field {
name = "Data";
size = 32;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
};
......@@ -5,6 +5,7 @@ library work;
use work.genram_pkg.all;
use work.wishbone_pkg.all;
use work.sysc_wbgen2_pkg.all;
use work.wrc_diags_wbgen2_pkg.all;
use work.wr_fabric_pkg.all;
use work.endpoint_pkg.all;
use work.softpll_pkg.all;
......@@ -124,6 +125,23 @@ package wrcore_pkg is
);
end component;
component xwr_diags_wb is
generic(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD
);
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
regs_i : in t_wrc_diags_in_registers;
regs_o : out t_wrc_diags_out_registers
);
end component;
constant c_wrc_periph0_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
......@@ -189,6 +207,22 @@ package wrcore_pkg is
date => x"20120615",
name => "WR-Periph-AuxWB ")));
constant c_wrc_periph4_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"779c5446",
version => x"00000001",
date => x"20170424",
name => "WR-Periph-WRPC-DIAG")));
component wrc_periph is
generic(
g_phys_uart : boolean := true;
......@@ -224,8 +258,8 @@ package wrcore_pkg is
spi_ncs_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic;
slave_i : in t_wishbone_slave_in_array(0 to 2);
slave_o : out t_wishbone_slave_out_array(0 to 2);
slave_i : in t_wishbone_slave_in_array(0 to 3);
slave_o : out t_wishbone_slave_out_array(0 to 3);
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
owr_pwren_o : out std_logic_vector(1 downto 0);
......
......@@ -6,7 +6,7 @@
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-02-02
-- Last update: 2017-02-01
-- Last update: 2017-04-01
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......
......@@ -50,7 +50,7 @@ architecture syn of xwr_syscon_wb is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(3 downto 0);
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
......@@ -96,7 +96,7 @@ begin
port map(
rst_n_i => rst_n_i,
clk_sys_i => clk_sys_i,
wb_adr_i => wb_in.adr(3 downto 0),
wb_adr_i => wb_in.adr(4 downto 0),
wb_dat_i => wb_in.dat,
wb_dat_o => wb_out.dat,
wb_cyc_i => wb_in.cyc,
......
-------------------------------------------------------------------------------
-- Title : WR PTP Core Diagnostics
-- Project : WhiteRabbit
-------------------------------------------------------------------------------
-- File : xwrc_diags_wb.vhd
-- Author : Maciej Lipinski <maciej.lipinski@cern.ch>
-- Company : CERN
-- Created : 2017-04-24
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- Wrapper for wrc_diags_wb. Uses types instead of std_logic signals and
-- can use pipelined or classic wishbone.
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2017 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.wishbone_pkg.all;
use work.wrc_diags_wbgen2_pkg.all;
entity xwr_diags_wb is
generic(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD
);
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
regs_i : in t_wrc_diags_in_registers;
regs_o : out t_wrc_diags_out_registers
);
end xwr_diags_wb;
architecture syn of xwr_diags_wb is
component wrc_diags_wb is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
regs_i : in t_wrc_diags_in_registers;
regs_o : out t_wrc_diags_out_registers
);
end component;
signal wb_out : t_wishbone_slave_out;
signal wb_in : t_wishbone_slave_in;
begin
U_Adapter : wb_slave_adapter
generic map(
g_master_use_struct => true,
g_master_mode => CLASSIC,
g_master_granularity => WORD,
g_slave_use_struct => false,
g_slave_mode => g_interface_mode,
g_slave_granularity => g_address_granularity)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
master_i => wb_out,
master_o => wb_in,
sl_adr_i => slave_i.adr,
sl_dat_i => slave_i.dat,
sl_sel_i => slave_i.sel,
sl_cyc_i => slave_i.cyc,
sl_stb_i => slave_i.stb,
sl_we_i => slave_i.we,
sl_dat_o => slave_o.dat,
sl_ack_o => slave_o.ack,
sl_stall_o => slave_o.stall);
WRAPPED_DIAGS: wrc_diags_wb
port map(
rst_n_i => rst_n_i,
clk_sys_i => clk_sys_i,
wb_adr_i => wb_in.adr(4 downto 0),
wb_dat_i => wb_in.dat,
wb_dat_o => wb_out.dat,
wb_cyc_i => wb_in.cyc,
wb_sel_i => wb_in.sel,
wb_stb_i => wb_in.stb,
wb_we_i => wb_in.we,
wb_ack_o => wb_out.ack,
wb_stall_o => wb_out.stall,
regs_i => regs_i,
regs_o => regs_o);
slave_o.err <= '0';
slave_o.rty <= '0';
end syn;
`define ADDR_WRC_DIAGS_CTRL 7'h0
`define WRC_DIAGS_CTRL_DATA_VALID_OFFSET 0
`define WRC_DIAGS_CTRL_DATA_VALID 32'h00000001
`define WRC_DIAGS_CTRL_DATA_SNAPSHOT_OFFSET 8
`define WRC_DIAGS_CTRL_DATA_SNAPSHOT 32'h00000100
`define ADDR_WRC_DIAGS_WDIAG_SSTAT 7'h4
`define WRC_DIAGS_WDIAG_SSTAT_WR_MODE_OFFSET 0
`define WRC_DIAGS_WDIAG_SSTAT_WR_MODE 32'h00000001
`define WRC_DIAGS_WDIAG_SSTAT_SERVOSTATE_OFFSET 8
`define WRC_DIAGS_WDIAG_SSTAT_SERVOSTATE 32'h00000f00
`define ADDR_WRC_DIAGS_WDIAG_PSTAT 7'h8
`define WRC_DIAGS_WDIAG_PSTAT_LINK_OFFSET 0
`define WRC_DIAGS_WDIAG_PSTAT_LINK 32'h00000001
`define WRC_DIAGS_WDIAG_PSTAT_LOCKED_OFFSET 1
`define WRC_DIAGS_WDIAG_PSTAT_LOCKED 32'h00000002
`define ADDR_WRC_DIAGS_WDIAG_PTPSTAT 7'hc
`define WRC_DIAGS_WDIAG_PTPSTAT_PTPSTATE_OFFSET 0
`define WRC_DIAGS_WDIAG_PTPSTAT_PTPSTATE 32'h000000ff
`define ADDR_WRC_DIAGS_WDIAG_ASTAT 7'h10
`define WRC_DIAGS_WDIAG_ASTAT_AUX_OFFSET 0
`define WRC_DIAGS_WDIAG_ASTAT_AUX 32'h000000ff
`define ADDR_WRC_DIAGS_WDIAG_TXFCNT 7'h14
`define ADDR_WRC_DIAGS_WDIAG_RXFCNT 7'h18
`define ADDR_WRC_DIAGS_WDIAG_SEC_MSB 7'h1c
`define ADDR_WRC_DIAGS_WDIAG_SEC_LSB 7'h20
`define ADDR_WRC_DIAGS_WDIAG_NS 7'h24
`define ADDR_WRC_DIAGS_WDIAG_MU_MSB 7'h28
`define ADDR_WRC_DIAGS_WDIAG_MU_LSB 7'h2c
`define ADDR_WRC_DIAGS_WDIAG_DMS_MSB 7'h30
`define ADDR_WRC_DIAGS_WDIAG_DMS_LSB 7'h34
`define ADDR_WRC_DIAGS_WDIAG_ASYM 7'h38
`define ADDR_WRC_DIAGS_WDIAG_CKO 7'h3c
`define ADDR_WRC_DIAGS_WDIAG_SETP 7'h40
`define ADDR_WRC_DIAGS_WDIAG_UCNT 7'h44
`define ADDR_WRC_DIAGS_WDIAG_TEMP 7'h48
`define ADDR_SYSC_RSTR 6'h0
`define ADDR_SYSC_RSTR 7'h0
`define SYSC_RSTR_TRIG_OFFSET 0
`define SYSC_RSTR_TRIG 32'h0fffffff
`define SYSC_RSTR_RST_OFFSET 28
`define SYSC_RSTR_RST 32'h10000000
`define ADDR_SYSC_GPSR 6'h4
`define ADDR_SYSC_GPSR 7'h4
`define SYSC_GPSR_LED_STAT_OFFSET 0
`define SYSC_GPSR_LED_STAT 32'h00000001
`define SYSC_GPSR_LED_LINK_OFFSET 1
......@@ -32,7 +32,7 @@
`define SYSC_GPSR_SPI_MOSI 32'h00001000
`define SYSC_GPSR_SPI_MISO_OFFSET 13
`define SYSC_GPSR_SPI_MISO 32'h00002000
`define ADDR_SYSC_GPCR 6'h8
`define ADDR_SYSC_GPCR 7'h8
`define SYSC_GPCR_LED_STAT_OFFSET 0
`define SYSC_GPCR_LED_STAT 32'h00000001
`define SYSC_GPCR_LED_LINK_OFFSET 1
......@@ -51,28 +51,63 @@
`define SYSC_GPCR_SPI_CS 32'h00000800
`define SYSC_GPCR_SPI_MOSI_OFFSET 12
`define SYSC_GPCR_SPI_MOSI 32'h00001000
`define ADDR_SYSC_HWFR 6'hc
`define ADDR_SYSC_HWFR 7'hc
`define SYSC_HWFR_MEMSIZE_OFFSET 0
`define SYSC_HWFR_MEMSIZE 32'h0000000f
`define ADDR_SYSC_TCR 6'h10
`define ADDR_SYSC_TCR 7'h10
`define SYSC_TCR_TDIV_OFFSET 0
`define SYSC_TCR_TDIV 32'h00000fff
`define SYSC_TCR_ENABLE_OFFSET 31
`define SYSC_TCR_ENABLE 32'h80000000
`define ADDR_SYSC_TVR 6'h14
`define ADDR_SYSC_DIAG_INFO 6'h18
`define ADDR_SYSC_TVR 7'h14
`define ADDR_SYSC_DIAG_INFO 7'h18
`define SYSC_DIAG_INFO_VER_OFFSET 0
`define SYSC_DIAG_INFO_VER 32'h0000ffff
`define SYSC_DIAG_INFO_ID_OFFSET 16
`define SYSC_DIAG_INFO_ID 32'hffff0000
`define ADDR_SYSC_DIAG_NW 6'h1c
`define ADDR_SYSC_DIAG_NW 7'h1c
`define SYSC_DIAG_NW_RW_OFFSET 0
`define SYSC_DIAG_NW_RW 32'h0000ffff
`define SYSC_DIAG_NW_RO_OFFSET 16
`define SYSC_DIAG_NW_RO 32'hffff0000
`define ADDR_SYSC_DIAG_CR 6'h20
`define ADDR_SYSC_DIAG_CR 7'h20
`define SYSC_DIAG_CR_ADR_OFFSET 0
`define SYSC_DIAG_CR_ADR 32'h0000ffff
`define SYSC_DIAG_CR_RW_OFFSET 31
`define SYSC_DIAG_CR_RW 32'h80000000
`define ADDR_SYSC_DIAG_DAT 6'h24
`define ADDR_SYSC_DIAG_DAT 7'h24
`define ADDR_SYSC_WDIAG_CTRL 7'h28
`define SYSC_WDIAG_CTRL_DATA_VALID_OFFSET 0
`define SYSC_WDIAG_CTRL_DATA_VALID 32'h00000001
`define SYSC_WDIAG_CTRL_DATA_SNAPSHOT_OFFSET 8
`define SYSC_WDIAG_CTRL_DATA_SNAPSHOT 32'h00000100
`define ADDR_SYSC_WDIAG_SSTAT 7'h2c
`define SYSC_WDIAG_SSTAT_WR_MODE_OFFSET 0
`define SYSC_WDIAG_SSTAT_WR_MODE 32'h00000001
`define SYSC_WDIAG_SSTAT_SERVOSTATE_OFFSET 8
`define SYSC_WDIAG_SSTAT_SERVOSTATE 32'h00000f00
`define ADDR_SYSC_WDIAG_PSTAT 7'h30
`define SYSC_WDIAG_PSTAT_LINK_OFFSET 0
`define SYSC_WDIAG_PSTAT_LINK 32'h00000001
`define SYSC_WDIAG_PSTAT_LOCKED_OFFSET 1
`define SYSC_WDIAG_PSTAT_LOCKED 32'h00000002
`define ADDR_SYSC_WDIAG_PTPSTAT 7'h34
`define SYSC_WDIAG_PTPSTAT_PTPSTATE_OFFSET 0
`define SYSC_WDIAG_PTPSTAT_PTPSTATE 32'h000000ff
`define ADDR_SYSC_WDIAG_ASTAT 7'h38
`define SYSC_WDIAG_ASTAT_AUX_OFFSET 0
`define SYSC_WDIAG_ASTAT_AUX 32'h000000ff
`define ADDR_SYSC_WDIAG_TXFCNT 7'h3c
`define ADDR_SYSC_WDIAG_RXFCNT 7'h40
`define ADDR_SYSC_WDIAG_SEC_MSB 7'h44
`define ADDR_SYSC_WDIAG_SEC_LSB 7'h48
`define ADDR_SYSC_WDIAG_NS 7'h4c
`define ADDR_SYSC_WDIAG_MU_MSB 7'h50
`define ADDR_SYSC_WDIAG_MU_LSB 7'h54
`define ADDR_SYSC_WDIAG_DMS_MSB 7'h58
`define ADDR_SYSC_WDIAG_DMS_LSB 7'h5c
`define ADDR_SYSC_WDIAG_ASYM 7'h60
`define ADDR_SYSC_WDIAG_CKO 7'h64
`define ADDR_SYSC_WDIAG_SETP 7'h68
`define ADDR_SYSC_WDIAG_UCNT 7'h6c
`define ADDR_SYSC_WDIAG_TEMP 7'h70
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