Commit 93d49e1f authored by Grzegorz Daniluk's avatar Grzegorz Daniluk

Revert "hdl: use dual reset async fifos and pulse synchronizers to help with meeting timing"

This reverts commit 9810ef9a.
parent 7a42cf8e
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-02-25
-- Last update: 2018-08-03
-- Last update: 2014-07-15
-- Platform : FPGA-generic
-- Standard : VHDL '93
-------------------------------------------------------------------------------
......@@ -164,15 +164,14 @@ begin -- rtl
data_i => resync_p_a_i,
synced_o => resync_p_dmtd);
U_Sync_Start_Pulse : gc_pulse_synchronizer2
U_Sync_Start_Pulse : gc_pulse_synchronizer
port map (
clk_in_i => clk_sys_i,
rst_in_n_i => rst_n_sysclk_i,
clk_out_i => clk_dmtd_i,
rst_out_n_i => rst_n_dmtdclk_i,
d_ready_o => open,
d_p_i => resync_start_p_i,
q_p_o => resync_start_p_dmtd);
clk_in_i => clk_sys_i,
clk_out_i => clk_dmtd_i,
rst_n_i => rst_n_dmtdclk_i,
d_ready_o => open,
d_p_i => resync_start_p_i,
q_p_o => resync_start_p_dmtd);
U_Sync_Resync_Done : gc_sync_ffs
generic map (
......
......@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-11-18
-- Last update: 2018-08-03
-- Last update: 2012-08-28
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -84,7 +84,7 @@ begin
f_pack_fifo_contents (fab_i, fifo_in, fifo_we, false);
-- Clock adjustment FIFO
U_FIFO : generic_async_fifo_dual_rst
U_FIFO : generic_async_fifo
generic map (
g_data_width => 18,
g_size => g_size,
......@@ -92,13 +92,12 @@ begin
g_almost_full_threshold => g_almostfull_threshold
)
port map (
rst_wr_n_i => rst_n_wr_i,
rst_n_i => rst_n_wr_i,
clk_wr_i => clk_wr_i,
d_i => fifo_in,
we_i => fifo_we,
wr_full_o => full_o,
wr_almost_full_o => almostfull_o,
rst_rd_n_i => rst_n_rd_i,
clk_rd_i => clk_rd_i,
q_o => fifo_out,
rd_i => rx_rdreq,
......
......@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-11-18
-- Last update: 2018-08-03
-- Last update: 2017-02-02
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -360,13 +360,12 @@ begin -- behavioral
end if;
end process;
U_Sync_Done : gc_pulse_synchronizer2
U_Sync_Done : gc_pulse_synchronizer
port map (
clk_in_i => clk_rx_i,
rst_in_n_i => rst_n_rx_i,
clk_out_i => clk_sys_i,
rst_out_n_i => rst_n_sys_i,
d_p_i => done_int,
q_p_o => done_o);
clk_in_i => clk_rx_i,
clk_out_i => clk_sys_i,
rst_n_i => rst_n_rx_i,
d_p_i => done_int,
q_p_o => done_o);
end behavioral;
......@@ -7,7 +7,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2009-06-22
-- Last update: 2018-08-03
-- Last update: 2017-02-03
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
......
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