[WR Streamers/testbench] make the demo work also for synthesiz

by default, the bram content for synthesis is specified. it is only overriden by simulation. In this way, if the top can be both, simulated and synthesized.

[WR Streamers/testbench] make the demo work also for synthesiz
by default, the bram content for synthesis is specified. it is only overriden by simulation. In this way, if the top can be both, simulated and synthesized.
9513a851 · Maciej Lipinski · Grzegorz Daniluk · b66d2b25 · 9513a851 · 9513a851
Commit 9513a851 authored Sep 25, 2017 by Maciej Lipinski Committed by Grzegorz Daniluk Nov 24, 2017
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Showing with 13 additions and 3 deletions

main.sv ..._streamers/streamers-on-spec_trigger-distribution/main.sv +4 -2

spec_top.vhd top/spec_1_1/wr_streamers_demo/spec_top.vhd +9 -1

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--- a/testbench/wr_streamers/streamers-on-spec_trigger-distribution/main.sv
+++ b/testbench/wr_streamers/streamers-on-spec_trigger-distribution/main.sv
@@ -40,7 +40,8 @@ module main;
   // This time we have two SPECs talking to each other in the same testbench
   spec_top
     #(
-       .g_simulation (1)
+       .g_simulation (1),
+       .g_dpram_initf("../../../bin/wrpc/wrc_phy8_sim.bram")
    ) SPEC_A (
           .clk_125m_pllref_p_i (clk_ref),
           .clk_125m_pllref_n_i (~clk_ref),
@@ -64,7 +65,8 @@ module main;

   spec_top
     #(
-       .g_simulation (1)
+       .g_simulation (1),
+       .g_dpram_initf("../../../bin/wrpc/wrc_phy8_sim.bram")
    ) SPEC_B (
           .clk_125m_pllref_p_i (clk_ref),
           .clk_125m_pllref_n_i (~clk_ref),

--- a/top/spec_1_1/wr_streamers_demo/spec_top.vhd
+++ b/top/spec_1_1/wr_streamers_demo/spec_top.vhd
@@ -42,6 +42,14 @@ use work.wishbone_pkg.all;

 entity spec_top is
  generic (
+    -- setting g_dpram_initf to file path will result in syntesis/simulation using the
+    -- content of this file to run LM32 microprocessor
+    -- setting g_dpram_init to empty string (i.e."") will result in synthesis/simulation
+    -- with empty RAM for the LM32 (it will not work until code is loaded)
+    -- NOTE: the path is correct when used from the synthesis folder (this is where
+    --       ISE calls the function to find the file, the path is not correct for where
+    --       this file is stored, i.e. in the top/ folder)
+    g_dpram_initf : string  := "../../../bin/wrpc/wrc_phy8.bram";
    -- Simulation mode enable parameter. Set by default (synthesis) to 0, and
    -- changed to non-zero in the instantiation of the top level DUT in the testbench.
    -- Its purpose is to reduce some internal counters/timeouts to speed up simulations.
@@ -514,7 +522,7 @@ begin
      g_ep_rxbuf_size             => 1024,
      g_tx_runt_padding           => true,
      g_pcs_16bit                 => false,
-      g_dpram_initf               => "../../../bin/wrpc/wrc_phy8_sim.bram",
+      g_dpram_initf               => g_dpram_initf,
 --       g_aux_sdb                   => c_etherbone_sdb, --ML
      g_dpram_size                => 131072/4,
      g_interface_mode            => PIPELINED,