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White Rabbit core collection
Commit 985caf49 authored by li hongming's avatar li hongming
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Merge remote-tracking branch 'origin/wrs-v5.1' into hm-wrsfl

parents 3228a8c9 489a88b2
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Showing with 43 additions and 19 deletions
modules/wr_pps_gen/pps_gen_regs.h
View file @ 985caf49
......@@ -3,7 +3,7 @@
* File : pps_gen_regs.h
* Author : auto-generated by wbgen2 from pps_gen_wb.wb
* Created : Thu Aug 6 16:03:49 2015
* Created : Thu Sep 13 15:39:55 2018
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pps_gen_wb.wb
......@@ -14,7 +14,11 @@
#ifndef __WBGEN2_REGDEFS_PPS_GEN_WB_WB
#define __WBGEN2_REGDEFS_PPS_GEN_WB_WB
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <inttypes.h>
#endif
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
......@@ -80,6 +84,9 @@
/* definitions for field: Set nanoseconds counter in reg: External sync control register */
#define PPSG_ESCR_NSEC_SET WBGEN2_GEN_MASK(4, 1)
/* definitions for field: Enable PPS_IN 50Ohm termination in reg: External sync control register */
#define PPSG_ESCR_PPS_IN_TERM WBGEN2_GEN_MASK(5, 1)
PACKED struct PPSG_WB {
/* [0x0]: REG Control Register */
uint32_t CR;
......
modules/wr_pps_gen/pps_gen_wb.vhd
View file @ 985caf49
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : pps_gen_wb.vhd
-- Author : auto-generated by wbgen2 from pps_gen_wb.wb
-- Created : Thu Aug 6 16:03:49 2015
-- Created : Thu Sep 13 15:39:55 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pps_gen_wb.wb
......@@ -66,7 +66,9 @@ entity pps_gen_wb is
-- Port for asynchronous (clock: refclk_i) MONOSTABLE field: 'Set seconds counter' in reg: 'External sync control register'
ppsg_escr_sec_set_o : out std_logic;
-- Port for asynchronous (clock: refclk_i) MONOSTABLE field: 'Set nanoseconds counter' in reg: 'External sync control register'
ppsg_escr_nsec_set_o : out std_logic
ppsg_escr_nsec_set_o : out std_logic;
-- Port for BIT field: 'Enable PPS_IN 50Ohm termination' in reg: 'External sync control register'
ppsg_escr_pps_in_term_o : out std_logic
);
end pps_gen_wb;
......@@ -146,25 +148,16 @@ signal ppsg_escr_nsec_set_int_delay : std_logic ;
signal ppsg_escr_nsec_set_sync0 : std_logic ;
signal ppsg_escr_nsec_set_sync1 : std_logic ;
signal ppsg_escr_nsec_set_sync2 : std_logic ;
signal ppsg_escr_pps_in_term_int : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(2 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
-- Some internal signals assignments
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
......@@ -209,6 +202,7 @@ begin
ppsg_escr_sec_set_int_delay <= '0';
ppsg_escr_nsec_set_int <= '0';
ppsg_escr_nsec_set_int_delay <= '0';
ppsg_escr_pps_in_term_int <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
......@@ -481,6 +475,7 @@ begin
ppsg_escr_sec_set_int_delay <= wrdata_reg(3);
ppsg_escr_nsec_set_int <= wrdata_reg(4);
ppsg_escr_nsec_set_int_delay <= wrdata_reg(4);
ppsg_escr_pps_in_term_int <= wrdata_reg(5);
end if;
if (wb_we_i = '0') then
rddata_reg(0) <= 'X';
......@@ -493,7 +488,7 @@ begin
rddata_reg(2) <= ppsg_escr_tm_valid_int;
rddata_reg(3) <= '0';
rddata_reg(4) <= '0';
rddata_reg(5) <= 'X';
rddata_reg(5) <= ppsg_escr_pps_in_term_int;
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
......@@ -800,6 +795,8 @@ begin
end process;
-- Enable PPS_IN 50Ohm termination
ppsg_escr_pps_in_term_o <= ppsg_escr_pps_in_term_int;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
......
modules/wr_pps_gen/pps_gen_wb.wb
View file @ 985caf49
......@@ -210,6 +210,18 @@ peripheral {
clock = "refclk_i";
};
field {
name = "Enable PPS_IN 50Ohm termination";
description = "write 1: enable 50ohm termination for 1-PPS input \
write 0: disable 50ohm termination for 1-PPS input \
read 1: 50ohm termination for 1-PPS input enabled \
read 0: 50ohm termination for 1-PPS input disabled";
prefix = "PPS_IN_TERM";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
};
modules/wr_pps_gen/wr_pps_gen.vhd
View file @ 985caf49
......@@ -58,7 +58,8 @@ entity wr_pps_gen is
-- External PPS input. Warning! This signal is treated as synchronous to
-- the clk_ref_i (or the external 10 MHz reference) to prevent sync chain
-- delay uncertainities. Setup/hold times must be respected!
pps_in_i : in std_logic;
pps_in_i : in std_logic;
ppsin_term_o : out std_logic;
-- Single-pulse PPS output for synchronizing endpoints to
pps_csync_o : out std_logic;
......@@ -112,7 +113,8 @@ architecture behavioral of wr_pps_gen is
ppsg_escr_pps_valid_o : out std_logic;
ppsg_escr_tm_valid_o : out std_logic;
ppsg_escr_sec_set_o : out std_logic;
ppsg_escr_nsec_set_o : out std_logic);
ppsg_escr_nsec_set_o : out std_logic;
ppsg_escr_pps_in_term_o: out std_logic);
end component;
......@@ -489,7 +491,8 @@ begin -- behavioral
ppsg_escr_pps_valid_o => ppsg_escr_pps_valid,
ppsg_escr_tm_valid_o => ppsg_escr_tm_valid,
ppsg_escr_sec_set_o => ppsg_escr_sec_set,
ppsg_escr_nsec_set_o => ppsg_escr_nsec_set);
ppsg_escr_nsec_set_o => ppsg_escr_nsec_set,
ppsg_escr_pps_in_term_o=> ppsin_term_o);
-- start the adjustment upon write of 1 to CNT_ADJ bit
cntr_adjust_p <= ppsg_cr_cnt_adj_load and ppsg_cr_cnt_adj_o;
......
modules/wr_pps_gen/xwr_pps_gen.vhd
View file @ 985caf49
......@@ -46,7 +46,8 @@ entity xwr_pps_gen is
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
pps_in_i : in std_logic;
pps_in_i : in std_logic;
ppsin_term_o : out std_logic;
-- Single-pulse PPS output for synchronizing endpoints to
pps_csync_o : out std_logic;
......@@ -87,6 +88,7 @@ architecture behavioral of xwr_pps_gen is
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
pps_in_i : in std_logic;
ppsin_term_o : out std_logic;
pps_csync_o : out std_logic;
pps_out_o : out std_logic;
pps_led_o : out std_logic;
......@@ -123,6 +125,7 @@ begin -- behavioral
wb_ack_o => slave_o.ack,
wb_stall_o => slave_o.stall,
pps_in_i => pps_in_i,
ppsin_term_o => ppsin_term_o,
pps_csync_o => pps_csync_o,
pps_out_o => pps_out_o,
pps_led_o => pps_led_o,
......
sim/pps_gen_regs.v
View file @ 985caf49
......@@ -26,3 +26,5 @@
`define PPSG_ESCR_SEC_SET 32'h00000008
`define PPSG_ESCR_NSEC_SET_OFFSET 4
`define PPSG_ESCR_NSEC_SET 32'h00000010
`define PPSG_ESCR_PPS_IN_TERM_OFFSET 5
`define PPSG_ESCR_PPS_IN_TERM 32'h00000020
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