platform/xilinx: set g_phy_refclk_sel default value to 4.
GTP reference clock is connected to CLK01 and/or CLK11 in our instance of GTP_DUAL. According to UG386, figure 2-3, page 41, REFSELDYPLLx must be set to '4' to select CLK10/CLK11. This is done in order to ensure backward compatibility with previous versions of the Xilinx platform support package.
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