Commit 99932d24 authored by Dimitris Lampridis's avatar Dimitris Lampridis

platform/xilinx: set g_phy_refclk_sel default value to 4.

GTP reference clock is connected to CLK01 and/or CLK11 in our instance of GTP_DUAL.

According to UG386, figure 2-3, page 41, REFSELDYPLLx must be set to '4' to select
CLK10/CLK11.

This is done in order to ensure backward compatibility with previous versions of
the Xilinx platform support package.
parent 6ea37961
......@@ -58,7 +58,7 @@ package wr_xilinx_pkg is
g_gtp_enable_ch0 : integer := 0;
g_gtp_enable_ch1 : integer := 1;
g_gtp_mux_enable : boolean := FALSE;
g_phy_refclk_sel : integer range 0 to 7 := 0;
g_phy_refclk_sel : integer range 0 to 7 := 4;
g_simulation : integer := 0
);
port (
......
......@@ -67,7 +67,8 @@ entity xwrc_platform_xilinx is
g_gtp_enable_ch0 : integer := 0;
g_gtp_enable_ch1 : integer := 1;
-- Select PHY reference clock
g_phy_refclk_sel : integer range 0 to 7 := 0;
-- default value of 4 selects CLK10 / CLK11 (see UG386, Fig 2-3, page 41)
g_phy_refclk_sel : integer range 0 to 7 := 4;
g_gtp_mux_enable : boolean := FALSE;
-- Set to TRUE will speed up some initialization processes
g_simulation : integer := 0);
......
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