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White Rabbit core collection
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9a009ab1
Commit
9a009ab1
authored
Oct 23, 2013
by
Grzegorz Daniluk
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Plain Diff
wrsw_nic: reduce destination port mask to needed bits
parent
9430c320
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4 changed files
with
29 additions
and
21 deletions
+29
-21
nic_descriptor_manager.vhd
modules/wrsw_nic/nic_descriptor_manager.vhd
+3
-4
nic_tx_fsm.vhd
modules/wrsw_nic/nic_tx_fsm.vhd
+4
-3
wrsw_nic.vhd
modules/wrsw_nic/wrsw_nic.vhd
+8
-6
xwrsw_nic.vhd
modules/wrsw_nic/xwrsw_nic.vhd
+14
-8
No files found.
modules/wrsw_nic/nic_descriptor_manager.vhd
View file @
9a009ab1
...
...
@@ -28,13 +28,12 @@ library work;
use
work
.
nic_constants_pkg
.
all
;
use
work
.
nic_descriptors_pkg
.
all
;
entity
nic_descriptor_manager
is
generic
(
g_desc_mode
:
string
:
=
"tx"
;
g_num_descriptors
:
integer
;
g_num_descriptors_log2
:
integer
);
g_num_descriptors_log2
:
integer
;
g_port_mask_bits
:
integer
:
=
32
);
--worth using only in TX mode
port
(
clk_sys_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
...
...
@@ -179,7 +178,7 @@ begin -- behavioral
when
"11"
=>
p_unmarshall_tx_descriptor
(
dtbl_data_i
,
3
,
tmp_desc_tx
);
-- TX
granted_desc_tx
.
dpm
<=
tmp_desc_tx
.
dpm
;
granted_desc_tx
.
dpm
(
g_port_mask_bits
-1
downto
0
)
<=
tmp_desc_tx
.
dpm
(
g_port_mask_bits
-1
downto
0
)
;
p_unmarshall_rx_descriptor
(
dtbl_data_i
,
3
,
tmp_desc_rx
);
-- RX
...
...
modules/wrsw_nic/nic_tx_fsm.vhd
View file @
9a009ab1
...
...
@@ -32,7 +32,8 @@ use work.nic_wbgen2_pkg.all;
entity
nic_tx_fsm
is
generic
(
g_port_mask_bits
:
integer
:
=
32
);
port
(
clk_sys_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
-------------------------------------------------------------------------------
...
...
@@ -45,7 +46,7 @@ entity nic_tx_fsm is
-- "Fake" RTU interface
-------------------------------------------------------------------------------
rtu_dst_port_mask_o
:
out
std_logic_vector
(
3
1
downto
0
);
rtu_dst_port_mask_o
:
out
std_logic_vector
(
g_port_mask_bits
-
1
downto
0
);
rtu_prio_o
:
out
std_logic_vector
(
2
downto
0
);
rtu_drop_o
:
out
std_logic
;
rtu_rsp_valid_o
:
out
std_logic
;
...
...
@@ -285,7 +286,7 @@ begin -- behavioral
regs_o
.
sr_tx_error_i
<=
'0'
;
rtu_prio_o
<=
(
others
=>
'0'
);
rtu_dst_port_mask_o
<=
cur_tx_desc
.
dpm
;
rtu_dst_port_mask_o
<=
cur_tx_desc
.
dpm
(
g_port_mask_bits
-1
downto
0
)
;
rtu_drop_o
<=
'0'
;
rtu_valid_int
<=
'1'
;
...
...
modules/wrsw_nic/wrsw_nic.vhd
View file @
9a009ab1
...
...
@@ -10,8 +10,8 @@ entity wrsw_nic is
generic
(
g_interface_mode
:
t_wishbone_interface_mode
:
=
CLASSIC
;
g_address_granularity
:
t_wishbone_address_granularity
:
=
WORD
);
g_address_granularity
:
t_wishbone_address_granularity
:
=
WORD
;
g_port_mask_bits
:
integer
:
=
32
);
--should be num_ports+1
port
(
clk_sys_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
...
...
@@ -46,7 +46,7 @@ entity wrsw_nic is
-- "Fake" RTU interface
-------------------------------------------------------------------------------
rtu_dst_port_mask_o
:
out
std_logic_vector
(
3
1
downto
0
);
rtu_dst_port_mask_o
:
out
std_logic_vector
(
g_port_mask_bits
-
1
downto
0
);
rtu_prio_o
:
out
std_logic_vector
(
2
downto
0
);
rtu_drop_o
:
out
std_logic
;
rtu_rsp_valid_o
:
out
std_logic
;
...
...
@@ -76,7 +76,8 @@ architecture rtl of wrsw_nic is
component
xwrsw_nic
generic
(
g_interface_mode
:
t_wishbone_interface_mode
;
g_address_granularity
:
t_wishbone_address_granularity
);
g_address_granularity
:
t_wishbone_address_granularity
;
g_port_mask_bits
:
integer
:
=
32
);
port
(
clk_sys_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
...
...
@@ -84,7 +85,7 @@ architecture rtl of wrsw_nic is
snk_o
:
out
t_wrf_sink_out
;
src_i
:
in
t_wrf_source_in
;
src_o
:
out
t_wrf_source_out
;
rtu_dst_port_mask_o
:
out
std_logic_vector
(
3
1
downto
0
);
rtu_dst_port_mask_o
:
out
std_logic_vector
(
g_port_mask_bits
-
1
downto
0
);
rtu_prio_o
:
out
std_logic_vector
(
2
downto
0
);
rtu_drop_o
:
out
std_logic
;
rtu_rsp_valid_o
:
out
std_logic
;
...
...
@@ -108,7 +109,8 @@ begin
U_Wrapped_NIC
:
xwrsw_nic
generic
map
(
g_interface_mode
=>
g_interface_mode
,
g_address_granularity
=>
g_address_granularity
)
g_address_granularity
=>
g_address_granularity
,
g_port_mask_bits
=>
g_port_mask_bits
)
port
map
(
clk_sys_i
=>
clk_sys_i
,
rst_n_i
=>
rst_n_i
,
...
...
modules/wrsw_nic/xwrsw_nic.vhd
View file @
9a009ab1
...
...
@@ -16,8 +16,8 @@ entity xwrsw_nic is
generic
(
g_interface_mode
:
t_wishbone_interface_mode
:
=
CLASSIC
;
g_address_granularity
:
t_wishbone_address_granularity
:
=
WORD
);
g_address_granularity
:
t_wishbone_address_granularity
:
=
WORD
;
g_port_mask_bits
:
integer
:
=
32
);
--should be num_ports+1
port
(
clk_sys_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
...
...
@@ -36,7 +36,7 @@ entity xwrsw_nic is
-- "Fake" RTU interface
-------------------------------------------------------------------------------
rtu_dst_port_mask_o
:
out
std_logic_vector
(
3
1
downto
0
);
rtu_dst_port_mask_o
:
out
std_logic_vector
(
g_port_mask_bits
-
1
downto
0
);
rtu_prio_o
:
out
std_logic_vector
(
2
downto
0
);
rtu_drop_o
:
out
std_logic
;
rtu_rsp_valid_o
:
out
std_logic
;
...
...
@@ -58,7 +58,8 @@ architecture rtl of xwrsw_nic is
generic
(
g_desc_mode
:
string
;
g_num_descriptors
:
integer
;
g_num_descriptors_log2
:
integer
);
g_num_descriptors_log2
:
integer
;
g_port_mask_bits
:
integer
:
=
32
);
port
(
clk_sys_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
...
...
@@ -161,12 +162,14 @@ architecture rtl of xwrsw_nic is
end
component
;
component
nic_tx_fsm
generic
(
g_port_mask_bits
:
integer
:
=
32
);
port
(
clk_sys_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
src_o
:
out
t_wrf_source_out
;
src_i
:
in
t_wrf_source_in
;
rtu_dst_port_mask_o
:
out
std_logic_vector
(
3
1
downto
0
);
rtu_dst_port_mask_o
:
out
std_logic_vector
(
g_port_mask_bits
-
1
downto
0
);
rtu_prio_o
:
out
std_logic_vector
(
2
downto
0
);
rtu_drop_o
:
out
std_logic
;
rtu_rsp_valid_o
:
out
std_logic
;
...
...
@@ -396,8 +399,8 @@ begin -- rtl
generic
map
(
g_desc_mode
=>
"rx"
,
g_num_descriptors
=>
c_nic_num_rx_descriptors
,
g_num_descriptors_log2
=>
c_nic_num_rx_descriptors_log2
)
g_num_descriptors_log2
=>
c_nic_num_rx_descriptors_log2
,
g_port_mask_bits
=>
g_port_mask_bits
)
port
map
(
clk_sys_i
=>
clk_sys_i
,
rst_n_i
=>
nic_reset_n
,
...
...
@@ -462,7 +465,8 @@ begin -- rtl
generic
map
(
g_desc_mode
=>
"tx"
,
g_num_descriptors
=>
c_nic_num_tx_descriptors
,
g_num_descriptors_log2
=>
c_nic_num_tx_descriptors_log2
)
g_num_descriptors_log2
=>
c_nic_num_tx_descriptors_log2
,
g_port_mask_bits
=>
g_port_mask_bits
)
port
map
(
clk_sys_i
=>
clk_sys_i
,
rst_n_i
=>
nic_reset_n
,
...
...
@@ -490,6 +494,8 @@ begin -- rtl
U_TX_FSM
:
nic_tx_fsm
generic
map
(
g_port_mask_bits
=>
g_port_mask_bits
)
port
map
(
clk_sys_i
=>
clk_sys_i
,
rst_n_i
=>
nic_reset_n
,
...
...
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