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White Rabbit core collection
Commits
9ab0dcb1
Commit
9ab0dcb1
authored
Dec 17, 2019
by
Grzegorz Daniluk
Browse files
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Browse Files
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Merge branch 'wr_starting_kit_update' into proposed_master
parents
ee358ebe
0244a1ae
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Showing
12 changed files
with
499 additions
and
12 deletions
+499
-12
wr_board_pkg.vhd
board/common/wr_board_pkg.vhd
+1
-0
xwrc_board_common.vhd
board/common/xwrc_board_common.vhd
+9
-1
wr_spec_pkg.vhd
board/spec/wr_spec_pkg.vhd
+10
-2
wrc_board_spec.vhd
board/spec/wrc_board_spec.vhd
+13
-6
xwrc_board_spec.vhd
board/spec/xwrc_board_spec.vhd
+7
-2
Manifest.py
modules/wr_nic/Manifest.py
+3
-1
wr_nic_wrapper.vhd
modules/wr_nic/wr_nic_wrapper.vhd
+228
-0
wr_nic_wrapper_pkg.vhd
modules/wr_nic/wr_nic_wrapper_pkg.vhd
+204
-0
wr_core.vhd
modules/wrc_core/wr_core.vhd
+2
-0
wrcore_pkg.vhd
modules/wrc_core/wrcore_pkg.vhd
+2
-0
xwr_core.vhd
modules/wrc_core/xwr_core.vhd
+2
-0
vic_regs.vh
sim/vic_regs.vh
+18
-0
No files found.
board/common/wr_board_pkg.vhd
View file @
9ab0dcb1
...
@@ -214,6 +214,7 @@ package wr_board_pkg is
...
@@ -214,6 +214,7 @@ package wr_board_pkg is
btn1_i
:
in
std_logic
:
=
'1'
;
btn1_i
:
in
std_logic
:
=
'1'
;
btn2_i
:
in
std_logic
:
=
'1'
;
btn2_i
:
in
std_logic
:
=
'1'
;
pps_csync_o
:
out
std_logic
;
pps_csync_o
:
out
std_logic
;
pps_valid_o
:
out
std_logic
;
pps_p_o
:
out
std_logic
;
pps_p_o
:
out
std_logic
;
pps_led_o
:
out
std_logic
;
pps_led_o
:
out
std_logic
;
link_ok_o
:
out
std_logic
);
link_ok_o
:
out
std_logic
);
...
...
board/common/xwrc_board_common.vhd
View file @
9ab0dcb1
...
@@ -259,6 +259,7 @@ entity xwrc_board_common is
...
@@ -259,6 +259,7 @@ entity xwrc_board_common is
btn2_i
:
in
std_logic
:
=
'1'
;
btn2_i
:
in
std_logic
:
=
'1'
;
-- 1PPS output
-- 1PPS output
pps_csync_o
:
out
std_logic
;
pps_csync_o
:
out
std_logic
;
pps_valid_o
:
out
std_logic
;
pps_p_o
:
out
std_logic
;
pps_p_o
:
out
std_logic
;
pps_led_o
:
out
std_logic
;
pps_led_o
:
out
std_logic
;
-- Link ok indication
-- Link ok indication
...
@@ -348,6 +349,10 @@ architecture struct of xwrc_board_common is
...
@@ -348,6 +349,10 @@ architecture struct of xwrc_board_common is
-- signal sfp1_sda_in : std_logic;
-- signal sfp1_sda_in : std_logic;
-- signal sfp1_det_in : std_logic;
-- signal sfp1_det_in : std_logic;
signal
pps_valid
:
std_logic
;
signal
pps_csync
:
std_logic
;
begin
-- architecture struct
begin
-- architecture struct
-- Check for unsupported fabric interface type
-- Check for unsupported fabric interface type
...
@@ -471,7 +476,8 @@ begin -- architecture struct
...
@@ -471,7 +476,8 @@ begin -- architecture struct
tm_time_valid_o
=>
tm_time_valid
,
tm_time_valid_o
=>
tm_time_valid
,
tm_tai_o
=>
tm_tai
,
tm_tai_o
=>
tm_tai
,
tm_cycles_o
=>
tm_cycles
,
tm_cycles_o
=>
tm_cycles
,
pps_csync_o
=>
pps_csync_o
,
pps_csync_o
=>
pps_csync
,
pps_valid_o
=>
pps_valid
,
pps_p_o
=>
pps_p_o
,
pps_p_o
=>
pps_p_o
,
pps_led_o
=>
pps_led_o
,
pps_led_o
=>
pps_led_o
,
rst_aux_n_o
=>
aux_rst_n
,
rst_aux_n_o
=>
aux_rst_n
,
...
@@ -479,6 +485,8 @@ begin -- architecture struct
...
@@ -479,6 +485,8 @@ begin -- architecture struct
aux_diag_o
=>
aux_diag_out
,
aux_diag_o
=>
aux_diag_out
,
link_ok_o
=>
link_ok
);
link_ok_o
=>
link_ok
);
pps_csync_o
<=
pps_csync
;
pps_valid_o
<=
pps_valid
;
link_ok_o
<=
link_ok
;
link_ok_o
<=
link_ok
;
tm_time_valid_o
<=
tm_time_valid
;
tm_time_valid_o
<=
tm_time_valid
;
tm_tai_o
<=
tm_tai
;
tm_tai_o
<=
tm_tai
;
...
...
board/spec/wr_spec_pkg.vhd
View file @
9ab0dcb1
...
@@ -61,7 +61,9 @@ package wr_spec_pkg is
...
@@ -61,7 +61,9 @@ package wr_spec_pkg is
g_diag_ver
:
integer
:
=
0
;
g_diag_ver
:
integer
:
=
0
;
g_diag_ro_size
:
integer
:
=
0
;
g_diag_ro_size
:
integer
:
=
0
;
g_diag_rw_size
:
integer
:
=
0
;
g_diag_rw_size
:
integer
:
=
0
;
g_aux_pll_cfg
:
t_auxpll_cfg_array
:
=
c_AUXPLL_CFG_ARRAY_DEFAULT
);
g_aux_pll_cfg
:
t_auxpll_cfg_array
:
=
c_AUXPLL_CFG_ARRAY_DEFAULT
;
g_aux_sdb
:
t_sdb_device
:
=
c_wrc_periph3_sdb
);
port
(
port
(
areset_n_i
:
in
std_logic
;
areset_n_i
:
in
std_logic
;
areset_edge_n_i
:
in
std_logic
:
=
'1'
;
areset_edge_n_i
:
in
std_logic
:
=
'1'
;
...
@@ -152,6 +154,8 @@ package wr_spec_pkg is
...
@@ -152,6 +154,8 @@ package wr_spec_pkg is
btn1_i
:
in
std_logic
:
=
'1'
;
btn1_i
:
in
std_logic
:
=
'1'
;
btn2_i
:
in
std_logic
:
=
'1'
;
btn2_i
:
in
std_logic
:
=
'1'
;
pps_p_o
:
out
std_logic
;
pps_p_o
:
out
std_logic
;
pps_csync_o
:
out
std_logic
;
pps_valid_o
:
out
std_logic
;
pps_led_o
:
out
std_logic
;
pps_led_o
:
out
std_logic
;
link_ok_o
:
out
std_logic
);
link_ok_o
:
out
std_logic
);
end
component
xwrc_board_spec
;
end
component
xwrc_board_spec
;
...
@@ -171,7 +175,9 @@ package wr_spec_pkg is
...
@@ -171,7 +175,9 @@ package wr_spec_pkg is
g_diag_id
:
integer
:
=
0
;
g_diag_id
:
integer
:
=
0
;
g_diag_ver
:
integer
:
=
0
;
g_diag_ver
:
integer
:
=
0
;
g_diag_ro_vector_width
:
integer
:
=
0
;
g_diag_ro_vector_width
:
integer
:
=
0
;
g_diag_rw_vector_width
:
integer
:
=
0
);
g_diag_rw_vector_width
:
integer
:
=
0
;
g_aux_sdb
:
t_sdb_device
:
=
c_wrc_periph3_sdb
);
port
(
port
(
areset_n_i
:
in
std_logic
;
areset_n_i
:
in
std_logic
;
areset_edge_n_i
:
in
std_logic
:
=
'1'
;
areset_edge_n_i
:
in
std_logic
:
=
'1'
;
...
@@ -311,6 +317,8 @@ package wr_spec_pkg is
...
@@ -311,6 +317,8 @@ package wr_spec_pkg is
btn1_i
:
in
std_logic
:
=
'1'
;
btn1_i
:
in
std_logic
:
=
'1'
;
btn2_i
:
in
std_logic
:
=
'1'
;
btn2_i
:
in
std_logic
:
=
'1'
;
pps_p_o
:
out
std_logic
;
pps_p_o
:
out
std_logic
;
pps_csync_o
:
out
std_logic
;
pps_valid_o
:
out
std_logic
;
pps_led_o
:
out
std_logic
;
pps_led_o
:
out
std_logic
;
link_ok_o
:
out
std_logic
);
link_ok_o
:
out
std_logic
);
end
component
wrc_board_spec
;
end
component
wrc_board_spec
;
...
...
board/spec/wrc_board_spec.vhd
View file @
9ab0dcb1
...
@@ -78,7 +78,8 @@ entity wrc_board_spec is
...
@@ -78,7 +78,8 @@ entity wrc_board_spec is
g_diag_ver
:
integer
:
=
0
;
g_diag_ver
:
integer
:
=
0
;
-- size the generic diag interface
-- size the generic diag interface
g_diag_ro_vector_width
:
integer
:
=
0
;
g_diag_ro_vector_width
:
integer
:
=
0
;
g_diag_rw_vector_width
:
integer
:
=
0
g_diag_rw_vector_width
:
integer
:
=
0
;
g_aux_sdb
:
t_sdb_device
:
=
c_wrc_periph3_sdb
);
);
port
(
port
(
---------------------------------------------------------------------------
---------------------------------------------------------------------------
...
@@ -302,6 +303,8 @@ entity wrc_board_spec is
...
@@ -302,6 +303,8 @@ entity wrc_board_spec is
btn2_i
:
in
std_logic
:
=
'1'
;
btn2_i
:
in
std_logic
:
=
'1'
;
-- 1PPS output
-- 1PPS output
pps_p_o
:
out
std_logic
;
pps_p_o
:
out
std_logic
;
pps_csync_o
:
out
std_logic
;
pps_valid_o
:
out
std_logic
;
pps_led_o
:
out
std_logic
;
pps_led_o
:
out
std_logic
;
-- Link ok indication
-- Link ok indication
link_ok_o
:
out
std_logic
link_ok_o
:
out
std_logic
...
@@ -419,6 +422,7 @@ begin -- architecture struct
...
@@ -419,6 +422,7 @@ begin -- architecture struct
tstamps_tsval_o
<=
timestamps_out
.
tsval
;
tstamps_tsval_o
<=
timestamps_out
.
tsval
;
tstamps_port_id_o
<=
timestamps_out
.
port_id
;
tstamps_port_id_o
<=
timestamps_out
.
port_id
;
tstamps_frame_id_o
<=
timestamps_out
.
frame_id
;
tstamps_frame_id_o
<=
timestamps_out
.
frame_id
;
tstamps_incorrect_o
<=
timestamps_out
.
incorrect
;
wrs_tx_cfg_in
.
mac_local
<=
wrs_tx_cfg_mac_l_i
;
wrs_tx_cfg_in
.
mac_local
<=
wrs_tx_cfg_mac_l_i
;
wrs_tx_cfg_in
.
mac_target
<=
wrs_tx_cfg_mac_t_i
;
wrs_tx_cfg_in
.
mac_target
<=
wrs_tx_cfg_mac_t_i
;
...
@@ -446,7 +450,8 @@ begin -- architecture struct
...
@@ -446,7 +450,8 @@ begin -- architecture struct
g_diag_id
=>
g_diag_id
,
g_diag_id
=>
g_diag_id
,
g_diag_ver
=>
g_diag_ver
,
g_diag_ver
=>
g_diag_ver
,
g_diag_ro_size
=>
c_diag_ro_size
,
g_diag_ro_size
=>
c_diag_ro_size
,
g_diag_rw_size
=>
c_diag_rw_size
)
g_diag_rw_size
=>
c_diag_rw_size
,
g_aux_sdb
=>
g_aux_sdb
)
port
map
(
port
map
(
areset_n_i
=>
areset_n_i
,
areset_n_i
=>
areset_n_i
,
areset_edge_n_i
=>
areset_edge_n_i
,
areset_edge_n_i
=>
areset_edge_n_i
,
...
@@ -534,6 +539,8 @@ begin -- architecture struct
...
@@ -534,6 +539,8 @@ begin -- architecture struct
btn1_i
=>
btn1_i
,
btn1_i
=>
btn1_i
,
btn2_i
=>
btn2_i
,
btn2_i
=>
btn2_i
,
pps_p_o
=>
pps_p_o
,
pps_p_o
=>
pps_p_o
,
pps_csync_o
=>
pps_csync_o
,
pps_valid_o
=>
pps_valid_o
,
pps_led_o
=>
pps_led_o
,
pps_led_o
=>
pps_led_o
,
link_ok_o
=>
link_ok_o
);
link_ok_o
=>
link_ok_o
);
...
...
board/spec/xwrc_board_spec.vhd
View file @
9ab0dcb1
...
@@ -80,7 +80,8 @@ entity xwrc_board_spec is
...
@@ -80,7 +80,8 @@ entity xwrc_board_spec is
g_diag_ro_size
:
integer
:
=
0
;
g_diag_ro_size
:
integer
:
=
0
;
g_diag_rw_size
:
integer
:
=
0
;
g_diag_rw_size
:
integer
:
=
0
;
-- User-defined PLL_BASE outputs config
-- User-defined PLL_BASE outputs config
g_aux_pll_cfg
:
t_auxpll_cfg_array
:
=
c_AUXPLL_CFG_ARRAY_DEFAULT
g_aux_pll_cfg
:
t_auxpll_cfg_array
:
=
c_AUXPLL_CFG_ARRAY_DEFAULT
;
g_aux_sdb
:
t_sdb_device
:
=
c_wrc_periph3_sdb
);
);
port
(
port
(
---------------------------------------------------------------------------
---------------------------------------------------------------------------
...
@@ -256,6 +257,8 @@ entity xwrc_board_spec is
...
@@ -256,6 +257,8 @@ entity xwrc_board_spec is
btn2_i
:
in
std_logic
:
=
'1'
;
btn2_i
:
in
std_logic
:
=
'1'
;
-- 1PPS output
-- 1PPS output
pps_p_o
:
out
std_logic
;
pps_p_o
:
out
std_logic
;
pps_csync_o
:
out
std_logic
;
pps_valid_o
:
out
std_logic
;
pps_led_o
:
out
std_logic
;
pps_led_o
:
out
std_logic
;
-- Link ok indication
-- Link ok indication
link_ok_o
:
out
std_logic
link_ok_o
:
out
std_logic
...
@@ -444,7 +447,7 @@ begin -- architecture struct
...
@@ -444,7 +447,7 @@ begin -- architecture struct
g_dpram_size
=>
131072
/
4
,
g_dpram_size
=>
131072
/
4
,
g_interface_mode
=>
PIPELINED
,
g_interface_mode
=>
PIPELINED
,
g_address_granularity
=>
BYTE
,
g_address_granularity
=>
BYTE
,
g_aux_sdb
=>
c_wrc_periph3
_sdb
,
g_aux_sdb
=>
g_aux
_sdb
,
g_softpll_enable_debugger
=>
FALSE
,
g_softpll_enable_debugger
=>
FALSE
,
g_vuart_fifo_size
=>
1024
,
g_vuart_fifo_size
=>
1024
,
g_pcs_16bit
=>
FALSE
,
g_pcs_16bit
=>
FALSE
,
...
@@ -537,6 +540,8 @@ begin -- architecture struct
...
@@ -537,6 +540,8 @@ begin -- architecture struct
btn1_i
=>
btn1_i
,
btn1_i
=>
btn1_i
,
btn2_i
=>
btn2_i
,
btn2_i
=>
btn2_i
,
pps_p_o
=>
pps_p_o
,
pps_p_o
=>
pps_p_o
,
pps_csync_o
=>
pps_csync_o
,
pps_valid_o
=>
pps_valid_o
,
pps_led_o
=>
pps_led_o
,
pps_led_o
=>
pps_led_o
,
link_ok_o
=>
link_ok_o
);
link_ok_o
=>
link_ok_o
);
...
...
modules/wr_nic/Manifest.py
View file @
9ab0dcb1
...
@@ -9,5 +9,7 @@ files = [ "nic_constants_pkg.vhd" ,
...
@@ -9,5 +9,7 @@ files = [ "nic_constants_pkg.vhd" ,
"nic_bw_throttling.vhd"
,
"nic_bw_throttling.vhd"
,
"nic_wbgen2_pkg.vhd"
,
"nic_wbgen2_pkg.vhd"
,
"xwr_nic.vhd"
,
"xwr_nic.vhd"
,
"wr_nic.vhd"
];
"wr_nic.vhd"
,
"wr_nic_wrapper.vhd"
,
"wr_nic_wrapper_pkg.vhd"
];
modules/wr_nic/wr_nic_wrapper.vhd
0 → 100644
View file @
9ab0dcb1
This diff is collapsed.
Click to expand it.
modules/wr_nic/wr_nic_wrapper_pkg.vhd
0 → 100644
View file @
9ab0dcb1
-------------------------------------------------------------------------------
-- Title : WR-NIC Wrapper package
-- Project : WR PTP Core
-- URL : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
-------------------------------------------------------------------------------
-- File : wr_nic_wrapper_pkg.vhd
-- Company : Seven Solutions
-- Standard : VHDL'93
-------------------------------------------------------------------------------
--
-- Copyright (c) 2019 CERN (www.cern.ch)
--
-- GNU LESSER GENERAL PUBLIC LICENSE
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
library
work
;
use
work
.
gencores_pkg
.
all
;
use
work
.
wrcore_pkg
.
all
;
use
work
.
wishbone_pkg
.
all
;
use
work
.
wr_fabric_pkg
.
all
;
use
work
.
endpoint_pkg
.
all
;
package
wr_nic_wrapper_pkg
is
-----------------------------------------------------------------------------
-- Components
-----------------------------------------------------------------------------
-- Network Interface Core (NIC) component
component
xwr_nic
generic
(
g_interface_mode
:
t_wishbone_interface_mode
:
=
CLASSIC
;
g_address_granularity
:
t_wishbone_address_granularity
:
=
WORD
;
g_src_cyc_on_stall
:
boolean
:
=
false
;
g_port_mask_bits
:
integer
:
=
32
;
--should be num_ports+1
g_rmon_events_pp
:
integer
:
=
1
);
port
(
clk_sys_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
pps_p_i
:
in
std_logic
;
pps_valid_i
:
in
std_logic
;
snk_i
:
in
t_wrf_sink_in
;
snk_o
:
out
t_wrf_sink_out
;
src_i
:
in
t_wrf_source_in
;
src_o
:
out
t_wrf_source_out
;
rtu_dst_port_mask_o
:
out
std_logic_vector
(
g_port_mask_bits
-1
downto
0
);
rtu_prio_o
:
out
std_logic_vector
(
2
downto
0
);
rtu_drop_o
:
out
std_logic
;
rtu_rsp_valid_o
:
out
std_logic
;
rtu_rsp_ack_i
:
in
std_logic
;
wb_i
:
in
t_wishbone_slave_in
;
wb_o
:
out
t_wishbone_slave_out
;
int_o
:
out
std_logic
;
rmon_events_o
:
out
std_logic_vector
(
g_port_mask_bits
*
g_rmon_events_pp
-1
downto
0
));
end
component
;
-- Transimission TimeStamp Unit (TxTSU) component
component
xwr_tx_tsu
generic
(
g_num_ports
:
integer
:
=
10
;
g_interface_mode
:
t_wishbone_interface_mode
:
=
CLASSIC
;
g_address_granularity
:
t_wishbone_address_granularity
:
=
WORD
);
port
(
clk_sys_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
timestamps_i
:
in
t_txtsu_timestamp_array
(
g_num_ports
-1
downto
0
);
timestamps_ack_o
:
out
std_logic_vector
(
g_num_ports
-1
downto
0
);
wb_i
:
in
t_wishbone_slave_in
;
wb_o
:
out
t_wishbone_slave_out
;
int_o
:
out
std_logic
);
end
component
;
component
wr_nic_wrapper
generic
(
-- Number of peripheral interrupt lines
g_num_irqs
:
integer
:
=
3
;
-- Number of ports for the TxTSU module
g_num_ports
:
integer
:
=
1
);
port
(
---------------------------------------------------------------------------
-- Global ports (Clocks & Resets)
---------------------------------------------------------------------------
-- System clock
clk_sys_i
:
in
std_logic
;
-- Global reset (active low)
resetn_i
:
in
std_logic
;
---------------------------------------------------------------------------
-- External WB slave interface
---------------------------------------------------------------------------
ext_slave_i
:
in
t_wishbone_slave_in
;
ext_slave_o
:
out
t_wishbone_slave_out
;
---------------------------------------------------------------------------
-- NIC fabric data buses
---------------------------------------------------------------------------
nic_snk_i
:
in
t_wrf_sink_in
;
nic_snk_o
:
out
t_wrf_sink_out
;
nic_src_i
:
in
t_wrf_source_in
;
nic_src_o
:
out
t_wrf_source_out
;
-- PPS-related signal for NIC core
pps_p_i
:
in
std_logic
:
=
'0'
;
pps_valid_i
:
in
std_logic
:
=
'0'
;
---------------------------------------------------------------------------
-- VIC ports (peripheral interrupts lines and global interrupt output)
---------------------------------------------------------------------------
vic_irqs_i
:
in
std_logic_vector
(
g_num_irqs
-1
downto
0
);
vic_int_o
:
out
std_logic
;
---------------------------------------------------------------------------
-- TxTSU ports (Timestamp trigger and acknowlegdement signal)
---------------------------------------------------------------------------
txtsu_timestamps_i
:
in
t_txtsu_timestamp_array
(
g_num_ports
-1
downto
0
);
txtsu_timestamps_ack_o
:
out
std_logic_vector
(
g_num_ports
-1
downto
0
)
);
end
component
;
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
-- SDB constants for NIC and TxTSU
constant
c_xwr_nic_sdb
:
t_sdb_device
:
=
(
abi_class
=>
x"0000"
,
-- undocumented device
abi_ver_major
=>
x"01"
,
abi_ver_minor
=>
x"01"
,
wbd_endian
=>
c_sdb_endian_big
,
wbd_width
=>
x"7"
,
-- 8/16/32-bit port granularity
sdb_component
=>
(
addr_first
=>
x"0000000000000000"
,
addr_last
=>
x"000000000000ffff"
,
-- I think this is overestimated (orig. 1ffff, wrsw_hdl. ffff)
product
=>
(
vendor_id
=>
x"000000000000CE42"
,
-- CERN
device_id
=>
x"00000012"
,
version
=>
x"00000001"
,
date
=>
x"20000101"
,
-- UNKNOWN
name
=>
"WR-NIC "
)));
constant
c_xwr_txtsu_sdb
:
t_sdb_device
:
=
(
abi_class
=>
x"0000"
,
-- undocumented device
abi_ver_major
=>
x"01"
,
abi_ver_minor
=>
x"01"
,
wbd_endian
=>
c_sdb_endian_big
,
wbd_width
=>
x"7"
,
-- 8/16/32-bit port granularity
sdb_component
=>
(
addr_first
=>
x"0000000000000000"
,
addr_last
=>
x"00000000000000ff"
,
product
=>
(
vendor_id
=>
x"000000000000CE42"
,
-- CERN
device_id
=>
x"00000014"
,
version
=>
x"00000001"
,
date
=>
x"20120316"
,
name
=>
"WR-TXTSU "
)));
-- WB Crossbar constants
constant
c_NIC_WRAPPER_XBAR_REGISTERED
:
boolean
:
=
true
;
constant
c_NIC_WRAPPER_XBAR_WRAPAROUND
:
boolean
:
=
true
;
constant
c_NIC_WRAPPER_XBAR_NUM_MASTERS
:
integer
:
=
1
;
constant
c_NIC_WRAPPER_XBAR_MASTER_EXT
:
integer
:
=
0
;
constant
c_NIC_WRAPPER_XBAR_NUM_SLAVES
:
integer
:
=
3
;
constant
c_NIC_WRAPPER_XBAR_SLAVE_NIC
:
integer
:
=
0
;
constant
c_NIC_WRAPPER_XBAR_SLAVE_VIC
:
integer
:
=
1
;
constant
c_NIC_WRAPPER_XBAR_SLAVE_TXTSU
:
integer
:
=
2
;
-- Crossbar memory layout
constant
c_nic_wrapper_xbar_layout
:
t_sdb_record_array
(
c_NIC_WRAPPER_XBAR_NUM_SLAVES
-1
downto
0
)
:
=
(
c_NIC_WRAPPER_XBAR_SLAVE_NIC
=>
f_sdb_embed_device
(
c_xwr_nic_sdb
,
x"00000000"
),
c_NIC_WRAPPER_XBAR_SLAVE_VIC
=>
f_sdb_embed_device
(
c_xwb_vic_sdb
,
x"00010000"
),
c_NIC_WRAPPER_XBAR_SLAVE_TXTSU
=>
f_sdb_embed_device
(
c_xwr_txtsu_sdb
,
x"00010100"
)
);
-- Crossbar SDB entry address
constant
c_nic_wrapper_xbar_sdb_address
:
t_wishbone_address
:
=
x"00011000"
;
constant
c_nic_wrapper_xbar_bridge_sdb
:
t_sdb_bridge
:
=
f_xwb_bridge_layout_sdb
(
true
,
c_nic_wrapper_xbar_layout
,
c_nic_wrapper_xbar_sdb_address
);
end
wr_nic_wrapper_pkg
;
package
body
wr_nic_wrapper_pkg
is
end
package
body
wr_nic_wrapper_pkg
;
modules/wrc_core/wr_core.vhd
View file @
9ab0dcb1
...
@@ -293,6 +293,7 @@ entity wr_core is
...
@@ -293,6 +293,7 @@ entity wr_core is
tm_cycles_o
:
out
std_logic_vector
(
27
downto
0
);
tm_cycles_o
:
out
std_logic_vector
(
27
downto
0
);
-- 1PPS output
-- 1PPS output
pps_csync_o
:
out
std_logic
;
pps_csync_o
:
out
std_logic
;
pps_valid_o
:
out
std_logic
;
pps_p_o
:
out
std_logic
;
pps_p_o
:
out
std_logic
;
pps_led_o
:
out
std_logic
;
pps_led_o
:
out
std_logic
;
...
@@ -637,6 +638,7 @@ begin
...
@@ -637,6 +638,7 @@ begin
);
);
ppsg_link_ok
<=
not
phy_rst
;
ppsg_link_ok
<=
not
phy_rst
;
pps_csync_o
<=
s_pps_csync
;
pps_csync_o
<=
s_pps_csync
;
pps_valid_o
<=
pps_valid
;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Software PLL
-- Software PLL
...
...
modules/wrc_core/wrcore_pkg.vhd
View file @
9ab0dcb1
...
@@ -486,6 +486,7 @@ package wrcore_pkg is
...
@@ -486,6 +486,7 @@ package wrcore_pkg is
tm_tai_o
:
out
std_logic_vector
(
39
downto
0
);
tm_tai_o
:
out
std_logic_vector
(
39
downto
0
);
tm_cycles_o
:
out
std_logic_vector
(
27
downto
0
);
tm_cycles_o
:
out
std_logic_vector
(
27
downto
0
);
pps_csync_o
:
out
std_logic
;
pps_csync_o
:
out
std_logic
;
pps_valid_o
:
out
std_logic
;
pps_p_o
:
out
std_logic
;
pps_p_o
:
out
std_logic
;
pps_led_o
:
out
std_logic
;
pps_led_o
:
out
std_logic
;
...
@@ -724,6 +725,7 @@ package wrcore_pkg is
...
@@ -724,6 +725,7 @@ package wrcore_pkg is
tm_cycles_o
:
out
std_logic_vector
(
27
downto
0
);
tm_cycles_o
:
out
std_logic_vector
(
27
downto
0
);
-- 1PPS output
-- 1PPS output
pps_csync_o
:
out
std_logic
;
pps_csync_o
:
out
std_logic
;
pps_valid_o
:
out
std_logic
;
pps_p_o
:
out
std_logic
;
pps_p_o
:
out
std_logic
;
pps_led_o
:
out
std_logic
;
pps_led_o
:
out
std_logic
;
...
...
modules/wrc_core/xwr_core.vhd
View file @
9ab0dcb1
...
@@ -258,6 +258,7 @@ entity xwr_core is
...
@@ -258,6 +258,7 @@ entity xwr_core is
tm_cycles_o
:
out
std_logic_vector
(
27
downto
0
);
tm_cycles_o
:
out
std_logic_vector
(
27
downto
0
);
-- 1PPS output
-- 1PPS output
pps_csync_o
:
out
std_logic
;
pps_csync_o
:
out
std_logic
;
pps_valid_o
:
out
std_logic
;
pps_p_o
:
out
std_logic
;
pps_p_o
:
out
std_logic
;
pps_led_o
:
out
std_logic
;
pps_led_o
:
out
std_logic
;
...
@@ -431,6 +432,7 @@ begin
...
@@ -431,6 +432,7 @@ begin
tm_tai_o
=>
tm_tai_o
,
tm_tai_o
=>
tm_tai_o
,
tm_cycles_o
=>
tm_cycles_o
,
tm_cycles_o
=>
tm_cycles_o
,
pps_csync_o
=>
pps_csync_o
,
pps_csync_o
=>
pps_csync_o
,
pps_valid_o
=>
pps_valid_o
,
pps_p_o
=>
pps_p_o
,
pps_p_o
=>
pps_p_o
,
pps_led_o
=>
pps_led_o
,
pps_led_o
=>
pps_led_o
,
...
...
sim/vic_regs.vh
0 → 100644
View file @
9ab0dcb1
`define ADDR_VIC_CTL 8'h0
`define VIC_CTL_ENABLE_OFFSET 0
`define VIC_CTL_ENABLE 32'h00000001
`define VIC_CTL_POL_OFFSET 1
`define VIC_CTL_POL 32'h00000002
`define VIC_CTL_EMU_EDGE_OFFSET 2
`define VIC_CTL_EMU_EDGE 32'h00000004
`define VIC_CTL_EMU_LEN_OFFSET 3
`define VIC_CTL_EMU_LEN 32'h0007fff8
`define ADDR_VIC_RISR 8'h4
`define ADDR_VIC_IER 8'h8
`define ADDR_VIC_IDR 8'hc
`define ADDR_VIC_IMR 8'h10
`define ADDR_VIC_VAR 8'h14
`define ADDR_VIC_SWIR 8'h18
`define ADDR_VIC_EOIR 8'h1c
`define BASE_VIC_IVT_RAM 8'h80
`define SIZE_VIC_IVT_RAM 32'h20
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