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White Rabbit core collection
Commit 9ad5c482 authored by Maciej Lipinski's avatar Maciej Lipinski Committed by Grzegorz Daniluk
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[wr_streamers] add VLAN support to streamers

parent 2abec03c
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Showing with 193 additions and 32 deletions
modules/wr_streamers/streamers_pkg.vhd
View file @ 9ad5c482
......@@ -150,6 +150,12 @@ package streamers_pkg is
-- Ethertype of our frames. Default value is accepted by standard
-- configuration of the WR PTP Core
ethertype : std_logic_vector(15 downto 0);
-- enable tagging with VLAN tags
qtag_ena : std_logic;
---VLAN used to tag
qtag_vid : std_logic_vector(11 downto 0);
-- priority used to tag
qtag_prio : std_logic_vector(2 downto 0);
end record;
constant c_rx_streamer_cfg_default: t_rx_streamer_cfg :=(
......@@ -163,7 +169,10 @@ package streamers_pkg is
constant c_tx_streamer_cfg_default: t_tx_streamer_cfg :=(
mac_local => x"000000000000",
mac_target => x"ffffffffffff",
ethertype => x"dbff");
ethertype => x"dbff",
qtag_ena => '0',
qtag_vid => x"000",
qtag_prio => "000");
component xtx_streamer
generic (
......
modules/wr_streamers/wr_streamers_wb.vhd
View file @ 9ad5c482
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wr_streamers_wb.vhd
-- Author : auto-generated by wbgen2 from wr_streamers_wb.wb
-- Created : Fri May 5 15:07:47 2017
-- Created : Mon May 8 18:32:46 2017
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_streamers_wb.wb
......@@ -47,6 +47,9 @@ signal wr_streamers_tx_cfg1_mac_local_lsb_int : std_logic_vector(31 downto 0);
signal wr_streamers_tx_cfg2_mac_local_msb_int : std_logic_vector(15 downto 0);
signal wr_streamers_tx_cfg3_mac_target_lsb_int : std_logic_vector(31 downto 0);
signal wr_streamers_tx_cfg4_mac_target_msb_int : std_logic_vector(15 downto 0);
signal wr_streamers_tx_cfg5_qtag_ena_int : std_logic ;
signal wr_streamers_tx_cfg5_qtag_vid_int : std_logic_vector(11 downto 0);
signal wr_streamers_tx_cfg5_qtag_prio_int : std_logic_vector(2 downto 0);
signal wr_streamers_rx_cfg0_ethertype_int : std_logic_vector(15 downto 0);
signal wr_streamers_rx_cfg0_accept_broadcast_int : std_logic ;
signal wr_streamers_rx_cfg0_filter_remote_int : std_logic ;
......@@ -58,6 +61,7 @@ signal wr_streamers_rx_cfg5_fixed_latency_int : std_logic_vector(27 downto 0);
signal wr_streamers_cfg_or_tx_ethtype_int : std_logic ;
signal wr_streamers_cfg_or_tx_mac_loc_int : std_logic ;
signal wr_streamers_cfg_or_tx_mac_tar_int : std_logic ;
signal wr_streamers_cfg_or_tx_qtag_int : std_logic ;
signal wr_streamers_cfg_or_rx_ethertype_int : std_logic ;
signal wr_streamers_cfg_or_rx_mac_loc_int : std_logic ;
signal wr_streamers_cfg_or_rx_mac_rem_int : std_logic ;
......@@ -101,6 +105,9 @@ begin
wr_streamers_tx_cfg2_mac_local_msb_int <= "0000000000000000";
wr_streamers_tx_cfg3_mac_target_lsb_int <= "00000000000000000000000000000000";
wr_streamers_tx_cfg4_mac_target_msb_int <= "0000000000000000";
wr_streamers_tx_cfg5_qtag_ena_int <= '0';
wr_streamers_tx_cfg5_qtag_vid_int <= "000000000000";
wr_streamers_tx_cfg5_qtag_prio_int <= "000";
wr_streamers_rx_cfg0_ethertype_int <= "0000000000000000";
wr_streamers_rx_cfg0_accept_broadcast_int <= '0';
wr_streamers_rx_cfg0_filter_remote_int <= '0';
......@@ -112,6 +119,7 @@ begin
wr_streamers_cfg_or_tx_ethtype_int <= '0';
wr_streamers_cfg_or_tx_mac_loc_int <= '0';
wr_streamers_cfg_or_tx_mac_tar_int <= '0';
wr_streamers_cfg_or_tx_qtag_int <= '0';
wr_streamers_cfg_or_rx_ethertype_int <= '0';
wr_streamers_cfg_or_rx_mac_loc_int <= '0';
wr_streamers_cfg_or_rx_mac_rem_int <= '0';
......@@ -299,6 +307,33 @@ begin
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000" =>
if (wb_we_i = '1') then
wr_streamers_tx_cfg5_qtag_ena_int <= wrdata_reg(0);
wr_streamers_tx_cfg5_qtag_vid_int <= wrdata_reg(19 downto 8);
wr_streamers_tx_cfg5_qtag_prio_int <= wrdata_reg(26 downto 24);
end if;
rddata_reg(0) <= wr_streamers_tx_cfg5_qtag_ena_int;
rddata_reg(19 downto 8) <= wr_streamers_tx_cfg5_qtag_vid_int;
rddata_reg(26 downto 24) <= wr_streamers_tx_cfg5_qtag_prio_int;
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001" =>
if (wb_we_i = '1') then
wr_streamers_rx_cfg0_ethertype_int <= wrdata_reg(15 downto 0);
wr_streamers_rx_cfg0_accept_broadcast_int <= wrdata_reg(16);
......@@ -323,14 +358,14 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001" =>
when "10010" =>
if (wb_we_i = '1') then
wr_streamers_rx_cfg1_mac_local_lsb_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= wr_streamers_rx_cfg1_mac_local_lsb_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010" =>
when "10011" =>
if (wb_we_i = '1') then
wr_streamers_rx_cfg2_mac_local_msb_int <= wrdata_reg(15 downto 0);
end if;
......@@ -353,14 +388,14 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10011" =>
when "10100" =>
if (wb_we_i = '1') then
wr_streamers_rx_cfg3_mac_remote_lsb_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= wr_streamers_rx_cfg3_mac_remote_lsb_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10100" =>
when "10101" =>
if (wb_we_i = '1') then
wr_streamers_rx_cfg4_mac_remote_msb_int <= wrdata_reg(15 downto 0);
end if;
......@@ -383,7 +418,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10101" =>
when "10110" =>
if (wb_we_i = '1') then
wr_streamers_rx_cfg5_fixed_latency_int <= wrdata_reg(27 downto 0);
end if;
......@@ -394,11 +429,12 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10110" =>
when "10111" =>
if (wb_we_i = '1') then
wr_streamers_cfg_or_tx_ethtype_int <= wrdata_reg(0);
wr_streamers_cfg_or_tx_mac_loc_int <= wrdata_reg(1);
wr_streamers_cfg_or_tx_mac_tar_int <= wrdata_reg(2);
wr_streamers_cfg_or_tx_qtag_int <= wrdata_reg(3);
wr_streamers_cfg_or_rx_ethertype_int <= wrdata_reg(16);
wr_streamers_cfg_or_rx_mac_loc_int <= wrdata_reg(17);
wr_streamers_cfg_or_rx_mac_rem_int <= wrdata_reg(18);
......@@ -409,13 +445,13 @@ begin
rddata_reg(0) <= wr_streamers_cfg_or_tx_ethtype_int;
rddata_reg(1) <= wr_streamers_cfg_or_tx_mac_loc_int;
rddata_reg(2) <= wr_streamers_cfg_or_tx_mac_tar_int;
rddata_reg(3) <= wr_streamers_cfg_or_tx_qtag_int;
rddata_reg(16) <= wr_streamers_cfg_or_rx_ethertype_int;
rddata_reg(17) <= wr_streamers_cfg_or_rx_mac_loc_int;
rddata_reg(18) <= wr_streamers_cfg_or_rx_mac_rem_int;
rddata_reg(19) <= wr_streamers_cfg_or_rx_acc_broadcast_int;
rddata_reg(20) <= wr_streamers_cfg_or_rx_ftr_remote_int;
rddata_reg(21) <= wr_streamers_cfg_or_rx_fix_lat_int;
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
......@@ -440,7 +476,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10111" =>
when "11000" =>
if (wb_we_i = '1') then
wr_streamers_dbg_ctrl_mux_int <= wrdata_reg(0);
wr_streamers_dbg_ctrl_start_byte_int <= wrdata_reg(15 downto 8);
......@@ -472,13 +508,13 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11000" =>
when "11001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.dbg_data_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11001" =>
when "11010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.dummy_dummy_i;
......@@ -547,6 +583,12 @@ begin
regs_o.tx_cfg3_mac_target_lsb_o <= wr_streamers_tx_cfg3_mac_target_lsb_int;
-- MAC Target MSB
regs_o.tx_cfg4_mac_target_msb_o <= wr_streamers_tx_cfg4_mac_target_msb_int;
-- Enable tagging with Qtags
regs_o.tx_cfg5_qtag_ena_o <= wr_streamers_tx_cfg5_qtag_ena_int;
-- VLAN ID
regs_o.tx_cfg5_qtag_vid_o <= wr_streamers_tx_cfg5_qtag_vid_int;
-- Priority
regs_o.tx_cfg5_qtag_prio_o <= wr_streamers_tx_cfg5_qtag_prio_int;
-- Ethertype
regs_o.rx_cfg0_ethertype_o <= wr_streamers_rx_cfg0_ethertype_int;
-- Accept Broadcast
......@@ -569,6 +611,8 @@ begin
regs_o.cfg_or_tx_mac_loc_o <= wr_streamers_cfg_or_tx_mac_loc_int;
-- Tx MAC Target
regs_o.cfg_or_tx_mac_tar_o <= wr_streamers_cfg_or_tx_mac_tar_int;
-- QTAG
regs_o.cfg_or_tx_qtag_o <= wr_streamers_cfg_or_tx_qtag_int;
-- Rx Ethertype
regs_o.cfg_or_rx_ethertype_o <= wr_streamers_cfg_or_rx_ethertype_int;
-- Rx MAC Local
......
modules/wr_streamers/wr_streamers_wb.wb
View file @ 9ad5c482
......@@ -268,6 +268,35 @@ peripheral {
access_dev = READ_ONLY;
};
};
reg {
name = "Tx Config Reg 4";
prefix = "TX_CFG5";
field {
name = "Enable tagging with Qtags";
prefix = "qtag_ena";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "VLAN ID";
prefix = "qtag_vid";
type = SLV;
size = 12;
align= 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Priority";
prefix = "qtag_prio";
type = SLV;
size = 3;
align= 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Rx Config Reg 0";
prefix = "RX_CFG0";
......@@ -392,6 +421,16 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "QTAG";
description = "Overrides default/application QTAG values with configuration in the proper register:\
0: Default/set by application; \
1: Value from WB register";
prefix = "or_tx_qtag";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Rx Ethertype";
......
modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd
View file @ 9ad5c482
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wr_streamers_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from wr_streamers_wb.wb
-- Created : Fri May 5 15:07:47 2017
-- Created : Mon May 8 18:32:46 2017
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_streamers_wb.wb
......@@ -64,6 +64,9 @@ package wr_streamers_wbgen2_pkg is
tx_cfg2_mac_local_msb_o : std_logic_vector(15 downto 0);
tx_cfg3_mac_target_lsb_o : std_logic_vector(31 downto 0);
tx_cfg4_mac_target_msb_o : std_logic_vector(15 downto 0);
tx_cfg5_qtag_ena_o : std_logic;
tx_cfg5_qtag_vid_o : std_logic_vector(11 downto 0);
tx_cfg5_qtag_prio_o : std_logic_vector(2 downto 0);
rx_cfg0_ethertype_o : std_logic_vector(15 downto 0);
rx_cfg0_accept_broadcast_o : std_logic;
rx_cfg0_filter_remote_o : std_logic;
......@@ -75,6 +78,7 @@ package wr_streamers_wbgen2_pkg is
cfg_or_tx_ethtype_o : std_logic;
cfg_or_tx_mac_loc_o : std_logic;
cfg_or_tx_mac_tar_o : std_logic;
cfg_or_tx_qtag_o : std_logic;
cfg_or_rx_ethertype_o : std_logic;
cfg_or_rx_mac_loc_o : std_logic;
cfg_or_rx_mac_rem_o : std_logic;
......@@ -94,6 +98,9 @@ package wr_streamers_wbgen2_pkg is
tx_cfg2_mac_local_msb_o => (others => '0'),
tx_cfg3_mac_target_lsb_o => (others => '0'),
tx_cfg4_mac_target_msb_o => (others => '0'),
tx_cfg5_qtag_ena_o => '0',
tx_cfg5_qtag_vid_o => (others => '0'),
tx_cfg5_qtag_prio_o => (others => '0'),
rx_cfg0_ethertype_o => (others => '0'),
rx_cfg0_accept_broadcast_o => '0',
rx_cfg0_filter_remote_o => '0',
......@@ -105,6 +112,7 @@ package wr_streamers_wbgen2_pkg is
cfg_or_tx_ethtype_o => '0',
cfg_or_tx_mac_loc_o => '0',
cfg_or_tx_mac_tar_o => '0',
cfg_or_tx_qtag_o => '0',
cfg_or_rx_ethertype_o => '0',
cfg_or_rx_mac_loc_o => '0',
cfg_or_rx_mac_rem_o => '0',
......
modules/wr_streamers/xrx_streamer.vhd
View file @ 9ad5c482
......@@ -179,6 +179,7 @@ architecture rtl of xrx_streamer is
signal rx_latency_valid : std_logic;
signal delay_state : t_rx_delay_state;
signal rx_dreq : std_logic;
signal is_vlan : std_logic;
constant c_fixed_latency_zero : unsigned(27 downto 0) := (others => '0');
constant c_timestamper_delay : unsigned(27 downto 0) := to_unsigned(3, 28); -- cycles
......@@ -374,6 +375,7 @@ begin -- rtl
rx_latency_valid <= '0';
blocks_lost <= '0';
pack_data <= (others=>'0');
is_vlan <= '0';
else
case state is
when IDLE =>
......@@ -396,6 +398,7 @@ begin -- rtl
blocks_lost <= '0';
rx_latency <= (others=>'0');
rx_latency_valid <= '0';
is_vlan <= '0';
if(fsm_in.sof = '1') then
state <= HEADER;
......@@ -437,21 +440,43 @@ begin -- rtl
end if;
count <= count + 1;
when x"06" =>
if(fsm_in.data /= rx_streamer_cfg_i.ethertype) then
state <= IDLE;
if(fsm_in.data = x"8100") then
is_vlan <='1';
elsif(fsm_in.data /= rx_streamer_cfg_i.ethertype) then
state <= IDLE;
is_vlan <='0';
end if;
count <= count + 1;
when x"07" =>
tx_tag_valid <= fsm_in.data(15);
tx_tag_cycles(27 downto 16)<= fsm_in.data(11 downto 0);
if(is_vlan = '0') then
tx_tag_valid <= fsm_in.data(15);
tx_tag_cycles(27 downto 16)<= fsm_in.data(11 downto 0);
end if;
count <= count + 1;
when x"08" =>
if(is_vlan = '0') then
tx_tag_cycles(15 downto 0) <= fsm_in.data;
count <= count + 1;
crc_en <= '1';
detect_escapes <= '1';
state <= FRAME_SEQ_ID;
rx_frame_p1_o <= '1';
elsif(fsm_in.data /= rx_streamer_cfg_i.ethertype) then
state <= IDLE;
end if;
count <= count + 1;
when x"09" =>
tx_tag_valid <= fsm_in.data(15);
tx_tag_cycles(27 downto 16)<= fsm_in.data(11 downto 0);
count <= count + 1;
when x"0A" =>
tx_tag_cycles(15 downto 0) <= fsm_in.data;
count <= count + 1;
crc_en <= '1';
detect_escapes <= '1';
state <= FRAME_SEQ_ID;
rx_frame_p1_o <= '1';
rx_frame_p1_o <= '1';
count <= count + 1;
when others => null;
end case;
end if;
......
modules/wr_streamers/xtx_streamer.vhd
View file @ 9ad5c482
......@@ -176,7 +176,8 @@ architecture rtl of xtx_streamer is
signal link_ok_delay_cnt : unsigned(25 downto 0);
constant c_link_ok_rst_delay : unsigned(25 downto 0) := to_unsigned(62500000, 26);-- 1s
constant c_link_ok_rst_delay_sim : unsigned(25 downto 0) := to_unsigned(6250 , 26); -- 100us
constant c_link_ok_rst_delay_sim : unsigned(25 downto 0) := to_unsigned(6250 , 26);-- 100us
begin -- rtl
......@@ -411,15 +412,34 @@ begin -- rtl
fsm_out.data <= tx_streamer_cfg_i.mac_local(15 downto 0);
count <= count + 1;
when x"06" =>
fsm_out.data <= tx_streamer_cfg_i.ethertype;
if(tx_streamer_cfg_i.qtag_ena = '0') then
fsm_out.data <= tx_streamer_cfg_i.ethertype;
else
fsm_out.data <= x"8100";
end if;
count <= count + 1;
when x"07" =>
fsm_out.data <= tag_valid_latched & "000" & tag_cycles(27 downto 16);
if(tx_streamer_cfg_i.qtag_ena = '0') then
fsm_out.data <= tag_valid_latched & "000" & tag_cycles(27 downto 16);
else
fsm_out.data <= tx_streamer_cfg_i.qtag_prio & '0' & tx_streamer_cfg_i.qtag_vid;
end if;
count <= count + 1;
when x"08" =>
fsm_out.data <= tag_cycles(15 downto 0);
if(tx_streamer_cfg_i.qtag_ena = '0') then
fsm_out.data <= tag_cycles(15 downto 0);
state <= FRAME_SEQ_ID;
else
fsm_out.data <= tx_streamer_cfg_i.ethertype;
end if;
count <= count + 1;
when x"09" =>
fsm_out.data <= tag_valid_latched & "000" & tag_cycles(27 downto 16);
count <= count + 1;
when x"0A" =>
fsm_out.data <= tag_cycles(15 downto 0);
state <= FRAME_SEQ_ID;
count <= count + 1;
when others =>
fsm_out.data <= (others => 'X');
count <= (others => 'X');
......
modules/wr_streamers/xwr_streamers.vhd
View file @ 9ad5c482
......@@ -416,6 +416,13 @@ begin
tx_streamer_cfg.mac_target <= from_wb.tx_cfg4_mac_target_msb_o &
from_wb.tx_cfg3_mac_target_lsb_o when (from_wb.cfg_or_tx_mac_tar_o='1') else
tx_streamer_cfg_i.mac_target;
tx_streamer_cfg.qtag_ena <= from_wb.tx_cfg5_qtag_ena_o when (from_wb.cfg_or_tx_qtag_o='1') else
tx_streamer_cfg_i.qtag_ena;
tx_streamer_cfg.qtag_vid <= from_wb.tx_cfg5_qtag_vid_o when (from_wb.cfg_or_tx_qtag_o='1') else
tx_streamer_cfg_i.qtag_vid;
tx_streamer_cfg.qtag_prio <= from_wb.tx_cfg5_qtag_prio_o when (from_wb.cfg_or_tx_qtag_o='1') else
tx_streamer_cfg_i.qtag_prio;
-- rx config
rx_streamer_cfg.ethertype <= from_wb.rx_cfg0_ethertype_o when (from_wb.cfg_or_rx_ethertype_o='1') else
rx_streamer_cfg_i.ethertype;
......
sim/wr_streamers_wb.svh
View file @ 9ad5c482
......@@ -54,35 +54,44 @@
`define ADDR_WR_STREAMERS_TX_CFG4 7'h3c
`define WR_STREAMERS_TX_CFG4_MAC_TARGET_MSB_OFFSET 0
`define WR_STREAMERS_TX_CFG4_MAC_TARGET_MSB 32'h0000ffff
`define ADDR_WR_STREAMERS_RX_CFG0 7'h40
`define ADDR_WR_STREAMERS_TX_CFG5 7'h40
`define WR_STREAMERS_TX_CFG5_QTAG_ENA_OFFSET 0
`define WR_STREAMERS_TX_CFG5_QTAG_ENA 32'h00000001
`define WR_STREAMERS_TX_CFG5_QTAG_VID_OFFSET 8
`define WR_STREAMERS_TX_CFG5_QTAG_VID 32'h000fff00
`define WR_STREAMERS_TX_CFG5_QTAG_PRIO_OFFSET 24
`define WR_STREAMERS_TX_CFG5_QTAG_PRIO 32'h07000000
`define ADDR_WR_STREAMERS_RX_CFG0 7'h44
`define WR_STREAMERS_RX_CFG0_ETHERTYPE_OFFSET 0
`define WR_STREAMERS_RX_CFG0_ETHERTYPE 32'h0000ffff
`define WR_STREAMERS_RX_CFG0_ACCEPT_BROADCAST_OFFSET 16
`define WR_STREAMERS_RX_CFG0_ACCEPT_BROADCAST 32'h00010000
`define WR_STREAMERS_RX_CFG0_FILTER_REMOTE_OFFSET 17
`define WR_STREAMERS_RX_CFG0_FILTER_REMOTE 32'h00020000
`define ADDR_WR_STREAMERS_RX_CFG1 7'h44
`define ADDR_WR_STREAMERS_RX_CFG1 7'h48
`define WR_STREAMERS_RX_CFG1_MAC_LOCAL_LSB_OFFSET 0
`define WR_STREAMERS_RX_CFG1_MAC_LOCAL_LSB 32'hffffffff
`define ADDR_WR_STREAMERS_RX_CFG2 7'h48
`define ADDR_WR_STREAMERS_RX_CFG2 7'h4c
`define WR_STREAMERS_RX_CFG2_MAC_LOCAL_MSB_OFFSET 0
`define WR_STREAMERS_RX_CFG2_MAC_LOCAL_MSB 32'h0000ffff
`define ADDR_WR_STREAMERS_RX_CFG3 7'h4c
`define ADDR_WR_STREAMERS_RX_CFG3 7'h50
`define WR_STREAMERS_RX_CFG3_MAC_REMOTE_LSB_OFFSET 0
`define WR_STREAMERS_RX_CFG3_MAC_REMOTE_LSB 32'hffffffff
`define ADDR_WR_STREAMERS_RX_CFG4 7'h50
`define ADDR_WR_STREAMERS_RX_CFG4 7'h54
`define WR_STREAMERS_RX_CFG4_MAC_REMOTE_MSB_OFFSET 0
`define WR_STREAMERS_RX_CFG4_MAC_REMOTE_MSB 32'h0000ffff
`define ADDR_WR_STREAMERS_RX_CFG5 7'h54
`define ADDR_WR_STREAMERS_RX_CFG5 7'h58
`define WR_STREAMERS_RX_CFG5_FIXED_LATENCY_OFFSET 0
`define WR_STREAMERS_RX_CFG5_FIXED_LATENCY 32'h0fffffff
`define ADDR_WR_STREAMERS_CFG 7'h58
`define ADDR_WR_STREAMERS_CFG 7'h5c
`define WR_STREAMERS_CFG_OR_TX_ETHTYPE_OFFSET 0
`define WR_STREAMERS_CFG_OR_TX_ETHTYPE 32'h00000001
`define WR_STREAMERS_CFG_OR_TX_MAC_LOC_OFFSET 1
`define WR_STREAMERS_CFG_OR_TX_MAC_LOC 32'h00000002
`define WR_STREAMERS_CFG_OR_TX_MAC_TAR_OFFSET 2
`define WR_STREAMERS_CFG_OR_TX_MAC_TAR 32'h00000004
`define WR_STREAMERS_CFG_OR_TX_QTAG_OFFSET 3
`define WR_STREAMERS_CFG_OR_TX_QTAG 32'h00000008
`define WR_STREAMERS_CFG_OR_RX_ETHERTYPE_OFFSET 16
`define WR_STREAMERS_CFG_OR_RX_ETHERTYPE 32'h00010000
`define WR_STREAMERS_CFG_OR_RX_MAC_LOC_OFFSET 17
......@@ -95,12 +104,12 @@
`define WR_STREAMERS_CFG_OR_RX_FTR_REMOTE 32'h00100000
`define WR_STREAMERS_CFG_OR_RX_FIX_LAT_OFFSET 21
`define WR_STREAMERS_CFG_OR_RX_FIX_LAT 32'h00200000
`define ADDR_WR_STREAMERS_DBG_CTRL 7'h5c
`define ADDR_WR_STREAMERS_DBG_CTRL 7'h60
`define WR_STREAMERS_DBG_CTRL_MUX_OFFSET 0
`define WR_STREAMERS_DBG_CTRL_MUX 32'h00000001
`define WR_STREAMERS_DBG_CTRL_START_BYTE_OFFSET 8
`define WR_STREAMERS_DBG_CTRL_START_BYTE 32'h0000ff00
`define ADDR_WR_STREAMERS_DBG_DATA 7'h60
`define ADDR_WR_STREAMERS_DUMMY 7'h64
`define ADDR_WR_STREAMERS_DBG_DATA 7'h64
`define ADDR_WR_STREAMERS_DUMMY 7'h68
`define WR_STREAMERS_DUMMY_DUMMY_OFFSET 0
`define WR_STREAMERS_DUMMY_DUMMY 32'hffffffff
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