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Commit 9dab8265 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski Committed by Maciej Lipinski
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platform/xilinx/wr_gth_phy: first version of Ultrascale GTH transceiver wrapper

parent 69cc4cc3
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platform/xilinx/Manifest.py
View file @ 9dab8265
files = [ "wr_xilinx_pkg.vhd", "xwrc_platform_xilinx.vhd" ]
modules = {"local" : ["wr_gtp_phy", "chipscope"]}
modules = {"local" : ["wr_gtp_phy", "chipscope", "ip"]}
platform/xilinx/ip/Manifest.py 0 → 100644
View file @ 9dab8265
files = [
"common/gtwizard_ultrascale_v1_6_bit_sync.v",
"common/gtwizard_ultrascale_v1_6_gthe3_cal_freqcnt.v",
"common/gtwizard_ultrascale_v1_6_gthe3_cpll_cal.v",
"common/gtwizard_ultrascale_v1_6_gthe4_cal_freqcnt.v",
"common/gtwizard_ultrascale_v1_6_gthe4_cpll_cal.v",
"common/gtwizard_ultrascale_v1_6_gtwiz_buffbypass_rx.v",
"common/gtwizard_ultrascale_v1_6_gtwiz_buffbypass_tx.v",
"common/gtwizard_ultrascale_v1_6_gtwiz_reset.v",
"common/gtwizard_ultrascale_v1_6_gtwiz_userclk_rx.v",
"common/gtwizard_ultrascale_v1_6_gtwiz_userclk_tx.v",
"common/gtwizard_ultrascale_v1_6_gtwiz_userdata_rx.v",
"common/gtwizard_ultrascale_v1_6_gtwiz_userdata_tx.v",
"common/gtwizard_ultrascale_v1_6_gtye4_cal_freqcnt.v",
"common/gtwizard_ultrascale_v1_6_gtye4_cpll_cal.v",
"common/gtwizard_ultrascale_v1_6_reset_inv_sync.v",
"common/gtwizard_ultrascale_v1_6_reset_sync.v",
"example/wr_gth_wrapper_example_bit_sync.v",
"example/wr_gth_wrapper_example_checking_8b10b.v",
"example/wr_gth_wrapper_example_gtwiz_userclk_rx.v",
"example/wr_gth_wrapper_example_gtwiz_userclk_tx.v",
"example/wr_gth_wrapper_example_init.v",
"example/wr_gth_wrapper_example_reset_sync.v",
"example/wr_gth_wrapper_example_stimulus_8b10b.v",
"example/wr_gth_wrapper_example_top_sim.v",
"example/wr_gth_wrapper_example_top.v",
"example/wr_gth_wrapper_example_top.xdc",
"example/wr_gth_wrapper_example_wrapper.v",
"example/wr_gth_wrapper_prbs_any.v",
"synth/gtwizard_ultrascale_v1_6_gthe3_channel.v",
"synth/wr_gth_wrapper_gthe3_channel_wrapper.v",
"synth/wr_gth_wrapper_gtwizard_gthe3.v",
"synth/wr_gth_wrapper_gtwizard_top.v",
"synth/wr_gth_wrapper.v" ];
platform/xilinx/ip/common/gtwizard_ultrascale_v1_6_bit_sync.v 0 → 100644
View file @ 9dab8265
//------------------------------------------------------------------------------
// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//------------------------------------------------------------------------------
// ***************************
// * DO NOT MODIFY THIS FILE *
// ***************************
`timescale 1ps/1ps
module gtwizard_ultrascale_v1_6_5_bit_synchronizer # (
parameter INITIALIZE = 5'b00000,
parameter FREQUENCY = 512
)(
input wire clk_in,
input wire i_in,
output wire o_out
);
// Use 5 flip-flops as a single synchronizer, and tag each declaration with the appropriate synthesis attribute to
// enable clustering. Their GSR default values are provided by the INITIALIZE parameter.
(* ASYNC_REG = "TRUE" *) reg i_in_meta = INITIALIZE[0];
(* ASYNC_REG = "TRUE" *) reg i_in_sync1 = INITIALIZE[1];
(* ASYNC_REG = "TRUE" *) reg i_in_sync2 = INITIALIZE[2];
(* ASYNC_REG = "TRUE" *) reg i_in_sync3 = INITIALIZE[3];
reg i_in_out = INITIALIZE[4];
always @(posedge clk_in) begin
i_in_meta <= i_in;
i_in_sync1 <= i_in_meta;
i_in_sync2 <= i_in_sync1;
i_in_sync3 <= i_in_sync2;
i_in_out <= i_in_sync3;
end
assign o_out = i_in_out;
endmodule
platform/xilinx/ip/common/gtwizard_ultrascale_v1_6_gthe3_cal_freqcnt.v 0 → 100644
View file @ 9dab8265
//------------------------------------------------------------------------------
// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//------------------------------------------------------------------------------
// ***************************
// * DO NOT MODIFY THIS FILE *
// ***************************
`timescale 1ps/1ps
module gtwizard_ultrascale_v1_6_5_gthe3_cpll_cal_freq_counter # (
parameter REVISION = 1
)(
output reg [17:0] freq_cnt_o = 18'd0,
output reg done_o,
input wire rst_i,
input wire [15:0] test_term_cnt_i,
input wire ref_clk_i,
input wire test_clk_i
);
//****************************************************************************
// Local Parameters
//****************************************************************************
localparam RESET_STATE = 0;
localparam MEASURE_STATE = 1;
localparam HOLD_STATE = 2;
localparam UPDATE_STATE = 3;
localparam DONE_STATE = 4;
//****************************************************************************
// Local Signals
//****************************************************************************
reg [17:0] testclk_cnt = 18'h00000;
reg [15:0] refclk_cnt = 16'h0000;
reg [3:0] testclk_div4 = 4'h1;
wire testclk_rst;
wire testclk_en;
reg [5:0] hold_clk = 6'd0;
reg [4:0] state = 5'd1;
(* ASYNC_REG = "TRUE" *) reg tstclk_rst_dly1, tstclk_rst_dly2;
(* ASYNC_REG = "TRUE" *) reg testclk_en_dly1, testclk_en_dly2;
//
// need to get testclk_rst into TESTCLK_I domain
//
always @(posedge test_clk_i)
begin
tstclk_rst_dly1 <= testclk_rst;
tstclk_rst_dly2 <= tstclk_rst_dly1;
end
//
// need to get testclk_en into TESTCLK_I domain
//
always @(posedge test_clk_i)
begin
testclk_en_dly1 <= testclk_en;
testclk_en_dly2 <= testclk_en_dly1;
end
always @(posedge test_clk_i)
begin
if (tstclk_rst_dly2 == 1'b1)
begin
testclk_div4 <= 4'h1;
end
else
begin
testclk_div4 <= {testclk_div4[2:0], testclk_div4[3]};
end
end
wire testclk_rst_sync;
gtwizard_ultrascale_v1_6_5_reset_synchronizer reset_synchronizer_testclk_rst_inst (
.clk_in (test_clk_i),
.rst_in (testclk_rst),
.rst_out (testclk_rst_sync)
);
always @(posedge test_clk_i or posedge testclk_rst_sync)
begin
if (testclk_rst_sync == 1'b1)
begin
testclk_cnt <= 0;
end
else if (testclk_en_dly2 == 1'b1 && testclk_div4 == 4'h8)
begin
testclk_cnt <= testclk_cnt + 1;
end
end
/* always @(posedge test_clk_i or posedge testclk_rst)
begin
if (testclk_rst == 1'b1)
begin
testclk_cnt <= 0;
end
else if (testclk_en_dly2 == 1'b1 && testclk_div4 == 4'h8)
begin
testclk_cnt <= testclk_cnt + 1;
end
end */
always @(posedge ref_clk_i or posedge rst_i)
begin
if (rst_i)
done_o <= 1'b0;
else
done_o <= state[DONE_STATE];
end
always @(posedge ref_clk_i or posedge rst_i)
begin
if (rst_i) begin
state <= 0;
state[RESET_STATE] <= 1'b1;
end
else begin
state <= 0;
case (1'b1) // synthesis parallel_case full_case
state[RESET_STATE]:
begin
if (hold_clk == 6'h3F)
state[MEASURE_STATE] <= 1'b1;
else
state[RESET_STATE] <= 1'b1;
end
state[MEASURE_STATE]:
begin
if (refclk_cnt == test_term_cnt_i)
state[HOLD_STATE] <= 1'b1;
else
state[MEASURE_STATE] <= 1'b1;
end
state[HOLD_STATE]:
begin
if (hold_clk == 6'hF)
state[UPDATE_STATE] <= 1'b1;
else
state[HOLD_STATE] <= 1'b1;
end
state[UPDATE_STATE]:
begin
freq_cnt_o <= testclk_cnt;
state[DONE_STATE] <= 1'b1;
end
state[DONE_STATE]:
begin
state[DONE_STATE] <= 1'b1;
end
endcase
end
end
assign testclk_rst = state[RESET_STATE];
assign testclk_en = state[MEASURE_STATE];
always @(posedge ref_clk_i)
begin
if (state[RESET_STATE] == 1'b1 || state[HOLD_STATE] == 1'b1)
hold_clk <= hold_clk + 1;
else
hold_clk <= 0;
end
always @(posedge ref_clk_i)
begin
if (state[MEASURE_STATE] == 1'b1)
refclk_cnt <= refclk_cnt + 1;
else
refclk_cnt <= 0;
end
endmodule
platform/xilinx/ip/common/gtwizard_ultrascale_v1_6_gthe4_cal_freqcnt.v 0 → 100644
View file @ 9dab8265
//------------------------------------------------------------------------------
// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//------------------------------------------------------------------------------
// ***************************
// * DO NOT MODIFY THIS FILE *
// ***************************
`timescale 1ps/1ps
module gtwizard_ultrascale_v1_6_5_gthe4_cpll_cal_freq_counter # (
parameter REVISION = 1
)(
output reg [17:0] freq_cnt_o = 18'd0,
output reg done_o,
input wire rst_i,
input wire [15:0] test_term_cnt_i,
input wire ref_clk_i,
input wire test_clk_i
);
//****************************************************************************
// Local Parameters
//****************************************************************************
localparam RESET_STATE = 0;
localparam MEASURE_STATE = 1;
localparam HOLD_STATE = 2;
localparam UPDATE_STATE = 3;
localparam DONE_STATE = 4;
//****************************************************************************
// Local Signals
//****************************************************************************
reg [17:0] testclk_cnt = 18'h00000;
reg [15:0] refclk_cnt = 16'h0000;
reg [3:0] testclk_div4 = 4'h1;
wire testclk_rst;
wire testclk_en;
reg [5:0] hold_clk = 6'd0;
reg [4:0] state = 5'd1;
(* ASYNC_REG = "TRUE" *) reg tstclk_rst_dly1, tstclk_rst_dly2;
(* ASYNC_REG = "TRUE" *) reg testclk_en_dly1, testclk_en_dly2;
//
// need to get testclk_rst into TESTCLK_I domain
//
always @(posedge test_clk_i)
begin
tstclk_rst_dly1 <= testclk_rst;
tstclk_rst_dly2 <= tstclk_rst_dly1;
end
//
// need to get testclk_en into TESTCLK_I domain
//
always @(posedge test_clk_i)
begin
testclk_en_dly1 <= testclk_en;
testclk_en_dly2 <= testclk_en_dly1;
end
always @(posedge test_clk_i)
begin
if (tstclk_rst_dly2 == 1'b1)
begin
testclk_div4 <= 4'h1;
end
else
begin
testclk_div4 <= {testclk_div4[2:0], testclk_div4[3]};
end
end
wire testclk_rst_sync;
gtwizard_ultrascale_v1_6_5_reset_synchronizer reset_synchronizer_testclk_rst_inst (
.clk_in (test_clk_i),
.rst_in (testclk_rst),
.rst_out (testclk_rst_sync)
);
always @(posedge test_clk_i or posedge testclk_rst_sync)
begin
if (testclk_rst_sync == 1'b1)
begin
testclk_cnt <= 0;
end
else if (testclk_en_dly2 == 1'b1 && testclk_div4 == 4'h8)
begin
testclk_cnt <= testclk_cnt + 1;
end
end
/* always @(posedge test_clk_i or posedge testclk_rst)
begin
if (testclk_rst == 1'b1)
begin
testclk_cnt <= 0;
end
else if (testclk_en_dly2 == 1'b1 && testclk_div4 == 4'h8)
begin
testclk_cnt <= testclk_cnt + 1;
end
end */
always @(posedge ref_clk_i or posedge rst_i)
begin
if (rst_i)
done_o <= 1'b0;
else
done_o <= state[DONE_STATE];
end
always @(posedge ref_clk_i or posedge rst_i)
begin
if (rst_i) begin
state <= 0;
state[RESET_STATE] <= 1'b1;
end
else begin
state <= 0;
case (1'b1) // synthesis parallel_case full_case
state[RESET_STATE]:
begin
if (hold_clk == 6'h3F)
state[MEASURE_STATE] <= 1'b1;
else
state[RESET_STATE] <= 1'b1;
end
state[MEASURE_STATE]:
begin
if (refclk_cnt == test_term_cnt_i)
state[HOLD_STATE] <= 1'b1;
else
state[MEASURE_STATE] <= 1'b1;
end
state[HOLD_STATE]:
begin
if (hold_clk == 6'hF)
state[UPDATE_STATE] <= 1'b1;
else
state[HOLD_STATE] <= 1'b1;
end
state[UPDATE_STATE]:
begin
freq_cnt_o <= testclk_cnt;
state[DONE_STATE] <= 1'b1;
end
state[DONE_STATE]:
begin
state[DONE_STATE] <= 1'b1;
end
endcase
end
end
assign testclk_rst = state[RESET_STATE];
assign testclk_en = state[MEASURE_STATE];
always @(posedge ref_clk_i)
begin
if (state[RESET_STATE] == 1'b1 || state[HOLD_STATE] == 1'b1)
hold_clk <= hold_clk + 1;
else
hold_clk <= 0;
end
always @(posedge ref_clk_i)
begin
if (state[MEASURE_STATE] == 1'b1)
refclk_cnt <= refclk_cnt + 1;
else
refclk_cnt <= 0;
end
endmodule
platform/xilinx/ip/common/gtwizard_ultrascale_v1_6_gtwiz_userclk_rx.v 0 → 100644
View file @ 9dab8265
//------------------------------------------------------------------------------
// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//------------------------------------------------------------------------------
// ***************************
// * DO NOT MODIFY THIS FILE *
// ***************************
`timescale 1ps/1ps
module gtwizard_ultrascale_v1_6_5_gtwiz_userclk_rx #(
parameter integer P_CONTENTS = 0,
parameter integer P_FREQ_RATIO_SOURCE_TO_USRCLK = 1,
parameter integer P_FREQ_RATIO_USRCLK_TO_USRCLK2 = 1
)(
input wire gtwiz_userclk_rx_srcclk_in,
input wire gtwiz_userclk_rx_reset_in,
output wire gtwiz_userclk_rx_usrclk_out,
output wire gtwiz_userclk_rx_usrclk2_out,
output wire gtwiz_userclk_rx_active_out
);
// -------------------------------------------------------------------------------------------------------------------
// Local parameters
// -------------------------------------------------------------------------------------------------------------------
// Convert integer parameters with known, limited legal range to a 3-bit local parameter values
localparam integer P_USRCLK_INT_DIV = P_FREQ_RATIO_SOURCE_TO_USRCLK - 1;
localparam [2:0] P_USRCLK_DIV = P_USRCLK_INT_DIV[2:0];
localparam integer P_USRCLK2_INT_DIV = (P_FREQ_RATIO_SOURCE_TO_USRCLK * P_FREQ_RATIO_USRCLK_TO_USRCLK2) - 1;
localparam [2:0] P_USRCLK2_DIV = P_USRCLK2_INT_DIV[2:0];
// -------------------------------------------------------------------------------------------------------------------
// Receiver user clocking network conditional generation, based on parameter values in module instantiation
// -------------------------------------------------------------------------------------------------------------------
generate if (1) begin: gen_gtwiz_userclk_rx_main
// Use BUFG_GT instance(s) to drive RXUSRCLK and RXUSRCLK2, inferred for integral source to RXUSRCLK frequency ratio
if (P_CONTENTS == 0) begin
// Drive RXUSRCLK with BUFG_GT-buffered source clock, dividing the input by the integral source clock to RXUSRCLK
// frequency ratio
BUFG_GT bufg_gt_usrclk_inst (
.CE (1'b1),
.CEMASK (1'b0),
.CLR (gtwiz_userclk_rx_reset_in),
.CLRMASK (1'b0),
.DIV (P_USRCLK_DIV),
.I (gtwiz_userclk_rx_srcclk_in),
.O (gtwiz_userclk_rx_usrclk_out)
);
// If RXUSRCLK and RXUSRCLK2 frequencies are identical, drive both from the same BUFG_GT. Otherwise, drive
// RXUSRCLK2 from a second BUFG_GT instance, dividing the source clock down to the RXUSRCLK2 frequency.
if (P_FREQ_RATIO_USRCLK_TO_USRCLK2 == 1)
assign gtwiz_userclk_rx_usrclk2_out = gtwiz_userclk_rx_usrclk_out;
else begin
BUFG_GT bufg_gt_usrclk2_inst (
.CE (1'b1),
.CEMASK (1'b0),
.CLR (gtwiz_userclk_rx_reset_in),
.CLRMASK (1'b0),
.DIV (P_USRCLK2_DIV),
.I (gtwiz_userclk_rx_srcclk_in),
.O (gtwiz_userclk_rx_usrclk2_out)
);
end
// Indicate active helper block functionality when the BUFG_GT divider is not held in reset
(* ASYNC_REG = "TRUE" *) reg gtwiz_userclk_rx_active_meta = 1'b0;
(* ASYNC_REG = "TRUE" *) reg gtwiz_userclk_rx_active_sync = 1'b0;
always @(posedge gtwiz_userclk_rx_usrclk2_out, posedge gtwiz_userclk_rx_reset_in) begin
if (gtwiz_userclk_rx_reset_in) begin
gtwiz_userclk_rx_active_meta <= 1'b0;
gtwiz_userclk_rx_active_sync <= 1'b0;
end
else begin
gtwiz_userclk_rx_active_meta <= 1'b1;
gtwiz_userclk_rx_active_sync <= gtwiz_userclk_rx_active_meta;
end
end
assign gtwiz_userclk_rx_active_out = gtwiz_userclk_rx_active_sync;
end
end
endgenerate
endmodule
platform/xilinx/ip/common/gtwizard_ultrascale_v1_6_gtwiz_userclk_tx.v 0 → 100644
View file @ 9dab8265
//------------------------------------------------------------------------------
// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//------------------------------------------------------------------------------
// ***************************
// * DO NOT MODIFY THIS FILE *
// ***************************
`timescale 1ps/1ps
module gtwizard_ultrascale_v1_6_5_gtwiz_userclk_tx #(
parameter integer P_CONTENTS = 0,
parameter integer P_FREQ_RATIO_SOURCE_TO_USRCLK = 1,
parameter integer P_FREQ_RATIO_USRCLK_TO_USRCLK2 = 1
)(
input wire gtwiz_userclk_tx_srcclk_in,
input wire gtwiz_userclk_tx_reset_in,
output wire gtwiz_userclk_tx_usrclk_out,
output wire gtwiz_userclk_tx_usrclk2_out,
output wire gtwiz_userclk_tx_active_out
);
// -------------------------------------------------------------------------------------------------------------------
// Local parameters
// -------------------------------------------------------------------------------------------------------------------
// Convert integer parameters with known, limited legal range to a 3-bit local parameter values
localparam integer P_USRCLK_INT_DIV = P_FREQ_RATIO_SOURCE_TO_USRCLK - 1;
localparam [2:0] P_USRCLK_DIV = P_USRCLK_INT_DIV[2:0];
localparam integer P_USRCLK2_INT_DIV = (P_FREQ_RATIO_SOURCE_TO_USRCLK * P_FREQ_RATIO_USRCLK_TO_USRCLK2) - 1;
localparam [2:0] P_USRCLK2_DIV = P_USRCLK2_INT_DIV[2:0];
// -------------------------------------------------------------------------------------------------------------------
// Transmitter user clocking network conditional generation, based on parameter values in module instantiation
// -------------------------------------------------------------------------------------------------------------------
generate if (1) begin: gen_gtwiz_userclk_tx_main
// Use BUFG_GT instance(s) to drive TXUSRCLK and TXUSRCLK2, inferred for integral source to TXUSRCLK frequency ratio
if (P_CONTENTS == 0) begin
// Drive TXUSRCLK with BUFG_GT-buffered source clock, dividing the input by the integral source clock to TXUSRCLK
// frequency ratio
BUFG_GT bufg_gt_usrclk_inst (
.CE (1'b1),
.CEMASK (1'b0),
.CLR (gtwiz_userclk_tx_reset_in),
.CLRMASK (1'b0),
.DIV (P_USRCLK_DIV),
.I (gtwiz_userclk_tx_srcclk_in),
.O (gtwiz_userclk_tx_usrclk_out)
);
// If TXUSRCLK and TXUSRCLK2 frequencies are identical, drive both from the same BUFG_GT. Otherwise, drive
// TXUSRCLK2 from a second BUFG_GT instance, dividing the source clock down to the TXUSRCLK2 frequency.
if (P_FREQ_RATIO_USRCLK_TO_USRCLK2 == 1)
assign gtwiz_userclk_tx_usrclk2_out = gtwiz_userclk_tx_usrclk_out;
else begin
BUFG_GT bufg_gt_usrclk2_inst (
.CE (1'b1),
.CEMASK (1'b0),
.CLR (gtwiz_userclk_tx_reset_in),
.CLRMASK (1'b0),
.DIV (P_USRCLK2_DIV),
.I (gtwiz_userclk_tx_srcclk_in),
.O (gtwiz_userclk_tx_usrclk2_out)
);
end
// Indicate active helper block functionality when the BUFG_GT divider is not held in reset
(* ASYNC_REG = "TRUE" *) reg gtwiz_userclk_tx_active_meta = 1'b0;
(* ASYNC_REG = "TRUE" *) reg gtwiz_userclk_tx_active_sync = 1'b0;
always @(posedge gtwiz_userclk_tx_usrclk2_out, posedge gtwiz_userclk_tx_reset_in) begin
if (gtwiz_userclk_tx_reset_in) begin
gtwiz_userclk_tx_active_meta <= 1'b0;
gtwiz_userclk_tx_active_sync <= 1'b0;
end
else begin
gtwiz_userclk_tx_active_meta <= 1'b1;
gtwiz_userclk_tx_active_sync <= gtwiz_userclk_tx_active_meta;
end
end
assign gtwiz_userclk_tx_active_out = gtwiz_userclk_tx_active_sync;
end
end
endgenerate
endmodule
platform/xilinx/ip/common/gtwizard_ultrascale_v1_6_gtye4_cal_freqcnt.v 0 → 100644
View file @ 9dab8265
//------------------------------------------------------------------------------
// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//------------------------------------------------------------------------------
// ***************************
// * DO NOT MODIFY THIS FILE *
// ***************************
`timescale 1ps/1ps
module gtwizard_ultrascale_v1_6_5_gtye4_cpll_cal_freq_counter # (
parameter REVISION = 1
)(
output reg [17:0] freq_cnt_o = 18'd0,
output reg done_o,
input wire rst_i,
input wire [15:0] test_term_cnt_i,
input wire ref_clk_i,
input wire test_clk_i
);
//****************************************************************************
// Local Parameters
//****************************************************************************
localparam RESET_STATE = 0;
localparam MEASURE_STATE = 1;
localparam HOLD_STATE = 2;
localparam UPDATE_STATE = 3;
localparam DONE_STATE = 4;
//****************************************************************************
// Local Signals
//****************************************************************************
reg [17:0] testclk_cnt = 18'h00000;
reg [15:0] refclk_cnt = 16'h0000;
reg [3:0] testclk_div4 = 4'h1;
wire testclk_rst;
wire testclk_en;
reg [5:0] hold_clk = 6'd0;
reg [4:0] state = 5'd1;
(* ASYNC_REG = "TRUE" *) reg tstclk_rst_dly1, tstclk_rst_dly2;
(* ASYNC_REG = "TRUE" *) reg testclk_en_dly1, testclk_en_dly2;
//
// need to get testclk_rst into TESTCLK_I domain
//
always @(posedge test_clk_i)
begin
tstclk_rst_dly1 <= testclk_rst;
tstclk_rst_dly2 <= tstclk_rst_dly1;
end
//
// need to get testclk_en into TESTCLK_I domain
//
always @(posedge test_clk_i)
begin
testclk_en_dly1 <= testclk_en;
testclk_en_dly2 <= testclk_en_dly1;
end
always @(posedge test_clk_i)
begin
if (tstclk_rst_dly2 == 1'b1)
begin
testclk_div4 <= 4'h1;
end
else
begin
testclk_div4 <= {testclk_div4[2:0], testclk_div4[3]};
end
end
wire testclk_rst_sync;
gtwizard_ultrascale_v1_6_5_reset_synchronizer reset_synchronizer_testclk_rst_inst (
.clk_in (test_clk_i),
.rst_in (testclk_rst),
.rst_out (testclk_rst_sync)
);
always @(posedge test_clk_i or posedge testclk_rst_sync)
begin
if (testclk_rst_sync == 1'b1)
begin
testclk_cnt <= 0;
end
else if (testclk_en_dly2 == 1'b1 && testclk_div4 == 4'h8)
begin
testclk_cnt <= testclk_cnt + 1;
end
end
/* always @(posedge test_clk_i or posedge testclk_rst)
begin
if (testclk_rst == 1'b1)
begin
testclk_cnt <= 0;
end
else if (testclk_en_dly2 == 1'b1 && testclk_div4 == 4'h8)
begin
testclk_cnt <= testclk_cnt + 1;
end
end */
always @(posedge ref_clk_i or posedge rst_i)
begin
if (rst_i)
done_o <= 1'b0;
else
done_o <= state[DONE_STATE];
end
always @(posedge ref_clk_i or posedge rst_i)
begin
if (rst_i) begin
state <= 0;
state[RESET_STATE] <= 1'b1;
end
else begin
state <= 0;
case (1'b1) // synthesis parallel_case full_case
state[RESET_STATE]:
begin
if (hold_clk == 6'h3F)
state[MEASURE_STATE] <= 1'b1;
else
state[RESET_STATE] <= 1'b1;
end
state[MEASURE_STATE]:
begin
if (refclk_cnt == test_term_cnt_i)
state[HOLD_STATE] <= 1'b1;
else
state[MEASURE_STATE] <= 1'b1;
end
state[HOLD_STATE]:
begin
if (hold_clk == 6'hF)
state[UPDATE_STATE] <= 1'b1;
else
state[HOLD_STATE] <= 1'b1;
end
state[UPDATE_STATE]:
begin
freq_cnt_o <= testclk_cnt;
state[DONE_STATE] <= 1'b1;
end
state[DONE_STATE]:
begin
state[DONE_STATE] <= 1'b1;
end
endcase
end
end
assign testclk_rst = state[RESET_STATE];
assign testclk_en = state[MEASURE_STATE];
always @(posedge ref_clk_i)
begin
if (state[RESET_STATE] == 1'b1 || state[HOLD_STATE] == 1'b1)
hold_clk <= hold_clk + 1;
else
hold_clk <= 0;
end
always @(posedge ref_clk_i)
begin
if (state[MEASURE_STATE] == 1'b1)
refclk_cnt <= refclk_cnt + 1;
else
refclk_cnt <= 0;
end
endmodule
platform/xilinx/ip/example/wr_gth_wrapper_example_bit_sync.v 0 → 100644
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platform/xilinx/wr_gtp_phy/Manifest.py
View file @ 9dab8265
......@@ -27,4 +27,6 @@ elif (syn_device[0:4].upper()=="XC7V"): # Family 7 GTH (other Virtex7 devices)
"whiterabbit_gthe2_channel_wrapper_gt.vhd",
"whiterabbit_gthe2_channel_wrapper_gtrxreset_seq.vhd",
"whiterabbit_gthe2_channel_wrapper_sync_block.vhd" ]);
\ No newline at end of file
elif (syn_device[0:5].upper()=="XC7KU"): # Kintex Ultrascale GTH
files.extend(["wr_gth_phy_kintex7ultrascale.vhd"]);
platform/xilinx/wr_gtp_phy/wr_gth_phy_kintex7ultrascale.vhd 0 → 100644
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