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9ddf4e64
Commit
9ddf4e64
authored
May 04, 2017
by
Denia Bouhired-Ferrag
Committed by
Grzegorz Daniluk
Jun 19, 2017
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early work on testbench + dimitris early version of oop testbench. Also adds html of memory map
parent
0c470a36
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wr_transmission_wb.htm
modules/wr_streamers/wr_transmission_wb.htm
+9509
-0
main.sv
testbench/wr_streamers/dlampridis_sv_oop/main.sv
+124
-0
tb_btrain_ref_design.sv
...ch/wr_streamers/dlampridis_sv_oop/tb_btrain_ref_design.sv
+119
-0
Manifest.py
testbench/wr_streamers/streamer-tb-class/Manifest.py
+15
-0
cstreamer-class.sv
testbench/wr_streamers/streamer-tb-class/cstreamer-class.sv
+70
-0
main.sv
testbench/wr_streamers/streamer-tb-class/main.sv
+349
-0
run.do
testbench/wr_streamers/streamer-tb-class/run.do
+11
-0
tcl_stacktrace.txt
testbench/wr_streamers/streamer-tb-class/tcl_stacktrace.txt
+25
-0
wave.do
testbench/wr_streamers/streamer-tb-class/wave.do
+42
-0
tcl_stacktrace.txt
...treamers/streamers-only_basic-transfer/tcl_stacktrace.txt
+4
-0
No files found.
modules/wr_streamers/wr_transmission_wb.htm
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9ddf4e64
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testbench/wr_streamers/dlampridis_sv_oop/main.sv
0 → 100644
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9ddf4e64
//-----------------------------------------------------------------------------
// Title : Testbench for verification of BTrain SPEC reference design
// Project : Btrain
//-----------------------------------------------------------------------------
// File : main.sv
// Author(s) : Maciej Lipinski <maciej.lipinski@cern.ch>
// Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
// Company : CERN (BE-CO-HT)
// Created : 2016-05-30
//-----------------------------------------------------------------------------
// Description:
//
// Simulation of two interconnected SPEC reference design modules (A and B):
// - both modules send and receive Bframes
// - Module A receives up/down/C0_reset pulses
//
// Please, note that the initialization of LM32 and the software takes
// some time, allow the simulation to run for ~5 minutes (at least 105us
// of simulation time)
//-----------------------------------------------------------------------------
//
// Copyright (c) 2016-2017 CERN
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, download it
// from http://www.gnu.org/licenses/lgpl-2.1.html
//
//-----------------------------------------------------------------------------
`timescale
1
ns
/
1
ps
`include
"gn4124_bfm.svh"
import
PBTrainRefDesign
::*;
module
main
;
bit
clk_125m_pllref
=
0
;
bit
clk_20m_vcxo
=
0
;
always
#
4
ns
clk_125m_pllref
<=
~
clk_125m_pllref
;
always
#
20
ns
clk_20m_vcxo
<=
~
clk_20m_vcxo
;
IGN4124PCIMaster
I_GennumA
()
;
IGN4124PCIMaster
I_GennumB
()
;
/// ///////////////////////////////////////////////////////////////////////////////////////
/// Instantiation of two interconnected SPECs
/// ///////////////////////////////////////////////////////////////////////////////////////
BtrainSpecTop
#(
.
g_simulation
(
1
)
,
.
g_dpram_initf
(
"../../ip_cores/wr-cores/bin/wrpc/wrc_phy8_sim.bram"
)
)
DUT_SPEC_A
(
.
clk_125m_pllref_p_i
(
clk_125m_pllref
)
,
.
clk_125m_pllref_n_i
(
~
clk_125m_pllref
)
,
.
clk_125m_gtp_p_i
(
clk_125m_pllref
)
,
.
clk_125m_gtp_n_i
(
~
clk_125m_pllref
)
,
.
clk_20m_vcxo_i
(
clk_20m_vcxo
)
,
.
sfp_txp_o
(
a_to_b_p_o
)
,
.
sfp_txn_o
(
a_to_b_n
)
,
.
sfp_rxp_i
(
b_to_a_p_i
)
,
.
sfp_rxn_i
(
b_to_a_n
)
,
`GENNUM_WIRE_SPEC_PINS_WITH_PROPER_NAMING
(
I_GennumA
)
)
;
BtrainSpecTop
#(
.
g_simulation
(
1
)
,
.
g_dpram_initf
(
"../../ip_cores/wr-cores/bin/wrpc/wrc_phy8_sim.bram"
)
)
DUT_SPEC_B
(
.
clk_125m_pllref_p_i
(
clk_125m_pllref
)
,
.
clk_125m_pllref_n_i
(
~
clk_125m_pllref
)
,
.
clk_125m_gtp_p_i
(
clk_125m_pllref
)
,
.
clk_125m_gtp_n_i
(
~
clk_125m_pllref
)
,
.
clk_20m_vcxo_i
(
clk_20m_vcxo
)
,
.
sfp_txp_o
(
b_to_a_p_o
)
,
.
sfp_txn_o
(
b_to_a_n
)
,
.
sfp_rxp_i
(
a_to_b_p_i
)
,
.
sfp_rxn_i
(
a_to_b_n
)
,
`GENNUM_WIRE_SPEC_PINS_WITH_PROPER_NAMING
(
I_GennumB
)
)
;
CBTrainRefDesign
ModA
=
new
(
I_GennumA
.
get_accessor
())
;
CBTrainRefDesign
ModB
=
new
(
I_GennumB
.
get_accessor
())
;
initial
begin
$
display
(
"test %d"
,
ModA
.
wrstream
.
is_present
)
;
$
finish
;
end
// initial begin
endmodule
// main
testbench/wr_streamers/dlampridis_sv_oop/tb_btrain_ref_design.sv
0 → 100644
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9ddf4e64
//-----------------------------------------------------------------------------
// Title : Definitions for BTrain reference design testbench
// Project : BTrain over White Rabbit
// URL : https://wikis.cern.ch/display/HT/Btrain+over+White+Rabbit
//-----------------------------------------------------------------------------
// File : tb_btrain_ref_design.sv
// Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
// Company : CERN (BE-CO-HT)
// Created : 2017-04-13
//-----------------------------------------------------------------------------
// Description:
//
// SystemVerilog package with all definitions, interfaces, etc. necessary
// for the BTrain reference design testbench.
//
//-----------------------------------------------------------------------------
//
// Copyright (c) 2017 CERN
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, download it
// from http://www.gnu.org/licenses/lgpl-2.1.html
//
//-----------------------------------------------------------------------------
package
PBTrainRefDesign
;
`include
"simdrv_defs.svh"
`include
"wr_transmission_wb.svh"
class
CWBPeriph
;
// Handle for all bus accesses
CBusAccessor
bus
;
// Offset in address map
uint32_t
base
;
function
new
(
const
ref
CBusAccessor
b
,
const
ref
uint32_t
addr
)
;
bus
=
b
;
base
=
addr
;
endfunction
// new
function
uint32_t
read32
(
uint32_t
offset
)
;
uint64_t
rval
;
fork
bus
.
read
(
base
+
offset
,
rval
,
4
)
;
join
return
uint32_t
'
(
rval
)
;
endfunction
// read32
task
write32
(
uint32_t
offset
,
wval
)
;
bus
.
write
(
base
+
offset
,
wval
,
4
)
;
endtask
// write32
endclass
;
// CWBPeriph
class
CWRStreamer
extends
CWBPeriph
;
const
uint32_t
c_DUMMY_VAL
=
'hDEADBEEF
;
function
new
(
const
ref
CBusAccessor
b
,
const
ref
uint32_t
addr
)
;
super
.
new
(
b
,
addr
)
;
endfunction
// new
function
bit
is_present
()
;
uint32_t
rval
=
read32
(
`ADDR_WR_TRANSMISSION_DUMMY
)
;
rval
=
(
`WR_TRANSMISSION_DUMMY_DUMMY
&
rval
)
>>
`WR_TRANSMISSION_DUMMY_DUMMY_OFFSET
;
if
(
c_DUMMY_VAL
==
rval
)
return
1
;
else
return
0
;
endfunction
// is_present
endclass
;
// CWRStreamer
class
CWRBTrain
extends
CWBPeriph
;
function
new
(
const
ref
CBusAccessor
b
,
const
ref
uint32_t
addr
)
;
super
.
new
(
b
,
addr
)
;
endfunction
// new
endclass
;
// CWRBTrain
class
CBTrainRefDesign
;
// base offsets/pointers for WR peripherals
const
uint32_t
c_BASE_WRPC
=
'h00040000
;
const
uint32_t
c_BASE_AUX_IN_WRPC
=
'h00020700
;
const
uint32_t
c_BASE_WRSTREAMERS
=
c_BASE_WRPC
+
c_BASE_AUX_IN_WRPC
;
const
uint32_t
c_BASE_WRBTRAIN
=
'h00001200
;
// Handles to WR streamer and BTrain WB peripherals
CWRStreamer
wrstream
;
CWRBTrain
wrbtrain
;
function
new
(
CBusAccessor
b
)
;
wrstream
=
new
(
b
,
c_BASE_WRSTREAMERS
)
;
wrbtrain
=
new
(
b
,
c_BASE_WRBTRAIN
)
;
endfunction
// new
endclass
// CBTRainRefDesign
endpackage
//PBTrainRefDesign
testbench/wr_streamers/streamer-tb-class/Manifest.py
0 → 100644
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9ddf4e64
action
=
"simulation"
target
=
"xilinx"
syn_device
=
"xc6slx45t"
sim_tool
=
"modelsim"
top_module
=
"main"
fetchto
=
"../../../ip_cores"
vlog_opt
=
"+incdir+../../../sim"
modules
=
{
"local"
:
[
"../../.."
,
"../../../modules/wr_streamers"
,
"../../../ip_cores/general-cores"
]}
files
=
[
"main.sv"
]
testbench/wr_streamers/streamer-tb-class/cstreamer-class.sv
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9ddf4e64
//-----------------------------------------------------------------------------
// Title : Definitions for WR streamers testbench
// Project : White Rabbit Cores
// URL : http://www.ohwr.org/projects/wr-cores/wiki/WR_Streamers
//-----------------------------------------------------------------------------
// File : wr-streamers-tb-class.sv
// Author(s) : Denia Bouhired <denia.bouhired@cern.ch>
// Company : CERN (BE-CO-HT)
// Created : 2017-04-28
//-----------------------------------------------------------------------------
// Description:
//
// SystemVerilog package with all definitions, interfaces, etc. necessary
// for the wr streamers testbench.
//
//-----------------------------------------------------------------------------
//
// Copyright (c) 2017 CERN
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, download it
// from http://www.gnu.org/licenses/lgpl-2.1.html
//
//-----------------------------------------------------------------------------
package
wr
-
streamers
-
tb
-
pkg
;
class
CWRSTREAMERS
;
int
data_width
bit
disable_escape_code
;
//Class constructor
function
new
(
input
int
width
=
32
,
bit
dis_esc
=
0
)
;
data_width
=
width
;
disable_escape_code
=
dis_esc
;
endfunction
endclass
;
//Transmitter class
class
CWRSTREAMERS_TX
extends
CWRSTREAMERS
;
function
endclass
;
//Receiver class
class
CWRSTREAMERS_RX
extends
CWRSTREAMERS
;
endclass
;
testbench/wr_streamers/streamer-tb-class/main.sv
0 → 100644
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9ddf4e64
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testbench/wr_streamers/streamer-tb-class/run.do
0 → 100644
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9ddf4e64
# make -f Makefile > /dev/null 2>&1
vsim -L unisim work.main -voptargs="+acc" -suppress 8684,8683
set NumericStdNoWarnings 1
set StdArithNoWarnings 1
do wave.do
run 10us
wave zoomfull
radix -hex
testbench/wr_streamers/streamer-tb-class/tcl_stacktrace.txt
0 → 100644
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9ddf4e64
Wed May 03 16:18:04 W. Europe Daylight Time 2017
Trace back: invalid command name ""
while executing
"$tree expandeditems -worm"
(procedure "_resetTree" line 6)
invoked from within
"_resetTree $w"
(procedure "QObjects::sort" line 4)
invoked from within
"QObjects::sort .main_pane.objects 0 ascending"
("eval" body line 1)
invoked from within
"eval $itk_option(-sortcommand) $column $dir"
(object "::.main_pane.objects.interior.cs.body.tree" method "::vsimwidgets::Hierarchy::sort" body line 26)
invoked from within
"sort $sortIdx $dir"
(object "::.main_pane.objects.interior.cs.body.tree" method "::vsimwidgets::Hierarchy::_initializeSortColumn" body line 10)
invoked from within
"::.main_pane.objects.interior.cs.body.tree _initializeSortColumn"
(in namespace inscope "::vsimwidgets::Hierarchy" script line 1)
invoked from within
"namespace inscope ::vsimwidgets::Hierarchy {::.main_pane.objects.interior.cs.body.tree _initializeSortColumn}"
("after" script)
<2: ::tkerror {invalid command name ""}
<1: ::bgerror {invalid command name ""}
testbench/wr_streamers/streamer-tb-class/wave.do
0 → 100644
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9ddf4e64
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /main/U_TX_Streamer/tx_flush_p1_i
add wave -noupdate /main/U_TX_Streamer/tx_last_p1_i
add wave -noupdate /main/U_TX_Streamer/tx_data_i
add wave -noupdate /main/U_TX_Streamer/tx_reset_seq_i
add wave -noupdate /main/U_TX_Streamer/tx_valid_i
add wave -noupdate /main/U_TX_Streamer/tx_dreq_o
add wave -noupdate /main/mac/adr
add wave -noupdate /main/mac/dat_o
add wave -noupdate /main/mac/dat_i
add wave -noupdate /main/mac/sel
add wave -noupdate /main/mac/ack
add wave -noupdate /main/mac/stall
add wave -noupdate /main/mac/err
add wave -noupdate /main/mac/rty
add wave -noupdate /main/mac/cyc
add wave -noupdate /main/mac/stb
add wave -noupdate /main/mac/we
add wave -noupdate /main/U_RX_Streamer/rx_first_p1_o
add wave -noupdate /main/U_RX_Streamer/rx_last_p1_o
add wave -noupdate /main/U_RX_Streamer/rx_data_o
add wave -noupdate /main/U_RX_Streamer/rx_valid_o
add wave -noupdate /main/U_RX_Streamer/rx_dreq_i
add wave -noupdate /main/U_RX_Streamer/rx_lost_p1_o
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {867 ns} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 ns} {915 ns}
testbench/wr_streamers/streamers-only_basic-transfer/tcl_stacktrace.txt
View file @
9ddf4e64
<<<<<<< Updated upstream
Tue Apr 04 11:10:53 W. Europe Daylight Time 2017
=======
Tue Apr 25 14:55:16 W. Europe Daylight Time 2017
>>>>>>> Stashed changes
Trace back: invalid command name ""
while executing
"$tree expandeditems -worm"
...
...
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