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White Rabbit core collection
Commit 9fb02603 authored by Wesley W. Terpstra's avatar Wesley W. Terpstra
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Fix the indentation of the SCU top file => remove tabs.

parent e00e3ee3
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Showing with 289 additions and 326 deletions
top/gsi_scu2/wr_core_demo/scu_top.vhd
View file @ 9fb02603
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gencores_pkg.all;
use work.wrcore_pkg.all;
......@@ -17,8 +16,7 @@ use work.wr_altera_pkg.all;
use work.lpc_uart_pkg.all;
entity scu_top is
port
(
port(
clk_20m_vcxo_i : in std_logic; -- 20MHz VCXO clock
clk_125m_pllref_p : in std_logic; -- 125 MHz PLL reference
......@@ -30,7 +28,6 @@ entity scu_top is
-----------------------------------------
uart_rxd_i : in std_logic_vector(1 downto 0);
uart_txd_o : out std_logic_vector(1 downto 0);
serial_to_cb_o : out std_logic;
-----------------------------------------
......@@ -55,7 +52,6 @@ entity scu_top is
lemo_en_in : out std_logic_vector(2 downto 1);
lemo_led : out std_logic_vector(2 downto 1);
-----------------------------------------------------------------------
-- LPC interface from ComExpress
-----------------------------------------------------------------------
......@@ -76,13 +72,12 @@ entity scu_top is
-----------------------------------------------------------------------
OneWire_CB : inout std_logic;
-----------------------------------------------------------------------
-- AUX SFP
-----------------------------------------------------------------------
sfp1_tx_disable_o : out std_logic;
--sfp1_txp_o : out std_logic;
--sfp1_rxp_i : in std_logic;
sfp1_txp_o : out std_logic;
sfp1_rxp_i : in std_logic;
sfp1_mod0 : in std_logic; -- grounded by module
sfp1_mod1 : inout std_logic; -- SCL
......@@ -102,14 +97,12 @@ entity scu_top is
-----------------------------------------------------------------------
-- LA port
-----------------------------------------------------------------------
hpla_ch : out std_logic_vector(15 downto 0);
hpla_clk : out std_logic;
-----------------------------------------------------------------------
-- EXT CONN
-----------------------------------------------------------------------
IO_2_5 : out std_logic_vector(13 downto 0);
A_EXT_LVDS_RX : in std_logic_vector(3 downto 0);
A_EXT_LVDS_TX : out std_logic_vector(3 downto 0);
......@@ -120,7 +113,6 @@ entity scu_top is
-----------------------------------------------------------------------
-- SCU Bus
-----------------------------------------------------------------------
A_D : inout std_logic_vector(15 downto 0);
A_A : out std_logic_vector(15 downto 0);
A_nTiming_Cycle : out std_logic;
......@@ -140,7 +132,6 @@ entity scu_top is
-----------------------------------------------------------------------
-- ComExpress signals
-----------------------------------------------------------------------
nTHRMTRIP : in std_logic;
nEXCD0_PERST : in std_logic;
WDT : in std_logic;
......@@ -148,7 +139,6 @@ entity scu_top is
-----------------------------------------------------------------------
-- Parallel Flash
-----------------------------------------------------------------------
AD : out std_logic_vector(25 downto 1);
DF : inout std_logic_vector(15 downto 0);
ADV_FSH : out std_logic;
......@@ -162,7 +152,6 @@ entity scu_top is
-----------------------------------------------------------------------
-- DDR3
-----------------------------------------------------------------------
DDR3_DQ : inout std_logic_vector(15 downto 0);
DDR3_DM : out std_logic_vector(1 downto 0);
DDR3_BA : out std_logic_vector(2 downto 0);
......@@ -182,19 +171,14 @@ entity scu_top is
-----------------------------------------------------------------------
-- Board configuration
-----------------------------------------------------------------------
A_nCONFIG : out std_logic; -- triggers reconfig
nPWRBTN : out std_logic; -- Powerbutton for ComExpress
nFPGA_Res_Out : out std_logic := '1' -- drives sys_reset
);
nFPGA_Res_Out : out std_logic := '1'); -- drives sys_reset
end scu_top;
architecture rtl of scu_top is
component xetherbone_core
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
......@@ -354,12 +338,10 @@ architecture rtl of scu_top is
signal s_hpla_ch: unsigned(15 downto 0);
signal ddr3_test_status: std_logic_vector(7 downto 0);
begin
-- open drain buffer for one wire
owr_i(0) <= OneWire_CB;
OneWire_CB <= owr_pwren_o(0) when (owr_pwren_o(0) = '1' or owr_en_o(0) = '1') else 'Z';
-- open drain buffer for SFP i2c
......@@ -371,28 +353,23 @@ begin
sfp2_mod2 <= '0' when sfp2_sda_o = '0' else 'Z';
Inst_flash_loader_v01 : flash_loader
port map (
noe_in => '0'
);
port map(
noe_in => '0');
reset : pow_reset
port map (
clk => pllout_clk_sys,
nreset => nreset
);
nreset => nreset);
dmtd_clk_pll_inst : dmtd_clk_pll port map (
inclk0 => clk_20m_vcxo_i, -- 20Mhz
c0 => pllout_clk_dmtd -- 62.5Mhz
);
c0 => pllout_clk_dmtd); -- 62.5Mhz
sys_pll_inst : sys_pll port map (
inclk0 => L_CLKp, -- 125Mhz
c0 => pllout_clk_sys, -- 62.5Mhy sys clk
c1 => clk_reconf, -- 50Mhz for reconfig block
locked => open
);
locked => open);
U_WR_CORE : xwr_core
generic map (
......@@ -453,7 +430,6 @@ begin
owr_pwren_o => owr_pwren_o,
owr_en_o => owr_en_o,
owr_i => owr_i,
slave_i => cbar_master_o(2),
slave_o => cbar_master_i(2),
......@@ -474,9 +450,7 @@ begin
dio_o => open,
rst_aux_n_o => open,
link_ok_o => open
);
link_ok_o => open);
wr_gxb_phy_arriaii_1 : wr_gxb_phy_arriaii
generic map (
......@@ -530,9 +504,8 @@ begin
pulse_i => pps,
extended_o => lemo_led(1));
lpc_slave: lpc_uart
port map (
port map(
lpc_clk => LPC_FPGA_CLK,
lpc_serirq => LPC_SERIRQ,
lpc_ad => LPC_AD,
......@@ -547,10 +520,8 @@ begin
serial_ri => '0',
serial_cts => '0',
serial_rts => open,
seven_seg_L => open,
seven_seg_H => open
);
seven_seg_H => open);
test_ram : xwb_dpram
generic map(
......@@ -568,8 +539,7 @@ begin
slave1_i => cbar_master_o(0),
slave1_o => cbar_master_i(0),
slave2_i => cc_dummy_slave_in,
slave2_o => open
);
slave2_o => open);
U_ebone : xetherbone_core
port map (
......@@ -614,7 +584,6 @@ begin
wb_slave_i => cbar_ref_master_o(2),
wb_slave_o => cbar_ref_master_i(2));
ECA : xwr_eca
port map(
clk_i => clk_125m_pllref_p,
......@@ -689,7 +658,7 @@ begin
master_o => cbar_master_o);
ddr3_stub: ddr3_mem_example_top
port map (
port map(
clock_source => L_CLKp,
global_reset_n => nreset,
......@@ -711,8 +680,7 @@ begin
pnf => open,
pnf_per_byte => open,
test_complete => lemo_led(2),
test_status => ddr3_test_status
);
test_status => ddr3_test_status);
la_counter: process (pllout_clk_sys, nreset)
begin
......@@ -723,7 +691,6 @@ begin
end if;
end process;
hpla_ch <= std_logic_vector(s_hpla_ch);
hpla_clk <= pllout_clk_sys;
......@@ -741,12 +708,8 @@ begin
A_nCONFIG <= '1';
nPWRBTN <= '1';
ADR_TO_SCUB <= '1';
nADR_EN <= '1';
nSel_Ext_Data_DRV <= '1';
end rtl;
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