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White Rabbit core collection
Commit a16ae961 authored by Maciej Lipinski's avatar Maciej Lipinski
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added g_clk_ref_rate to wr_streamers 

WR Streamers need to be used with WR Reference clock of 62.5MHz,
adding generic to specify what ref_clk is used (125MHz by default,
or 62.5MHz)
parent aa529987
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Showing with 40 additions and 8 deletions
modules/wr_streamers/streamers_pkg.vhd
View file @ a16ae961
......@@ -183,7 +183,8 @@ package streamers_pkg is
g_tx_timeout : integer := 1024;
g_escape_code_disable : boolean := FALSE;
g_simulation : integer := 0;
g_sim_startup_cnt : integer := 6250);--100us
g_sim_startup_cnt : integer := 6250;--100us
g_clk_ref_rate : integer := 125000000);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
......@@ -209,7 +210,8 @@ package streamers_pkg is
g_data_width : integer := 32;
g_buffer_size : integer := 256;
g_escape_code_disable : boolean := FALSE;
g_expected_words_number : integer := 0);
g_expected_words_number : integer := 0;
g_clk_ref_rate : integer := 125000000);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
......@@ -240,6 +242,7 @@ package streamers_pkg is
component xrtx_streamers_stats is
generic (
g_streamers_op_mode : t_streamers_op_mode := TX_AND_RX;
g_clk_ref_rate : integer := 125000000;
g_cnt_width : integer := 50;
g_acc_width : integer := 64
);
......@@ -281,6 +284,7 @@ package streamers_pkg is
component xwr_streamers is
generic (
g_streamers_op_mode : t_streamers_op_mode := TX_AND_RX;
g_clk_ref_rate : integer := 125000000;
--tx/rx
g_tx_streamer_params : t_tx_streamer_params := c_tx_streamer_params_defaut;
g_rx_streamer_params : t_rx_streamer_params := c_rx_streamer_params_defaut;
......
modules/wr_streamers/streamers_priv_pkg.vhd
View file @ a16ae961
......@@ -102,6 +102,8 @@ package streamers_priv_pkg is
-- component from wr-core/modules/timing
component pulse_stamper
generic (
g_ref_clk_rate : integer := 125000000);
port (
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
......
modules/wr_streamers/xrtx_streamers_stats.vhd
View file @ a16ae961
......@@ -68,7 +68,10 @@ entity xrtx_streamers_stats is
g_streamers_op_mode : t_streamers_op_mode := TX_AND_RX;
-- Width of frame counters
g_cnt_width : integer := 50; -- min:15, max:64, 50 bits should be ok for 50 years
g_acc_width : integer := 64 -- max value 64
g_acc_width : integer := 64; -- max value 64
-- rate fo the White Rabbit referene clock. By default, this clock is
-- 125MHz for WR Nodes. There are some WR Nodes that work with 62.5MHz.
g_clk_ref_rate : integer := 125000000
);
port (
clk_i : in std_logic;
......@@ -184,6 +187,8 @@ begin
-------------------------------------------------------------------------------------------
-- process that timestamps the reset so that we can make statistics over time
U_Reset_Timestamper : pulse_stamper
generic map(
g_ref_clk_rate => g_clk_ref_rate)
port map (
clk_ref_i => clk_ref_i,
clk_sys_i => clk_i,
......
modules/wr_streamers/xrx_streamer.vhd
View file @ a16ae961
......@@ -71,7 +71,12 @@ entity xrx_streamer is
-- other than zero, only a fixed number of words is accepted.
-- In combination with the g_escape_code_disable generic set to TRUE, the behaviour of
-- the "Btrain streamers" can be recreated.
g_expected_words_number : integer := 0
g_expected_words_number : integer := 0;
-- rate fo the White Rabbit referene clock. By default, this clock is
-- 125MHz for WR Nodes. There are some WR Nodes that work with 62.5MHz.
-- in the future, more frequences might be supported..
g_clk_ref_rate : integer := 125000000
);
port (
......@@ -275,6 +280,8 @@ begin -- rtl
rx_last_p1_o <= fifo_dout(g_data_width);
U_RX_Timestamper : pulse_stamper
generic map(
g_ref_clk_rate => g_clk_ref_rate)
port map (
clk_ref_i => clk_ref_i,
clk_sys_i => clk_sys_i,
......
modules/wr_streamers/xtx_streamer.vhd
View file @ a16ae961
......@@ -78,7 +78,12 @@ entity xtx_streamer is
-- the timer is overriden is set in the second generic
g_simulation : integer :=0;
-- startup counter, used only in simulatin mode (value in 16ns cycles)
g_sim_startup_cnt : integer := 6250-- 100us
g_sim_startup_cnt : integer := 6250;-- 100us;
-- rate fo the White Rabbit referene clock. By default, this clock is
-- 125MHz for WR Nodes. There are some WR Nodes that work with 62.5MHz.
-- in the future, more frequences might be supported..
g_clk_ref_rate : integer := 125000000
);
port (
......@@ -290,6 +295,8 @@ begin -- rtl
tx_fifo_last <= tx_fifo_q(g_data_width);
U_Timestamper : pulse_stamper
generic map(
g_ref_clk_rate => g_clk_ref_rate)
port map (
clk_ref_i => clk_ref_i,
clk_sys_i => clk_sys_i,
......
modules/wr_streamers/xwr_streamers.vhd
View file @ a16ae961
......@@ -71,6 +71,10 @@ entity xwr_streamers is
-- of them. An application that only receives or only transmits might want to use
-- RX_ONLY or TX_ONLY mode to save resources.
g_streamers_op_mode : t_streamers_op_mode := TX_AND_RX;
-- rate fo the White Rabbit referene clock. By default, this clock is
-- 125MHz for WR Nodes. There are some WR Nodes that work with 62.5MHz.
-- in the future, more frequences might be supported..
g_clk_ref_rate : integer := 125000000;
-----------------------------------------------------------------------------------------
-- Transmission/reception parameters
-----------------------------------------------------------------------------------------
......@@ -215,7 +219,8 @@ begin
g_tx_max_words_per_frame => g_tx_streamer_params.max_words_per_frame,
g_tx_timeout => g_tx_streamer_params.timeout,
g_escape_code_disable => g_tx_streamer_params.escape_code_disable,
g_simulation => g_simulation)
g_simulation => g_simulation,
g_clk_ref_rate => g_clk_ref_rate)
port map(
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
......@@ -251,7 +256,8 @@ begin
g_data_width => g_rx_streamer_params.data_width,
g_buffer_size => g_rx_streamer_params.buffer_size,
g_escape_code_disable => g_rx_streamer_params.escape_code_disable,
g_expected_words_number => g_rx_streamer_params.expected_words_number
g_expected_words_number => g_rx_streamer_params.expected_words_number,
g_clk_ref_rate => g_clk_ref_rate
)
port map(
clk_sys_i => clk_sys_i,
......@@ -290,7 +296,8 @@ begin
generic map(
g_streamers_op_mode => g_streamers_op_mode,
g_cnt_width => g_stats_cnt_width,
g_acc_width => g_stats_acc_width
g_acc_width => g_stats_acc_width,
g_clk_ref_rate => g_clk_ref_rate
)
port map(
clk_i => clk_sys_i,
......
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