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White Rabbit core collection
Commit a31dc9eb authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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add rx preamble shrinkage support

parent b6dfc740
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Showing with 250 additions and 79 deletions
modules/wr_endpoint/endpoint_pkg.vhd
View file @ a31dc9eb
......@@ -148,6 +148,14 @@ package endpoint_pkg is
rx : t_dbg_ep_rxpcs;
end record;
type t_dbg_rtu_extract is record
in_packet : std_logic;
in_header : std_logic;
rtu_rq_valid_basic : std_logic;
rtu_rq_valid_tagged : std_logic;
rtu_rq_abort : std_logic;
end record;
type t_dbg_ep_rxpath is record
fab_pipe : t_fab_pipe(9 downto 0);
dreq_pipe : std_logic_vector(9 downto 0);
......@@ -155,6 +163,7 @@ package endpoint_pkg is
pcs_fifo_empty : std_logic;
pcs_fifo_full : std_logic;
rxbuf_full : std_logic;
rtu_extract : t_dbg_rtu_extract;
end record;
type t_dbg_ep is record
......@@ -186,7 +195,8 @@ package endpoint_pkg is
g_with_packet_injection : boolean := false;
g_use_new_rxcrc : boolean := false;
g_use_new_txcrc : boolean := false;
g_with_stop_traffic : boolean := false);
g_with_stop_traffic : boolean := false;
g_ep_idx : integer := 0);
port (
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
......@@ -297,7 +307,8 @@ package endpoint_pkg is
g_with_packet_injection : boolean := false;
g_use_new_rxcrc : boolean := false;
g_use_new_txcrc : boolean := false;
g_with_stop_traffic : boolean := false);
g_with_stop_traffic : boolean := false;
g_ep_idx : integer := 0);
port (
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
......@@ -403,7 +414,8 @@ package endpoint_pkg is
stop_traffic_i : in std_logic := '0';
dbg_tx_pcs_wr_count_o : out std_logic_vector(5+4 downto 0);
dbg_tx_pcs_rd_count_o : out std_logic_vector(5+4 downto 0);
nice_dbg_o : out t_dbg_ep);
nice_dbg_o : out t_dbg_ep;
preamble_shrinkage : in std_logic := '0');
end component;
constant c_xwr_endpoint_sdb : t_sdb_device := (
......
modules/wr_endpoint/endpoint_private_pkg.vhd
View file @ a31dc9eb
......@@ -116,7 +116,8 @@ package endpoint_private_pkg is
component ep_1000basex_pcs
generic (
g_simulation : boolean;
g_16bit : boolean);
g_16bit : boolean;
g_ep_idx : integer);
port (
rst_sys_n_i : in std_logic;
rst_txclk_n_i : in std_logic;
......@@ -163,7 +164,8 @@ package endpoint_private_pkg is
mdio_ready_o : out std_logic;
dbg_tx_pcs_wr_count_o : out std_logic_vector(5+4 downto 0);
dbg_tx_pcs_rd_count_o : out std_logic_vector(5+4 downto 0);
nice_dbg_o : out t_dbg_ep_pcs);
nice_dbg_o : out t_dbg_ep_pcs;
preamble_shrinkage : in std_logic);
end component;
component ep_tx_pcs_8bit
......@@ -186,7 +188,8 @@ package endpoint_private_pkg is
phy_tx_data_o : out std_logic_vector(7 downto 0);
phy_tx_k_o : out std_logic;
phy_tx_disparity_i : in std_logic;
phy_tx_enc_err_i : in std_logic);
phy_tx_enc_err_i : in std_logic;
preamble_shrinkage : in std_logic := '0');
end component;
component ep_tx_pcs_16bit
......@@ -250,7 +253,8 @@ package endpoint_private_pkg is
component ep_rx_pcs_16bit
generic (
g_simulation : boolean);
g_simulation : boolean;
g_ep_idx : integer);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
......@@ -517,7 +521,8 @@ package endpoint_private_pkg is
rtu_full_i : in std_logic;
rtu_rq_abort_o : out std_logic;
rtu_rq_valid_o : out std_logic;
rxbuf_full_i : in std_logic);
rxbuf_full_i : in std_logic;
nice_dbg_o : out t_dbg_rtu_extract);
end component;
component ep_rx_early_address_match
......@@ -620,6 +625,7 @@ package endpoint_private_pkg is
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
stop_traffic_i : in std_logic := '0';
snk_fab_i : in t_ep_internal_fabric;
snk_dreq_o : out std_logic;
src_wb_i : in t_wrf_source_in;
......@@ -675,6 +681,7 @@ package endpoint_private_pkg is
clk_rx_i : in std_logic;
rst_n_sys_i : in std_logic;
rst_n_rx_i : in std_logic;
stop_traffic_i : in std_logic;
pcs_fab_i : in t_ep_internal_fabric;
pcs_fifo_almostfull_o : out std_logic;
pcs_busy_i : in std_logic;
......
modules/wr_endpoint/ep_1000basex_pcs.vhd
View file @ a31dc9eb
......@@ -63,7 +63,8 @@ entity ep_1000basex_pcs is
g_simulation : boolean;
-- PCS datapath width selection: true = 16-bit (Virtex-6), false = 8-bit
-- (Spartan-6 or TBI).
g_16bit : boolean);
g_16bit : boolean;
g_ep_idx : integer);
port (
......@@ -195,7 +196,8 @@ entity ep_1000basex_pcs is
dbg_tx_pcs_wr_count_o : out std_logic_vector(5+4 downto 0);
dbg_tx_pcs_rd_count_o : out std_logic_vector(5+4 downto 0);
nice_dbg_o : out t_dbg_ep_pcs);
nice_dbg_o : out t_dbg_ep_pcs;
preamble_shrinkage : in std_logic);
end ep_1000basex_pcs;
......@@ -295,7 +297,8 @@ begin -- rtl
U_RX_PCS : ep_rx_pcs_16bit
generic map (
g_simulation => g_simulation)
g_simulation => g_simulation,
g_ep_idx => g_ep_idx)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => pcs_reset_n,
......@@ -366,7 +369,8 @@ begin -- rtl
phy_tx_data_o => serdes_tx_data_o(7 downto 0),
phy_tx_k_o => serdes_tx_k_o(0),
phy_tx_disparity_i => serdes_tx_disparity_i,
phy_tx_enc_err_i => serdes_tx_enc_err_i
phy_tx_enc_err_i => serdes_tx_enc_err_i,
preamble_shrinkage => preamble_shrinkage
);
U_RX_PCS : ep_rx_pcs_8bit
......
modules/wr_endpoint/ep_rtu_header_extract.vhd
View file @ a31dc9eb
......@@ -61,7 +61,8 @@ entity ep_rtu_header_extract is
rtu_full_i : in std_logic;
rtu_rq_abort_o : out std_logic;
rtu_rq_valid_o : out std_logic;
rxbuf_full_i : in std_logic
rxbuf_full_i : in std_logic;
nice_dbg_o : out t_dbg_rtu_extract
);
end ep_rtu_header_extract;
......@@ -201,5 +202,11 @@ begin -- rtl
rtu_rq_o.has_prio <= vlan_is_tagged_i;
rtu_rq_valid_o <= rtu_rq_valid_out and not snk_fab_i.ERROR;
rtu_rq_o.hash <= (others => '0');
nice_dbg_o.in_packet <= in_packet;
nice_dbg_o.in_header <= in_header;
nice_dbg_o.rtu_rq_valid_basic <= rtu_rq_valid_basic;
nice_dbg_o.rtu_rq_valid_tagged <= rtu_rq_valid_tagged;
nice_dbg_o.rtu_rq_abort <= rtu_rq_abort;
end rtl;
modules/wr_endpoint/ep_rx_path.vhd
View file @ a31dc9eb
......@@ -75,6 +75,8 @@ entity ep_rx_path is
rst_n_sys_i : in std_logic;
rst_n_rx_i : in std_logic;
stop_traffic_i : in std_logic;
-- physical coding sublayer (PCS) interface
pcs_fab_i : in t_ep_internal_fabric;
pcs_fifo_almostfull_o : out std_logic;
......@@ -394,7 +396,8 @@ begin -- behavioral
rtu_full_i => rtu_full_i,
rtu_rq_abort_o => rtu_rq_abort_o,
rtu_rq_valid_o => rtu_rq_valid,
rxbuf_full_i => rxbuf_full);
rxbuf_full_i => rxbuf_full,
nice_dbg_o => nice_dbg_o.rtu_extract);
gen_with_rx_buffer : if g_with_rx_buffer generate
U_Rx_Buffer : ep_rx_buffer
......@@ -445,6 +448,7 @@ begin -- behavioral
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_sys_i,
stop_traffic_i => stop_traffic_i,
snk_fab_i => fab_pipe(9),
snk_dreq_o => dreq_pipe(9),
src_wb_i => src_wb_i,
......
modules/wr_endpoint/ep_rx_pcs_16bit.vhd
View file @ a31dc9eb
......@@ -52,7 +52,8 @@ use work.endpoint_pkg.all;
entity ep_rx_pcs_16bit is
generic (
g_simulation : boolean);
g_simulation : boolean;
g_ep_idx : integer);
port (
-- 62.5 MHz refclk divided by 2
clk_sys_i : in std_logic;
......@@ -170,12 +171,23 @@ architecture behavioral of ep_rx_pcs_16bit is
-- 8b10b decoding and postprocessing signals
signal d_data : std_logic_vector(15 downto 0);
signal d_data_shrunk : std_logic_vector(15 downto 0);
signal d_data_buf : std_logic_vector(7 downto 0);
signal d_err, d_is_idle, d_is_spd_preamble : std_logic;
signal d_is_eof_extend, d_is_eof, d_is_extend : std_logic;
signal d_is_preamble, d_is_preamble_sfd : std_logic;
signal d_is_k : std_logic_vector(1 downto 0);
signal d_is_k_buf : std_logic;
signal d_is_k_shrunk : std_logic_vector(1 downto 0);
signal d_is_lcr : std_logic;
signal d_is_cal : std_logic;
signal phy_rx_data_shrunk : std_logic_vector(15 downto 0);
signal phy_rx_data_muxed : std_logic_vector(15 downto 0);
signal phy_rx_k_shrunk : std_logic_vector(1 downto 0);
signal phy_rx_k_muxed : std_logic_vector(1 downto 0);
signal d_is_shrunk : std_logic;
signal shrunk_preamble : std_logic;
-- Synchronization detection FSM signals
signal rx_synced : std_logic;
......@@ -208,6 +220,27 @@ architecture behavioral of ep_rx_pcs_16bit is
signal pcs_valid_int : std_logic;
signal timestamp_pending : std_logic_vector(2 downto 0) := "000";
------------------------
component chipscope_icon
port (
CONTROL0 : inout std_logic_vector(35 downto 0));
end component;
component chipscope_ila
port (
CONTROL : inout std_logic_vector(35 downto 0);
CLK : in std_logic;
TRIG0 : in std_logic_vector(31 downto 0);
TRIG1 : in std_logic_vector(31 downto 0);
TRIG2 : in std_logic_vector(31 downto 0);
TRIG3 : in std_logic_vector(31 downto 0));
end component;
signal control0 : std_logic_vector(35 downto 0);
signal trig0, trig1, trig2, trig3 : std_logic_vector(31 downto 0);
signal pcs_fab_out : t_ep_internal_fabric;
begin
-------------------------------------------------------------------------------
......@@ -335,6 +368,11 @@ begin
-- Clock adjustment FIFO
-------------------------------------------------------------------------------
phy_rx_data_shrunk <= d_data(7 downto 0) & phy_rx_data_i(15 downto 8);
phy_rx_data_muxed <= phy_rx_data_i when shrunk_preamble = '0' else
phy_rx_data_shrunk;
phy_rx_k_muxed <= phy_rx_k_i when shrunk_preamble = '0' else
d_is_k(0) & phy_rx_k_i(1);
-- process postprocesses the raw 8b10b decoder output (phy_rx_data_i, phy_rx_k_i, phy_rx_enc_err_ior)
-- providing 1-bit signals indicating various 8b10b control patterns
......@@ -354,10 +392,18 @@ begin
d_is_eof_extend <= '0';
d_is_lcr <= '0';
d_err <= '0';
d_data_buf <= (others=>'0');
d_data_shrunk <= (others=>'0');
d_is_shrunk <= '0';
else
d_data <= phy_rx_data_i;
d_is_k <= phy_rx_k_i;
d_data_shrunk <= d_data_buf & phy_rx_data_i(15 downto 8); --
d_data_buf <= phy_rx_data_i(7 downto 0);
d_is_k_shrunk <= d_is_k_buf & phy_rx_k_i(1);
d_is_k_buf <= phy_rx_k_i(0);
if(phy_rx_enc_err_i = '0') then
d_err <= '0';
......@@ -382,19 +428,25 @@ begin
phy_rx_data_i = c_preamble_char & c_preamble_sfd
and phy_rx_k_i = "00");
d_is_shrunk <= f_to_sl(
phy_rx_data_shrunk = c_preamble_char & c_preamble_sfd
and phy_rx_k_muxed = "00");
-- data + EPD
d_is_eof <= f_to_sl(
phy_rx_data_i(7 downto 0) = c_K29_7
and phy_rx_k_i = "01");
if (shrunk_preamble = '0') then
d_is_eof <= f_to_sl( phy_rx_data_i(7 downto 0) = c_K29_7 and phy_rx_k_i = "01");
else
d_is_eof <= f_to_sl( phy_rx_data_i(15 downto 8) = c_K29_7 and phy_rx_k_i(1) = '1');
end if;
-- EPD + extend
d_is_eof_extend <= f_to_sl(
phy_rx_data_i(15 downto 8) = c_K29_7
and phy_rx_data_i(7 downto 0) = c_k23_7
phy_rx_data_muxed(15 downto 8) = c_K29_7
and phy_rx_data_muxed(7 downto 0) = c_k23_7
and phy_rx_k_i = "11");
d_is_extend <= f_to_sl(
phy_rx_data_i = c_K23_7 & c_K23_7
phy_rx_data_muxed = c_K23_7 & c_K23_7
and phy_rx_k_i = "11");
d_is_lcr <= f_to_sl(
......@@ -434,13 +486,13 @@ begin
rx_state <= RX_NOFRAME;
rx_busy <= '0';
pcs_fab_o.sof <= '0';
pcs_fab_o.eof <= '0';
pcs_fab_o.error <= '0';
pcs_fab_o.dvalid <= '0';
pcs_fab_o.bytesel <= '0';
pcs_fab_o.has_rx_timestamp <= '0';
pcs_fab_o.data <= (others => 'X');
pcs_fab_out.sof <= '0';
pcs_fab_out.eof <= '0';
pcs_fab_out.error <= '0';
pcs_fab_out.dvalid <= '0';
pcs_fab_out.bytesel <= '0';
pcs_fab_out.has_rx_timestamp <= '0';
pcs_fab_out.data <= (others => 'X');
lcr_ready <= '0';
lcr_cur_val <= (others => '0');
......@@ -454,6 +506,7 @@ begin
rmon_invalid_code_p_int <= '0';
timestamp_trigger_p_a_o <= '0';
timestamp_pending <= "000";
shrunk_preamble <= '0';
else -- normal PCS operation
-- clear the autogotiation variables if the autonegotiation is disabled
......@@ -476,30 +529,32 @@ begin
when RX_NOFRAME =>
preamble_cntr <= "011";
pcs_fab_o.eof <= '0';
pcs_fab_o.error <= '0';
pcs_fab_o.bytesel <= '0';
pcs_fab_o.has_rx_timestamp <= '0';
pcs_fab_out.eof <= '0';
pcs_fab_out.error <= '0';
pcs_fab_out.bytesel <= '0';
pcs_fab_out.has_rx_timestamp <= '0';
rx_busy <= '0';
timestamp_trigger_p_a_o <= '0';
shrunk_preamble <= '0';
-- insert the RX timestamp into the FIFO
if(timestamp_pending /= "000") then
pcs_fab_o.dvalid <= '1';
pcs_fab_out.dvalid <= '1';
else
pcs_fab_o.dvalid <= '0';
pcs_fab_out.dvalid <= '0';
end if;
if(timestamp_pending(0) = '1')then
pcs_fab_o.data <= timestamp_i(31 downto 16);
pcs_fab_o.eof <= '0';
pcs_fab_out.data <= timestamp_i(31 downto 16);
pcs_fab_out.eof <= '0';
elsif(timestamp_pending(1) = '1')then
pcs_fab_o.data <= timestamp_i(15 downto 0);
pcs_fab_o.eof <= '0';
pcs_fab_out.data <= timestamp_i(15 downto 0);
pcs_fab_out.eof <= '0';
elsif(timestamp_pending(2) = '1')then
pcs_fab_o.data <= (others => 'X');
pcs_fab_o.eof <= '1';
pcs_fab_out.data <= (others => 'X');
pcs_fab_out.eof <= '1';
end if;
timestamp_pending <= timestamp_pending(1 downto 0) & '0';
......@@ -550,7 +605,8 @@ begin
-- values are identical.
-- an error? - abort the reception and go to NOFRAME state.
if(d_err = '1' or d_is_k /= "00" or rx_synced = '0') then
if(d_err = '1' or (d_is_k /= "00" and shrunk_preamble = '0') or
(d_is_k_shrunk /= "00" and shrunk_preamble = '1') or rx_synced = '0') then
rx_state <= RX_NOFRAME;
rmon_invalid_code_p_int <= d_err;
......@@ -598,7 +654,7 @@ begin
-- keep looking for Ethernet SFD char (0xd5). If it occurs on
-- the right position, start receiving the frame payload
if d_is_preamble_sfd = '1' then
if d_is_preamble_sfd = '1' or d_is_shrunk = '1' then
-- generate the RX timestamp pulse
timestamp_trigger_p_a_o <= '1';
......@@ -607,7 +663,8 @@ begin
-- indicate a start-of-packet condition in the RX FIFO and enable writing to
-- the FIFO.
pcs_fab_o.sof <= '1';
shrunk_preamble <= d_is_shrunk; -- remember if we're processing normal frame, or there was a shrunk preamble
pcs_fab_out.sof <= '1';
rx_state <= RX_PAYLOAD;
end if;
......@@ -633,20 +690,25 @@ begin
when RX_PAYLOAD =>
pcs_fab_o.sof <= '0';
pcs_fab_o.eof <= '0';
pcs_fab_o.has_rx_timestamp <= '0';
pcs_fab_o.data <= d_data;
pcs_fab_out.sof <= '0';
pcs_fab_out.eof <= '0';
pcs_fab_out.has_rx_timestamp <= '0';
if (shrunk_preamble = '1') then
pcs_fab_out.data <= d_data_shrunk;
else
pcs_fab_out.data <= d_data;
end if;
-- check for errors.
if (d_err = '1' or rx_synced = '0' or pcs_fifo_almostfull_i = '1'
or (d_is_k /= "00" and d_is_eof_extend = '0' and d_is_eof = '0')) then
or (d_is_k /= "00" and d_is_eof_extend = '0' and d_is_eof = '0' and shrunk_preamble = '0')
or (d_is_k_shrunk /= "00" and d_is_eof_extend = '0' and d_is_eof = '0' and shrunk_preamble = '1') ) then
-- indicate an errorneous termination of the current frame in the
-- RX FIFO
pcs_fab_o.error <= '1';
pcs_fab_o.dvalid <= '0';
pcs_fab_o.bytesel <= 'X';
pcs_fab_out.error <= '1';
pcs_fab_out.dvalid <= '0';
pcs_fab_out.bytesel <= 'X';
rmon_invalid_code_p_int <= d_err;
rmon_rx_overrun_p_int <= pcs_fifo_almostfull_i;
......@@ -654,22 +716,22 @@ begin
rx_state <= RX_NOFRAME;
elsif d_is_eof = '1' or d_is_eof_extend = '1' then
pcs_fab_o.error <= '0';
pcs_fab_out.error <= '0';
if d_is_eof = '1' then -- got EPD at even position
pcs_fab_o.bytesel <= '1';
pcs_fab_o.dvalid <= '1';
pcs_fab_out.bytesel <= '1';
pcs_fab_out.dvalid <= '1';
rx_state <= RX_EXTEND;
else
pcs_fab_o.bytesel <= '0';
pcs_fab_o.dvalid <= '0';
pcs_fab_out.bytesel <= '0';
pcs_fab_out.dvalid <= '0';
rx_state <= RX_EXTEND;
end if;
else
pcs_fab_o.bytesel <= '0';
pcs_fab_o.error <= '0';
pcs_fab_o.dvalid <= '1';
pcs_fab_out.bytesel <= '0';
pcs_fab_out.error <= '0';
pcs_fab_out.dvalid <= '1';
end if;
......@@ -680,24 +742,24 @@ begin
when RX_EXTEND =>
timestamp_trigger_p_a_o <= '0';
pcs_fab_o.dvalid <= '0';
pcs_fab_out.dvalid <= '0';
if d_is_extend = '1' then -- got carrier extend. Just keep
-- receiving it.
rx_state <= RX_EXTEND;
pcs_fab_o.eof <= '0';
pcs_fab_o.error <= '0';
pcs_fab_out.eof <= '0';
pcs_fab_out.error <= '0';
elsif d_is_idle = '1' then -- got comma, real end-of-frame
-- indicate the correct ending of the current frame in the RX FIFO
pcs_fab_o.eof <= not timestamp_stb_i;
pcs_fab_o.error <= '0';
pcs_fab_o.has_rx_timestamp <= timestamp_stb_i;
pcs_fab_out.eof <= not timestamp_stb_i;
pcs_fab_out.error <= '0';
pcs_fab_out.has_rx_timestamp <= timestamp_stb_i;
timestamp_pending <= (others => timestamp_stb_i);
rx_state <= RX_NOFRAME;
else
-- got anything else than comma (for example, the /V/ code):
pcs_fab_o.error <= '1';
pcs_fab_out.error <= '1';
rmon_invalid_code_p_int <= '1';
rx_state <= RX_NOFRAME;
end if;
......@@ -751,7 +813,7 @@ begin
-- drive the "RX PCS Sync Lost" event counter
rmon_rx_sync_lost <= rx_sync_lost_p and (not mdio_mcr_pdown_i);
pcs_fab_o.rx_timestamp_valid <= timestamp_valid_i;
pcs_fab_out.rx_timestamp_valid <= timestamp_valid_i;
nice_dbg_o.fsm <= "000" when (rx_state = RX_NOFRAME) else
"001" when (rx_state = RX_CR) else
......@@ -760,6 +822,55 @@ begin
"100" when (rx_state = RX_EXTEND) else
"111";
------------------------
pcs_fab_o <= pcs_fab_out;
GEN_CS: if g_ep_idx = 0 generate
CS_ICON : chipscope_icon
port map (
CONTROL0 => CONTROL0);
CS_ILA : chipscope_ila
port map (
CONTROL => CONTROL0,
CLK => phy_rx_clk_i, --phys_i(0).rx_clk,
TRIG0 => trig0,
TRIG1 => trig1,
TRIG2 => trig2,
TRIG3 => trig3);
end generate;
trig0(15 downto 0) <= phy_rx_data_i;
trig0(17 downto 16)<= phy_rx_k_i;
trig0(18) <= d_is_preamble;
trig0(19) <= d_is_preamble_sfd;
trig0(22 downto 20) <= "000" when (rx_state = RX_NOFRAME) else
"001" when (rx_state = RX_CR) else
"010" when (rx_state = RX_SPD_PREAMBLE) else
"011" when (rx_state = RX_PAYLOAD) else
"100" when (rx_state = RX_EXTEND) else
"111";
trig0(23) <= rx_busy;
trig0(24) <= rx_synced;
trig0(25) <= d_is_spd_preamble;
trig0(26) <= d_is_idle;
trig0(27) <= d_is_eof;
trig0(28) <= d_is_shrunk;
trig0(29) <= phy_rdy_i;
trig1(15 downto 0) <= pcs_fab_out.data;
trig1(16) <= pcs_fab_out.sof;
trig1(17) <= pcs_fab_out.eof;
trig1(18) <= pcs_fab_out.dvalid;
trig1(19) <= pcs_fab_out.error;
trig1(20) <= pcs_fab_out.bytesel;
trig1(28 downto 21) <= d_data_buf;
trig1(31 downto 29) <= std_logic_vector(preamble_cntr);
trig2(15 downto 0) <= d_data_shrunk;
------------------------
trig2(31 downto 16) <= phy_rx_data_muxed;
end behavioral;
modules/wr_endpoint/ep_rx_wb_master.vhd
View file @ a31dc9eb
......@@ -56,6 +56,7 @@ entity ep_rx_wb_master is
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
stop_traffic_i : in std_logic := '0';
-- physical coding sublayer (PCS) interface
snk_fab_i : in t_ep_internal_fabric;
snk_dreq_o : out std_logic;
......@@ -157,7 +158,7 @@ begin -- behavioral
state <= FLUSH_STALL;
end if;
if(snk_fab_i.eof = '1')then
if(snk_fab_i.eof = '1' or stop_traffic_i = '1')then
state <= FINISH_CYCLE;
end if;
......
modules/wr_endpoint/ep_tx_pcs_8bit.vhd
View file @ a31dc9eb
......@@ -119,7 +119,9 @@ entity ep_tx_pcs_8bit is
phy_tx_data_o : out std_logic_vector(7 downto 0);
phy_tx_k_o : out std_logic;
phy_tx_disparity_i : in std_logic;
phy_tx_enc_err_i : in std_logic
phy_tx_enc_err_i : in std_logic;
preamble_shrinkage : in std_logic := '0'
);
end ep_tx_pcs_8bit;
......@@ -162,6 +164,9 @@ architecture behavioral of ep_tx_pcs_8bit is
signal mdio_mcr_pdown_synced : std_logic;
signal an_tx_en_synced : std_logic;
signal s_one : std_logic := '1';
signal sh_preamble_sent : std_logic;
begin
U_sync_pcs_busy_o : gc_sync_ffs
......@@ -280,7 +285,7 @@ begin
tx_odd_length <= '0';
tx_rdreq_toggle <= '0';
rmon_tx_underrun <= '0';
sh_preamble_sent <= '0';
else
case tx_state is
......@@ -294,6 +299,7 @@ begin
tx_state <= TX_IDLE;
fifo_rd <= '0';
fifo_ready <= fifo_rd;
sh_preamble_sent <= '0';
-------------------------------------------------------------------------------
-- State IDLE: sends the second code of the /I/ sequence with proper disparity\
......@@ -304,6 +310,7 @@ begin
-- make sure is't long enough to trigger the event counter
rmon_tx_underrun <= '0';
tx_error <= '0';
sh_preamble_sent <= '0';
-- endpoint wants to send Config_Reg
if(an_tx_en_synced = '1') then
......@@ -315,7 +322,12 @@ begin
elsif (fifo_fab.sof = '1' and fifo_ready = '1' and tx_cntr = "0000")then
fifo_rd <= '1';
tx_state <= TX_SPD;
tx_cntr <= "0101";
if (preamble_shrinkage = '0') then -- generate preamble shrinkage
tx_cntr <= "0101";
else
sh_preamble_sent <= '1';
tx_cntr <= "0100";
end if;
-- host requested a calibration pattern
elsif(mdio_wr_spec_tx_cal_i = '1') then
......@@ -453,8 +465,13 @@ begin
tx_rdreq_toggle <= not tx_rdreq_toggle;
-- handle the end of frame both for even- and odd-length frames
tx_odd_length <= fifo_fab.bytesel;
-- handle the end of frame both for even- and odd-length frames,
-- including preamble shrinkage
if (sh_preamble_sent = '0') then
tx_odd_length <= fifo_fab.bytesel;
else
tx_odd_length <= not fifo_fab.bytesel;
end if;
if (fifo_fab.eof = '1' and (tx_rdreq_toggle = '0' or (tx_rdreq_toggle = '1' and fifo_fab.bytesel = '1'))) then
tx_state <= TX_EPD;
......
modules/wr_endpoint/wr_endpoint.vhd
View file @ a31dc9eb
......@@ -74,7 +74,8 @@ entity wr_endpoint is
g_with_packet_injection : boolean := false;
g_use_new_rxcrc : boolean := false;
g_use_new_txcrc : boolean := false;
g_with_stop_traffic : boolean := false
g_with_stop_traffic : boolean := false;
g_ep_idx : integer := 0
);
port (
......@@ -303,7 +304,8 @@ entity wr_endpoint is
dbg_tx_pcs_wr_count_o : out std_logic_vector(5+4 downto 0);
dbg_tx_pcs_rd_count_o : out std_logic_vector(5+4 downto 0);
nice_dbg_o : out t_dbg_ep
nice_dbg_o : out t_dbg_ep;
preamble_shrinkage : in std_logic
);
end wr_endpoint;
......@@ -488,7 +490,8 @@ begin
U_PCS_1000BASEX : ep_1000basex_pcs
generic map (
g_simulation => g_simulation,
g_16bit => g_pcs_16bit)
g_16bit => g_pcs_16bit,
g_ep_idx => g_ep_idx)
port map (
rst_sys_n_i => rst_sys_n_i,
rst_rxclk_n_i => rst_rxclk_n_i,
......@@ -544,7 +547,8 @@ begin
mdio_ready_o => regs_towb_ep.mdio_asr_ready_i,
dbg_tx_pcs_wr_count_o => dbg_tx_pcs_wr_count_o,
dbg_tx_pcs_rd_count_o => dbg_tx_pcs_rd_count_o,
nice_dbg_o => nice_dbg_o.pcs);
nice_dbg_o => nice_dbg_o.pcs,
preamble_shrinkage => preamble_shrinkage);
-------------------------------------------------------------------------------
......@@ -629,6 +633,8 @@ begin
rst_n_sys_i => rst_n_rx_resync_sys,
rst_n_rx_i => rst_n_rx,
stop_traffic_i => stop_traffic_i,
pcs_fab_i => rxpath_fab,
pcs_fifo_almostfull_o => rxpcs_fifo_almostfull,
pcs_busy_i => rxpcs_busy,
......
modules/wr_endpoint/xwr_endpoint.vhd
View file @ a31dc9eb
......@@ -65,7 +65,8 @@ entity xwr_endpoint is
g_with_packet_injection : boolean := false;
g_use_new_rxcrc : boolean := false;
g_use_new_txcrc : boolean := false;
g_with_stop_traffic : boolean := false
g_with_stop_traffic : boolean := false;
g_ep_idx : integer
);
port (
......@@ -319,7 +320,8 @@ begin
g_with_packet_injection => g_with_packet_injection,
g_use_new_rxcrc => g_use_new_rxcrc,
g_use_new_txcrc => g_use_new_txcrc,
g_with_stop_traffic => g_with_stop_traffic)
g_with_stop_traffic => g_with_stop_traffic,
g_ep_idx => g_ep_idx)
port map (
clk_ref_i => clk_ref_i,
clk_sys_i => clk_sys_i,
......
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