CLBv3: cleaned up clk_20m_vcxo

a4db868b · Peter Jansweijer · Grzegorz Daniluk · 622c948b · a4db868b · a4db868b
Commit a4db868b authored Dec 01, 2017 by Peter Jansweijer Committed by Grzegorz Daniluk Dec 13, 2017
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wrc_board_clbv3.vhd board/clbv3/wrc_board_clbv3.vhd +0 -1

xwrc_board_clbv3.vhd board/clbv3/xwrc_board_clbv3.vhd +0 -1

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--- a/board/clbv3/wrc_board_clbv3.vhd
+++ b/board/clbv3/wrc_board_clbv3.vhd
@@ -87,7 +87,6 @@ entity wrc_board_clbv3 is
    -- reset PLLs.
    areset_edge_n_i     : in  std_logic := '1';
    -- Clock inputs from the board
--    clk_20m_vcxo_i      : in  std_logic;
    clk_125m_dmtd_p_i : in  std_logic;
    clk_125m_dmtd_n_i : in  std_logic;
    clk_125m_gtp_n_i    : in  std_logic;

--- a/board/clbv3/xwrc_board_clbv3.vhd
+++ b/board/clbv3/xwrc_board_clbv3.vhd
@@ -88,7 +88,6 @@ entity xwrc_board_clbv3 is
    -- reset PLLs.
    areset_edge_n_i     : in  std_logic := '1';
    -- Clock inputs from the board
--    clk_20m_vcxo_i      : in  std_logic;
    clk_125m_dmtd_n_i   : in  std_logic;  -- 124.992 MHz
    clk_125m_dmtd_p_i   : in  std_logic;
    clk_125m_gtp_n_i    : in  std_logic;