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White Rabbit core collection
Commit a595a117 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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adding edge-sensitive reset to boards to allow standalone operation

parent 717d0f1e
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Showing with 86 additions and 34 deletions
board/spec/wr_spec_pkg.vhd
View file @ a595a117
......@@ -27,6 +27,7 @@ package wr_spec_pkg is
g_diag_rw_size : integer := 0);
port (
areset_n_i : in std_logic;
areset_edge_n_i : in std_logic := '1';
clk_20m_vcxo_i : in std_logic;
clk_125m_pllref_p_i : in std_logic;
clk_125m_pllref_n_i : in std_logic;
......@@ -118,7 +119,7 @@ package wr_spec_pkg is
g_simulation : integer := 0;
g_with_external_clock_input : integer := 1;
g_aux_clks : integer := 0;
g_fabric_iface : string := "plainfbrc";
g_fabric_iface : string := "PLAINFBRC";
g_streamers_op_mode : t_streamers_op_mode := TX_AND_RX;
g_tx_streamer_params : t_tx_streamer_params := c_tx_streamer_params_defaut;
g_rx_streamer_params : t_rx_streamer_params := c_rx_streamer_params_defaut;
......@@ -129,6 +130,7 @@ package wr_spec_pkg is
g_diag_rw_vector_width : integer := 0);
port (
areset_n_i : in std_logic;
areset_edge_n_i : in std_logic := '1';
clk_20m_vcxo_i : in std_logic;
clk_125m_pllref_p_i : in std_logic;
clk_125m_pllref_n_i : in std_logic;
......
board/spec/wrc_board_spec.vhd
View file @ a595a117
......@@ -84,6 +84,9 @@ entity wrc_board_spec is
---------------------------------------------------------------------------
-- Reset from system fpga
areset_n_i : in std_logic;
-- Optional reset input active low with rising edge detection. Does not
-- reset PLLs.
areset_edge_n_i : in std_logic := '1';
-- Clock inputs from the board
clk_20m_vcxo_i : in std_logic;
clk_125m_pllref_p_i : in std_logic;
......@@ -413,6 +416,7 @@ begin -- architecture struct
g_diag_rw_size => c_diag_rw_size)
port map (
areset_n_i => areset_n_i,
areset_edge_n_i => areset_edge_n_i,
clk_20m_vcxo_i => clk_20m_vcxo_i,
clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
......
board/spec/xwrc_board_spec.vhd
View file @ a595a117
......@@ -85,6 +85,9 @@ entity xwrc_board_spec is
---------------------------------------------------------------------------
-- Reset input (active low, can be async)
areset_n_i : in std_logic;
-- Optional reset input active low with rising edge detection. Does not
-- reset PLLs.
areset_edge_n_i : in std_logic := '1';
-- Clock inputs from the board
clk_20m_vcxo_i : in std_logic;
clk_125m_pllref_p_i : in std_logic;
......@@ -262,10 +265,11 @@ architecture struct of xwrc_board_spec is
signal clk_10m_ext : std_logic;
-- Reset logic
signal rst_62m5_n : std_logic;
signal rstlogic_arst_n : std_logic;
signal rstlogic_clk_in : std_logic_vector(1 downto 0);
signal rstlogic_rst_out : std_logic_vector(1 downto 0);
signal areset_edge_ppulse : std_logic;
signal rst_62m5_n : std_logic;
signal rstlogic_arst_n : std_logic;
signal rstlogic_clk_in : std_logic_vector(1 downto 0);
signal rstlogic_rst_out : std_logic_vector(1 downto 0);
-- PLL DAC ARB
signal dac_hpll_load_p1 : std_logic;
......@@ -341,9 +345,21 @@ begin -- architecture struct
-----------------------------------------------------------------------------
-- Reset logic
-----------------------------------------------------------------------------
-- Detect when areset_edge_n_i goes high (end of reset) and use this edge to
-- generate rstlogic_arst_n. This is needed to connect optional reset like PCIe
-- reset. When baord runs standalone, we need to ignore PCIe reset being
-- constantly low.
cmp_arst_edge: gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => clk_pll_62m5,
rst_n_i => '1',
data_i => areset_edge_n_i,
ppulse_o => areset_edge_ppulse);
-- logic AND of all async reset sources (active low)
rstlogic_arst_n <= pll_locked and areset_n_i;
rstlogic_arst_n <= pll_locked and areset_n_i and (not areset_edge_ppulse);
-- concatenation of all clocks required to have synced resets
rstlogic_clk_in(0) <= clk_pll_62m5;
......
board/svec/wr_svec_pkg.vhd
View file @ a595a117
......@@ -27,6 +27,7 @@ package wr_svec_pkg is
g_diag_rw_size : integer := 0);
port (
areset_n_i : in std_logic;
areset_edge_n_i : in std_logic := '1';
clk_20m_vcxo_i : in std_logic;
clk_125m_pllref_p_i : in std_logic;
clk_125m_pllref_n_i : in std_logic;
......@@ -130,6 +131,7 @@ package wr_svec_pkg is
g_diag_rw_vector_width : integer := 0);
port (
areset_n_i : in std_logic;
areset_edge_n_i : in std_logic := '1';
clk_20m_vcxo_i : in std_logic;
clk_125m_pllref_p_i : in std_logic;
clk_125m_pllref_n_i : in std_logic;
......
board/svec/wrc_board_svec.vhd
View file @ a595a117
......@@ -84,6 +84,9 @@ entity wrc_board_svec is
---------------------------------------------------------------------------
-- Reset from system fpga
areset_n_i : in std_logic;
-- Optional reset input active low with rising edge detection. Does not
-- reset PLLs.
areset_edge_n_i : in std_logic := '1';
-- Clock inputs from the board
clk_20m_vcxo_i : in std_logic;
clk_125m_pllref_p_i : in std_logic;
......@@ -415,6 +418,7 @@ begin -- architecture struct
g_diag_rw_size => c_diag_rw_size)
port map (
areset_n_i => areset_n_i,
areset_edge_n_i => areset_edge_n_i,
clk_20m_vcxo_i => clk_20m_vcxo_i,
clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
......
board/svec/xwrc_board_svec.vhd
View file @ a595a117
......@@ -85,6 +85,9 @@ entity xwrc_board_svec is
---------------------------------------------------------------------------
-- Reset input (active low, can be async)
areset_n_i : in std_logic;
-- Optional reset input active low with rising edge detection. Does not
-- reset PLLs.
areset_edge_n_i : in std_logic := '1';
-- Clock inputs from the board
clk_20m_vcxo_i : in std_logic;
clk_125m_pllref_p_i : in std_logic;
......@@ -265,10 +268,11 @@ architecture struct of xwrc_board_svec is
signal clk_10m_ext : std_logic;
-- Reset logic
signal rst_62m5_n : std_logic;
signal rstlogic_arst_n : std_logic;
signal rstlogic_clk_in : std_logic_vector(1 downto 0);
signal rstlogic_rst_out : std_logic_vector(1 downto 0);
signal areset_edge_ppulse : std_logic;
signal rst_62m5_n : std_logic;
signal rstlogic_arst_n : std_logic;
signal rstlogic_clk_in : std_logic_vector(1 downto 0);
signal rstlogic_rst_out : std_logic_vector(1 downto 0);
-- PLL DAC ARB
signal dac_sync_n : std_logic_vector(1 downto 0);
......@@ -347,9 +351,21 @@ begin -- architecture struct
-----------------------------------------------------------------------------
-- Reset logic
-----------------------------------------------------------------------------
-- Detect when areset_edge_n_i goes high (end of reset) and use this edge to
-- generate rstlogic_arst_n. This is needed to connect optional reset like PCIe
-- reset. When baord runs standalone, we need to ignore PCIe reset being
-- constantly low.
cmp_arst_edge: gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => clk_pll_62m5,
rst_n_i => '1',
data_i => areset_edge_n_i,
ppulse_o => areset_edge_ppulse);
-- logic AND of all async reset sources (active low)
rstlogic_arst_n <= pll_locked and areset_n_i;
rstlogic_arst_n <= pll_locked and areset_n_i and (not areset_edge_ppulse);
-- concatenation of all clocks required to have synced resets
rstlogic_clk_in(0) <= clk_pll_62m5;
......
board/vfchd/wr_vfchd_pkg.vhd
View file @ a595a117
......@@ -32,6 +32,7 @@ package wr_vfchd_pkg is
clk_10m_ext_i : in std_logic := '0';
pps_ext_i : in std_logic := '0';
areset_n_i : in std_logic;
areset_edge_n_i : in std_logic := '1';
clk_sys_62m5_o : out std_logic;
clk_ref_125m_o : out std_logic;
rst_sys_62m5_n_o : out std_logic;
......@@ -119,6 +120,7 @@ package wr_vfchd_pkg is
clk_10m_ext_i : in std_logic := '0';
pps_ext_i : in std_logic := '0';
areset_n_i : in std_logic;
areset_edge_n_i : in std_logic := '1';
clk_sys_62m5_o : out std_logic;
clk_ref_125m_o : out std_logic;
rst_sys_62m5_n_o : out std_logic;
......
board/vfchd/wrc_board_vfchd.vhd
View file @ a595a117
......@@ -95,6 +95,9 @@ entity wrc_board_vfchd is
pps_ext_i : in std_logic := '0';
-- Reset input (active low, can be async)
areset_n_i : in std_logic;
-- Optional reset input active low with rising edge detection. Does not
-- reset PLLs.
areset_edge_n_i : in std_logic := '1';
-- 62.5MHz sys clock output
clk_sys_62m5_o : out std_logic;
-- 125MHz ref clock output
......@@ -404,6 +407,7 @@ begin -- architecture struct
clk_aux_i => clk_aux_i,
clk_10m_ext_i => clk_10m_ext_i,
areset_n_i => areset_n_i,
areset_edge_n_i => areset_edge_n_i,
clk_sys_62m5_o => clk_sys_62m5_o,
clk_ref_125m_o => clk_ref_125m_o,
rst_sys_62m5_n_o => rst_sys_62m5_n_o,
......
board/vfchd/xwrc_board_vfchd.vhd
View file @ a595a117
......@@ -93,6 +93,9 @@ entity xwrc_board_vfchd is
pps_ext_i : in std_logic := '0';
-- Reset input (active low, can be async)
areset_n_i : in std_logic;
-- Optional reset input active low with rising edge detection. Does not
-- reset PLLs.
areset_edge_n_i : in std_logic := '1';
-- 62.5MHz sys clock output
clk_sys_62m5_o : out std_logic;
-- 125MHz ref clock output
......@@ -240,10 +243,11 @@ architecture struct of xwrc_board_vfchd is
signal clk_10m_ext : std_logic;
-- Reset logic
signal rst_62m5_n : std_logic;
signal rstlogic_arst_n : std_logic;
signal rstlogic_clk_in : std_logic_vector(1 downto 0);
signal rstlogic_rst_out : std_logic_vector(1 downto 0);
signal areset_edge_ppulse : std_logic;
signal rst_62m5_n : std_logic;
signal rstlogic_arst_n : std_logic;
signal rstlogic_clk_in : std_logic_vector(1 downto 0);
signal rstlogic_rst_out : std_logic_vector(1 downto 0);
-- PLL DAC ARB
signal dac_sync_n : std_logic_vector(1 downto 0);
......@@ -314,9 +318,21 @@ begin -- architecture struct
-----------------------------------------------------------------------------
-- Reset logic
-----------------------------------------------------------------------------
-- Detect when areset_edge_n_i goes high (end of reset) and use this edge to
-- generate rstlogic_arst_n. This is needed to connect optional reset like PCIe
-- reset. When baord runs standalone, we need to ignore PCIe reset being
-- constantly low.
cmp_arst_edge: gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => clk_pll_62m5,
rst_n_i => '1',
data_i => areset_edge_n_i,
ppulse_o => areset_edge_ppulse);
-- logic AND of all async reset sources (active low)
rstlogic_arst_n <= pll_locked and areset_n_i;
rstlogic_arst_n <= pll_locked and areset_n_i and (not areset_edge_ppulse);
-- concatenation of all clocks required to have synced resets
rstlogic_clk_in(0) <= clk_pll_62m5;
......
top/spec_ref_design/spec_wr_ref_top.vhd
View file @ a595a117
......@@ -262,7 +262,6 @@ architecture top of spec_wr_ref_top is
signal gn_wbadr : std_logic_vector(31 downto 0);
-- clock and reset
signal areset_n : std_logic;
signal clk_sys_62m5 : std_logic;
signal rst_sys_62m5_n : std_logic;
signal rst_ref_125m_n : std_logic;
......@@ -298,13 +297,6 @@ architecture top of spec_wr_ref_top is
begin -- architecture top
------------------------------------------------------------------------------
-- System reset
------------------------------------------------------------------------------
-- logic AND of all async reset sources (active low)
areset_n <= button1_i and gn_rst_n;
-----------------------------------------------------------------------------
-- Primary wishbone Crossbar
-----------------------------------------------------------------------------
......@@ -426,7 +418,8 @@ begin -- architecture top
g_dpram_initf => g_dpram_initf,
g_fabric_iface => ETHERBONE)
port map (
areset_n_i => areset_n,
areset_n_i => button1_i,
areset_edge_n_i => gn_rst_n,
clk_20m_vcxo_i => clk_20m_vcxo_i,
clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
......
top/svec_ref_design/svec_wr_ref_top.vhd
View file @ a595a117
......@@ -233,7 +233,6 @@ architecture top of svec_wr_ref_top is
signal cnx_slave_in : t_wishbone_slave_in_array(c_NUM_WB_SLAVES-1 downto 0);
-- clock and reset
signal areset_n : std_logic;
signal clk_sys_62m5 : std_logic;
signal rst_sys_62m5_n : std_logic;
signal clk_ref_125m : std_logic;
......@@ -274,13 +273,6 @@ architecture top of svec_wr_ref_top is
begin -- architecture top
------------------------------------------------------------------------------
-- System reset
------------------------------------------------------------------------------
-- logic AND of all async reset sources (active low)
areset_n <= vme_sysreset_n_i and rst_n_i;
-----------------------------------------------------------------------------
-- Primary wishbone Crossbar
-----------------------------------------------------------------------------
......@@ -365,7 +357,8 @@ begin -- architecture top
clk_125m_gtp_n_i => clk_125m_gtp_n_i,
clk_125m_gtp_p_i => clk_125m_gtp_p_i,
clk_10m_ext_i => clk_ext_ref,
areset_n_i => areset_n,
areset_n_i => rst_n_i,
areset_edge_n_i => vme_sysreset_n_i,
clk_sys_62m5_o => clk_sys_62m5,
clk_ref_125m_o => clk_ref_125m,
rst_sys_62m5_n_o => rst_sys_62m5_n,
......
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