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White Rabbit core collection
Commit aa36aa47 authored by Maciej Lipinski's avatar Maciej Lipinski
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[wr_streamers_demo] Update of the testbench for steamers. 

This follows update of the top in: top/spec_1_1/wr_streamers_demo
that is used by this testbench. After the updated of the top, few
changes were needed in the simulation:
- update of inputs/outputs in the main
- addition of a (dummy) synthesis_description.vhd (this is generated
  when synthesising, yet needed for compilation in simulation. Since,
  the data in this file is not really important in simulation, no
  need for generation of the file, dummy version is OK
- waveform updated
parent 15403bb0
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Showing with 80 additions and 46 deletions
testbench/wr_streamers/streamers-on-spec_trigger-distribution/Manifest.py
View file @ aa36aa47
......@@ -11,7 +11,7 @@ modules = { "local" : ["../../..",
"../../../modules/wr_streamers",
"../../../top/spec_1_1/wr_streamers_demo",
"../../../ip_cores/general-cores"]}
files = ["main.sv"]
files = ["main.sv","synthesis_descriptor.vhd"]
testbench/wr_streamers/streamers-on-spec_trigger-distribution/main.sv
View file @ aa36aa47
......@@ -46,8 +46,8 @@ module main;
.clk_125m_pllref_p_i (clk_ref),
.clk_125m_pllref_n_i (~clk_ref),
.fpga_pll_ref_clk_101_p_i (clk_ref),
.fpga_pll_ref_clk_101_n_i (~clk_ref),
.clk_125m_gtp_p_i (clk_ref),
.clk_125m_gtp_n_i (~clk_ref),
.clk_20m_vcxo_i(clk_20m),
......@@ -71,8 +71,8 @@ module main;
.clk_125m_pllref_p_i (clk_ref),
.clk_125m_pllref_n_i (~clk_ref),
.fpga_pll_ref_clk_101_p_i (clk_ref),
.fpga_pll_ref_clk_101_n_i (~clk_ref),
.clk_125m_gtp_p_i (clk_ref),
.clk_125m_gtp_n_i (~clk_ref),
.clk_20m_vcxo_i(clk_20m),
......@@ -91,8 +91,8 @@ module main;
// observe the link LEDs on both sides, and tell us when the link is ready.
wire link_up_a = SPEC_A.U_The_WR_Core.led_link_o;
wire link_up_b = SPEC_B.U_The_WR_Core.led_link_o;
wire link_up_a = SPEC_A.cmp_xwrc_board_spec.led_link_o;
wire link_up_b = SPEC_B.cmp_xwrc_board_spec.led_link_o;
initial begin
// wait until both SPECs see the Ethernet link. Otherwise the packet we're going
......
testbench/wr_streamers/streamers-on-spec_trigger-distribution/synthesis_descriptor.vhd 0 → 100644
View file @ aa36aa47
--------------------------------------------------------------------------------
-- SDB meta information for spec_wr_ref.xise.
--
-- This file was automatically generated by ../../ip_cores/general-cores/tools/sdb_desc_gen.tcl on:
-- Monday, May 13 2019
--
-- ../../ip_cores/general-cores/tools/sdb_desc_gen.tcl is part of OHWR general-cores:
-- https://www.ohwr.org/projects/general-cores/wiki
--
-- For more information on SDB meta information, see also:
-- https://www.ohwr.org/projects/sdb/wiki
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.wishbone_pkg.all;
package synthesis_descriptor is
constant c_sdb_synthesis_info : t_sdb_synthesis := (
syn_module_name => "spec_wr_ref ",
syn_commit_id => "94c94685dfc78fe1c2e81ba0467dc7b*",
syn_tool_name => "ISE ",
syn_tool_version => x"00000147",
syn_date => x"20190513",
syn_username => "Maciej Lipinski");
constant c_sdb_repo_url : t_sdb_repo_url := (
repo_url => "https://ohwr.org/project/wr-cores.git ");
end package synthesis_descriptor;
testbench/wr_streamers/streamers-on-spec_trigger-distribution/wave.do
View file @ aa36aa47
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /main/link_up_a
add wave -noupdate /main/link_up_b
add wave -noupdate -divider {SPEC A-common}
add wave -noupdate -radix hexadecimal /main/SPEC_A/U_Pulse_Stamper/clk_ref_i
add wave -noupdate -radix hexadecimal /main/SPEC_A/U_Pulse_Stamper/clk_sys_i
add wave -noupdate -radix hexadecimal /main/SPEC_A/U_Pulse_Stamper/rst_n_i
add wave -noupdate -divider {SPEC A - WR timing}
add wave -noupdate /main/SPEC_A/dio_p_i(1)
add wave -noupdate -radix hexadecimal /main/SPEC_A/U_Pulse_Stamper/tm_time_valid_i
add wave -noupdate -radix hexadecimal /main/SPEC_A/U_Pulse_Stamper/tm_tai_i
add wave -noupdate -radix hexadecimal /main/SPEC_A/U_Pulse_Stamper/tm_cycles_i
add wave -noupdate -radix hexadecimal /main/link_up_a
add wave -noupdate -radix hexadecimal /main/link_up_b
add wave -noupdate -divider {SPEC A - common}
add wave -noupdate -radix hexadecimal /main/SPEC_A/clk_sys_62m5
add wave -noupdate -radix hexadecimal /main/SPEC_A/rst_sys_62m5_n
add wave -noupdate -radix hexadecimal /main/SPEC_A/rst_ref_125m_n
add wave -noupdate -radix hexadecimal /main/SPEC_A/clk_ref_125m
add wave -noupdate -divider {SPEC A - WR Timing}
add wave -noupdate -radix hexadecimal /main/SPEC_A/dio_p_i(1)
add wave -noupdate -radix hexadecimal /main/SPEC_A/cmp_xwrc_board_spec/tm_time_valid_o
add wave -noupdate -radix hexadecimal /main/SPEC_A/cmp_xwrc_board_spec/tm_tai_o
add wave -noupdate -radix hexadecimal /main/SPEC_A/cmp_xwrc_board_spec/tm_cycles_o
add wave -noupdate -divider {SPEC A - pulse stamper}
add wave -noupdate -radix hexadecimal /main/SPEC_A/U_Pulse_Stamper/tag_tai_o
add wave -noupdate -radix hexadecimal /main/SPEC_A/U_Pulse_Stamper/tag_cycles_o
add wave -noupdate -radix hexadecimal /main/SPEC_A/U_Pulse_Stamper/tag_valid_o
add wave -noupdate -divider {SPEC A - TX Streamer}
add wave -noupdate -radix hexadecimal /main/SPEC_A/U_TX_Streamer/tx_data_i
add wave -noupdate -radix hexadecimal /main/SPEC_A/U_TX_Streamer/tx_valid_i
add wave -noupdate -radix hexadecimal /main/SPEC_A/U_TX_Streamer/tx_dreq_o
add wave -noupdate -radix hexadecimal /main/SPEC_A/U_TX_Streamer/src_i
add wave -noupdate -radix hexadecimal /main/SPEC_A/U_TX_Streamer/src_o
add wave -noupdate -radix hexadecimal /main/SPEC_A/cmp_xwrc_board_spec/wrs_tx_data_i
add wave -noupdate -radix hexadecimal /main/SPEC_A/cmp_xwrc_board_spec/wrs_tx_valid_i
add wave -noupdate -radix hexadecimal /main/SPEC_A/cmp_xwrc_board_spec/wrs_tx_dreq_o
add wave -noupdate -radix hexadecimal /main/SPEC_A/cmp_xwrc_board_spec/cmp_board_common/gen_wr_streamers/cmp_xwr_streamers/src_i
add wave -noupdate -radix hexadecimal /main/SPEC_A/cmp_xwrc_board_spec/cmp_board_common/gen_wr_streamers/cmp_xwr_streamers/src_o
add wave -noupdate -divider {SPEC A - PHY}
add wave -noupdate -radix hexadecimal /main/SPEC_A/phy_tx_data
add wave -noupdate -radix hexadecimal /main/SPEC_A/phy_tx_k
add wave -noupdate -radix hexadecimal /main/SPEC_A/phy_tx_disparity
add wave -noupdate -radix hexadecimal /main/SPEC_A/phy_tx_enc_err
add wave -noupdate -radix hexadecimal /main/SPEC_A/cmp_xwrc_board_spec/cmp_board_common/phy8_o.tx_data
add wave -noupdate -radix hexadecimal /main/SPEC_A/cmp_xwrc_board_spec/cmp_board_common/phy8_o.tx_k
add wave -noupdate -radix hexadecimal /main/SPEC_A/cmp_xwrc_board_spec/cmp_board_common/phy8_i.tx_disparity
add wave -noupdate -radix hexadecimal /main/SPEC_A/cmp_xwrc_board_spec/cmp_board_common/phy8_i.tx_enc_err
add wave -noupdate -divider {SPEC B - PHY}
add wave -noupdate -radix hexadecimal /main/SPEC_B/phy_rx_data
add wave -noupdate -radix hexadecimal /main/SPEC_B/phy_rx_rbclk
add wave -noupdate -radix hexadecimal /main/SPEC_B/phy_rx_k
add wave -noupdate -radix hexadecimal /main/SPEC_B/phy_rx_enc_err
add wave -noupdate -radix hexadecimal /main/SPEC_B/cmp_xwrc_board_spec/cmp_board_common/phy8_i.rx_data
add wave -noupdate -radix hexadecimal /main/SPEC_B/cmp_xwrc_board_spec/cmp_board_common/phy8_i.ref_clk
add wave -noupdate -radix hexadecimal /main/SPEC_B/cmp_xwrc_board_spec/cmp_board_common/phy8_o.tx_k
add wave -noupdate -radix hexadecimal /main/SPEC_B/cmp_xwrc_board_spec/cmp_board_common/phy8_i.tx_enc_err
add wave -noupdate -divider {SPEC B - WR timing}
add wave -noupdate -radix hexadecimal /main/SPEC_B/U_Pulse_Stamper/tm_time_valid_i
add wave -noupdate -radix hexadecimal /main/SPEC_B/U_Pulse_Stamper/tm_tai_i
add wave -noupdate -radix hexadecimal /main/SPEC_B/U_Pulse_Stamper/tm_cycles_i
add wave -noupdate -divider {SPEC B - RX streamer}
add wave -noupdate -radix hexadecimal /main/SPEC_B/U_RX_Streamer/snk_i
add wave -noupdate -radix hexadecimal /main/SPEC_B/U_RX_Streamer/snk_o
add wave -noupdate -radix hexadecimal /main/SPEC_B/U_RX_Streamer/rx_data_o
add wave -noupdate -radix hexadecimal /main/SPEC_B/U_RX_Streamer/rx_valid_o
add wave -noupdate -radix hexadecimal /main/SPEC_B/U_RX_Streamer/rx_dreq_i
add wave -noupdate /main/SPEC_B/U_Pulse_Stamper/tm_time_valid_i
add wave -noupdate /main/SPEC_B/U_Pulse_Stamper/tm_tai_i
add wave -noupdate /main/SPEC_B/U_Pulse_Stamper/tm_cycles_i
add wave -noupdate -divider {SPEC B - RX Streamer}
add wave -noupdate -radix hexadecimal /main/SPEC_B/cmp_xwrc_board_spec/cmp_board_common/gen_wr_streamers/cmp_xwr_streamers/snk_i
add wave -noupdate -radix hexadecimal /main/SPEC_B/cmp_xwrc_board_spec/cmp_board_common/gen_wr_streamers/cmp_xwr_streamers/snk_o
add wave -noupdate -radix hexadecimal /main/SPEC_B/rx_data
add wave -noupdate -radix hexadecimal /main/SPEC_B/rx_valid
add wave -noupdate -radix hexadecimal /main/SPEC_B/cmp_xwrc_board_spec/cmp_board_common/wrs_rx_data_o
add wave -noupdate -radix hexadecimal /main/SPEC_B/cmp_xwrc_board_spec/cmp_board_common/wrs_rx_valid_o
add wave -noupdate -radix hexadecimal /main/SPEC_B/cmp_xwrc_board_spec/cmp_board_common/wrs_rx_dreq_i
add wave -noupdate -divider {SPEC B - Timestamp adder}
add wave -noupdate -radix hexadecimal /main/SPEC_B/U_Add_Delay1/valid_i
add wave -noupdate -radix hexadecimal /main/SPEC_B/U_Add_Delay1/a_tai_i
add wave -noupdate -radix hexadecimal /main/SPEC_B/U_Add_Delay1/a_cycles_i
add wave -noupdate -radix hexadecimal /main/SPEC_B/U_Add_Delay1/b_tai_i
add wave -noupdate -radix hexadecimal /main/SPEC_B/U_Add_Delay1/b_cycles_i
add wave -noupdate -radix hexadecimal /main/SPEC_B/U_Add_Delay1/valid_o
add wave -noupdate -radix hexadecimal /main/SPEC_B/U_Add_Delay1/q_tai_o
add wave -noupdate -radix hexadecimal /main/SPEC_B/U_Add_Delay1/q_cycles_o
add wave -noupdate -radix hexadecimal /main/SPEC_B/U_Add_Delay1/valid_o
add wave -noupdate -divider {SPEC B - pulse generator}
add wave -noupdate -radix hexadecimal /main/SPEC_B/U_Pulse_Generator/trig_ready_o
add wave -noupdate -radix hexadecimal /main/SPEC_B/U_Pulse_Generator/trig_tai_i
add wave -noupdate -radix hexadecimal /main/SPEC_B/U_Pulse_Generator/trig_cycles_i
add wave -noupdate -radix hexadecimal /main/SPEC_B/U_Pulse_Generator/trig_valid_i
add wave -noupdate -radix hexadecimal /main/SPEC_B/U_Pulse_Generator/trig_ready_o
add wave -noupdate -radix hexadecimal /main/SPEC_B/U_Pulse_Generator/pulse_o
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {593239379560 fs} 1} {{Cursor 2} {538394383110 fs} 0}
configure wave -namecolwidth 150
WaveRestoreCursors {{Cursor 1} {560018003180 fs} 0} {{Cursor 2} {530003823340 fs} 0}
configure wave -namecolwidth 221
configure wave -valuecolwidth 152
configure wave -justifyvalue left
configure wave -signalnamewidth 1
......@@ -72,4 +75,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 fs} {839137496540 fs}
WaveRestoreZoom {0 fs} {55629 ns}
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