Commit b34eac40 authored by Maciej Lipinski's avatar Maciej Lipinski

[streamers] correction of internal delays for fixed-latency

This was previously implemented but got lost when the fixed latency
instreamers was re-done. The idea is to compensate for internal
delays, so that the tx/rx_valid signals are as close to the
configured latency as possible.

Corrected simulation accordingly: the simulation also corrected for
delays.
parent 7f62305e
Pipeline #209 failed with stages
in 7 seconds
......@@ -118,7 +118,7 @@ architecture rtl of fixed_latency_ts_match is
signal trig : std_logic;
signal arm_synced_p, arm_synced_p_d : std_logic;
signal wait_cnt : unsigned(23 downto 0);
signal int_del_corr : unsigned(27 downto 0);
begin
......@@ -130,6 +130,22 @@ begin
end if;
end process;
-- Compensate for internal delays of streamers. The reference signals are
-- rx_valid_o and tx_valid_i in xwr_streamers. The numbers were obtained
-- by measuring the delay between these two signal in simulation and in
-- hardware. The delay depends whether the ref_clk is used for data or not.
-- NOTE: the compensation values are in a range that is unlikely to be set
-- as desired fixed_latency, thus the corrected value of fixed_latency
-- will be still a positive value. No need for prevention means (additinal
-- 'if').
gen_data_synchronous_to_wr_corr : if g_use_ref_clock_for_data /= 0 generate
int_del_corr <= to_unsigned(3, 28);
end generate ;
gen_data_asynchronous_to_wr_corr : if g_use_ref_clock_for_data = 0 generate
int_del_corr <= to_unsigned(12, 28);
end generate ;
-- clk_ref_i domain: tm_cycles_i
-- sys_clk domain: ts_latency_i & ts_timeout_i
-- scale the cycle counts depending what clack is used as ref_clk.
......@@ -138,11 +154,11 @@ begin
begin
if g_clk_ref_rate = 62500000 then
tm_cycles_scaled <= unsigned(tm_cycles_i & '0');
ts_latency_scaled <= unsigned(ts_latency_i & '0');
ts_latency_scaled <= unsigned(ts_latency_i & '0') - unsigned(int_del_corr & '0');
ts_timeout_scaled <= unsigned(ts_timeout_i & '0');
elsif g_clk_ref_rate = 125000000 then
tm_cycles_scaled <= unsigned('0' & tm_cycles_i);
ts_latency_scaled <= unsigned('0' & ts_latency_i);
ts_latency_scaled <= unsigned('0' & ts_latency_i) - unsigned('0' & int_del_corr);
ts_timeout_scaled <= unsigned('0' & ts_timeout_i);
else
report "Unsupported g_clk_ref_rate (62.5 / 125 MHz)" severity failure;
......
......@@ -215,9 +215,6 @@ architecture rtl of xrx_streamer is
signal rx_latency_valid : std_logic;
signal is_vlan : std_logic;
constant c_fixed_latency_zero : unsigned(27 downto 0) := (others => '0');
constant c_timestamper_delay : unsigned(27 downto 0) := to_unsigned(12, 28); -- cycles
signal fifo_last_int : std_logic;
signal rst_int_n : std_logic;
......
......@@ -295,7 +295,7 @@ module main;
// Got a record? Compare it against the copy stored in queue.
automatic t_queue_entry qe = queue.pop_front();
automatic time ts_rx = $time, delta;
const time c_pipeline_delay = 64ns;
const time c_pipeline_delay = 16ns;
if( rx_streamer_data != qe.data )
......
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