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White Rabbit core collection
Commit b465dcb3 authored by Stefan Rauch's avatar Stefan Rauch Committed by Wesley W. Terpstra
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First attempt to enable 1-wire on SCU

parent f2b94b45
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Showing with 17 additions and 2 deletions
syn/gsi_scu/wr_core_demo/scu.qsf
View file @ b465dcb3
...@@ -980,4 +980,6 @@ set_global_assignment -name VHDL_FILE ../../../top/gsi_scu/wr_core_demo/uart/sli ...@@ -980,4 +980,6 @@ set_global_assignment -name VHDL_FILE ../../../top/gsi_scu/wr_core_demo/uart/sli
set_global_assignment -name VERILOG_FILE ../../../top/gsi_scu/wr_core_demo/serirq_slave.v set_global_assignment -name VERILOG_FILE ../../../top/gsi_scu/wr_core_demo/serirq_slave.v
set_global_assignment -name VERILOG_FILE ../../../top/gsi_scu/wr_core_demo/serirq_defines.v set_global_assignment -name VERILOG_FILE ../../../top/gsi_scu/wr_core_demo/serirq_defines.v
set_global_assignment -name VHDL_FILE ../../../top/gsi_scu/wr_core_demo/scu_top_wo_timestamp.vhd set_global_assignment -name VHDL_FILE ../../../top/gsi_scu/wr_core_demo/scu_top_wo_timestamp.vhd
set_location_assignment PIN_AF1 -to OneWire_CB
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OneWire_CB
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
top/gsi_scu/wr_core_demo/scu_top.vhd
View file @ b465dcb3
...@@ -62,7 +62,12 @@ entity scu_top is ...@@ -62,7 +62,12 @@ entity scu_top is
----------------------------------------------------------------------- -----------------------------------------------------------------------
-- User LEDs -- User LEDs
----------------------------------------------------------------------- -----------------------------------------------------------------------
leds_o : out std_logic_vector(3 downto 0) leds_o : out std_logic_vector(3 downto 0);
-----------------------------------------------------------------------
-- OneWire
-----------------------------------------------------------------------
OneWire_CB : inout std_logic
); );
...@@ -394,9 +399,16 @@ architecture rtl of scu_top is ...@@ -394,9 +399,16 @@ architecture rtl of scu_top is
signal eca_toggle: std_logic_vector(31 downto 0); signal eca_toggle: std_logic_vector(31 downto 0);
signal owr_en_o: std_logic;
signal owr_i: std_logic;
begin begin
-- open drain buffer for one wire
owr_i <= OneWire_CB;
OneWire_CB <= '0' when owr_en_o = '1' else 'Z';
Inst_flash_loader_v01 : flash_loader Inst_flash_loader_v01 : flash_loader
port map ( port map (
noe_in => '0' noe_in => '0'
...@@ -459,7 +471,8 @@ begin ...@@ -459,7 +471,8 @@ begin
uart_rxd_i => uart_rxd_i(0), uart_rxd_i => uart_rxd_i(0),
uart_txd_o => uart_txd_o(0), uart_txd_o => uart_txd_o(0),
owr_i => '0', owr_en_o => owr_en_o,
owr_i => owr_i,
slave_i => cbar_master_o(2), slave_i => cbar_master_o(2),
slave_o => cbar_master_i(2), slave_o => cbar_master_i(2),
......
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