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Commit b5fb9ebd authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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wr_endpoint: ep_packet_filter: fixed invalid clock line, added (commented) chipscope for HW testing

parent 77dd337a
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modules/wr_endpoint/ep_packet_filter.vhd
View file @ b5fb9ebd
......@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-11-18
-- Last update: 2011-10-21
-- Last update: 2011-10-27
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -151,19 +151,74 @@ architecture behavioral of ep_packet_filter is
signal ra, rb, rc, result1, result2, rd : std_logic;
signal pmem_addr : unsigned(c_PC_SIZE-1 downto 0);
signal pmem_rdata : std_logic_vector(15 downto 0);
signal mm_addr : std_logic_vector(c_PC_SIZE-1 downto 0);
signal mm_write : std_logic;
signal mm_rdata, mm_wdata : std_logic_vector(35 downto 0);
type t_state is (WAIT_FRAME, PROCESS_FRAME, GEN_OUTPUT);
signal stage1, stage2 : std_logic;
component chipscope_ila
port (
CONTROL : inout std_logic_vector(35 downto 0);
CLK : in std_logic;
TRIG0 : in std_logic_vector(31 downto 0);
TRIG1 : in std_logic_vector(31 downto 0);
TRIG2 : in std_logic_vector(31 downto 0);
TRIG3 : in std_logic_vector(31 downto 0));
end component;
component chipscope_icon
port (
CONTROL0 : inout std_logic_vector (35 downto 0));
end component;
signal CONTROL : std_logic_vector(35 downto 0);
signal CLK : std_logic;
signal TRIG0 : std_logic_vector(31 downto 0);
signal TRIG1 : std_logic_vector(31 downto 0);
signal TRIG2 : std_logic_vector(31 downto 0);
signal TRIG3 : std_logic_vector(31 downto 0);
begin -- behavioral
chipscope_icon_1 : chipscope_icon
port map (
CONTROL0 => CONTROL);
chipscope_ila_1 : chipscope_ila
port map (
CONTROL => CONTROL,
CLK => clk_rx_i,
TRIG0 => TRIG0,
TRIG1 => TRIG1,
TRIG2 => TRIG2,
TRIG3 => TRIG3);
TRIG0 <= regs;
trig1 <= ir(31 downto 0);
trig2(3 downto 0) <= ir(35 downto 32);
trig2(4) <= stage1;
trig2(5) <= stage2;
trig2(6) <= result_cmp;
trig2(12 downto 7) <= std_logic_vector(pc);
trig2(31 downto 16) <= pmem_rdata;
trig2(13) <=mm_write;
trig2(14) <= result1;
trig2(15) <= result2;
trig3(0)<= done_int;
trig3(1)<=snk_fab_i.dvalid;
trig3(2)<=snk_fab_i.sof;
trig3(3)<=snk_fab_i.eof;
trig3(4)<=snk_fab_i.error;
trig3(31 downto 16) <= snk_fab_i.data;
mm_write <= not regs_i.pfcr0_enable_o and regs_i.pfcr0_mm_write_o and regs_i.pfcr0_mm_write_wr_o;
mm_wdata <= regs_i.pfcr0_mm_data_msb_o & regs_i.pfcr1_mm_data_lsb_o;
......@@ -297,7 +352,7 @@ begin -- behavioral
p_gen_status : process(clk_rx_i)
begin
if rising_edge(clk_sys_i) then
if rising_edge(clk_rx_i) then
if (rst_n_rx_i = '0' or snk_fab_i.sof = '1' or snk_fab_i.eof = '1' or snk_fab_i.error = '1') then
done_int <= '0';
drop_o <= '0';
......@@ -328,3 +383,4 @@ begin -- behavioral
end behavioral;
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