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White Rabbit core collection
Commit b84246f9 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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Revert "platform/xilinx: replace PLLs with DCMs on Spartan-6" - DCM is much more jittery 

This reverts commit 21c67bc8.
DCM is much more jittery than PLL_BASE:
DCM_SP:
125MHz -> 62.5MHz: pk-to-pk jitter: 300ps
125MHz -> 125MHz: pk-to-pk jitter: 200ps
20MHz -> 62.5MHz: pk-to-pk jitter: 1772ps (!!!!)

PLL_BASE:
125MHz -> 62.5MHz: pk-to-pk jitter: 185ps
125MHz-> 125MHz: pk-to-pk jitter 161ps
20MHz -> 62.5MHz: pk-to-pk jitter 417ps
parent 0d636aa5
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Showing with 113 additions and 175 deletions
board/spec/wr_spec_pkg.vhd
View file @ b84246f9
......@@ -7,7 +7,7 @@
-- Author(s) : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-02-17
-- Last update: 2018-11-28
-- Last update: 2018-07-25
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Copyright (c) 2017 CERN
......@@ -41,7 +41,6 @@ use work.wrcore_pkg.all;
use work.wr_fabric_pkg.all;
use work.endpoint_pkg.all;
use work.wr_board_pkg.all;
use work.wr_xilinx_pkg.all;
use work.streamers_pkg.all;
package wr_spec_pkg is
......@@ -51,7 +50,6 @@ package wr_spec_pkg is
g_simulation : integer := 0;
g_with_external_clock_input : boolean := TRUE;
g_aux_clks : integer := 0;
g_aux_pll_config : t_px_pll_cfg := c_PX_DEFAULT_PLL_CFG;
g_fabric_iface : t_board_fabric_iface := plain;
g_streamers_op_mode : t_streamers_op_mode := TX_AND_RX;
g_tx_streamer_params : t_tx_streamer_params := c_tx_streamer_params_defaut;
......@@ -60,7 +58,8 @@ package wr_spec_pkg is
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
g_diag_ro_size : integer := 0;
g_diag_rw_size : integer := 0);
g_diag_rw_size : integer := 0;
g_ddr_clock_divider : integer := 3);
port (
areset_n_i : in std_logic;
areset_edge_n_i : in std_logic := '1';
......@@ -74,10 +73,9 @@ package wr_spec_pkg is
pps_ext_i : in std_logic := '0';
clk_sys_62m5_o : out std_logic;
clk_ref_125m_o : out std_logic;
clk_pll_aux_o : out std_logic;
rst_sys_62m5_n_o : out std_logic;
rst_ref_125m_n_o : out std_logic;
rst_pll_aux_n_o : out std_logic;
clk_ddr_o : out std_logic;
plldac_sclk_o : out std_logic;
plldac_din_o : out std_logic;
pll25dac_cs_n_o : out std_logic;
......
board/spec/wrc_board_spec.vhd
View file @ b84246f9
......@@ -7,7 +7,7 @@
-- Author(s) : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-02-17
-- Last update: 2018-11-28
-- Last update: 2018-03-20
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
......
board/spec/xwrc_board_spec.vhd
View file @ b84246f9
......@@ -7,14 +7,14 @@
-- Author(s) : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-02-17
-- Last update: 2018-11-28
-- Last update: 2018-07-25
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
-- needed to operate the core on the SPEC board.
-- http://www.ohwr.org/projects/spec/
-------------------------------------------------------------------------------
-- Copyright (c) 2017-2018 CERN
-- Copyright (c) 2017 CERN
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--
......@@ -61,16 +61,14 @@ entity xwrc_board_spec is
g_with_external_clock_input : boolean := TRUE;
-- Number of aux clocks syntonized by WRPC to WR timebase
g_aux_clks : integer := 0;
-- Config for the auxiliary PLL output
g_aux_pll_config : t_px_pll_cfg := c_PX_DEFAULT_PLL_CFG;
-- plain = expose WRC fabric interface
-- streamers = attach WRC streamers to fabric interface
-- etherbone = attach Etherbone slave to fabric interface
g_fabric_iface : t_board_fabric_iface := plain;
-- parameters configuration when g_fabric_iface = "streamers" (otherwise ignored)
g_streamers_op_mode : t_streamers_op_mode := TX_AND_RX;
g_tx_streamer_params : t_tx_streamer_params := c_tx_streamer_params_defaut;
g_rx_streamer_params : t_rx_streamer_params := c_rx_streamer_params_defaut;
g_streamers_op_mode : t_streamers_op_mode := TX_AND_RX;
g_tx_streamer_params : t_tx_streamer_params := c_tx_streamer_params_defaut;
g_rx_streamer_params : t_rx_streamer_params := c_rx_streamer_params_defaut;
-- memory initialisation file for embedded CPU
g_dpram_initf : string := "default_xilinx";
-- identification (id and ver) of the layout of words in the generic diag interface
......@@ -78,7 +76,11 @@ entity xwrc_board_spec is
g_diag_ver : integer := 0;
-- size the generic diag interface
g_diag_ro_size : integer := 0;
g_diag_rw_size : integer := 0);
g_diag_rw_size : integer := 0;
-- DDR clock divider setting
g_ddr_clock_divider :integer := 3
);
port (
---------------------------------------------------------------------------
-- Clocks/resets
......@@ -104,13 +106,11 @@ entity xwrc_board_spec is
clk_sys_62m5_o : out std_logic;
-- 125MHz ref clock output
clk_ref_125m_o : out std_logic;
-- Auxiliary clock output from PLL, configured through g_aux_pll_config.
-- Not to be confused with clk_aux_i and/or g_aux_clks parameter.
clk_pll_aux_o : out std_logic;
-- Programmable frequency DDR controller clock output (divider set in g_ddr3_clock_divider)
clk_ddr_o : out std_logic;
-- active low reset outputs, synchronous to 62m5 and 125m clocks
rst_sys_62m5_n_o : out std_logic;
rst_ref_125m_n_o : out std_logic;
rst_pll_aux_n_o : out std_logic;
---------------------------------------------------------------------------
-- Shared SPI interface to DACs
......@@ -273,17 +273,17 @@ architecture struct of xwrc_board_spec is
-- PLLs, clocks
signal clk_pll_62m5 : std_logic;
signal clk_pll_125m : std_logic;
signal clk_pll_ddr : std_logic;
signal clk_pll_dmtd : std_logic;
signal pll_locked : std_logic;
signal clk_10m_ext : std_logic;
signal clk_pll_aux : std_logic;
-- Reset logic
signal areset_edge_ppulse : std_logic;
signal rst_62m5_n : std_logic;
signal rstlogic_arst : std_logic;
signal rstlogic_clk_in : std_logic_vector(2 downto 0);
signal rstlogic_rst_out : std_logic_vector(2 downto 0);
signal rstlogic_arst_n : std_logic;
signal rstlogic_clk_in : std_logic_vector(1 downto 0);
signal rstlogic_rst_out : std_logic_vector(1 downto 0);
-- PLL DAC ARB
signal dac_hpll_load_p1 : std_logic;
......@@ -326,8 +326,8 @@ begin -- architecture struct
g_fpga_family => "spartan6",
g_with_external_clock_input => g_with_external_clock_input,
g_use_default_plls => TRUE,
g_aux_pll_config => g_aux_pll_config,
g_simulation => g_simulation)
g_simulation => g_simulation,
g_ddr_clock_divider => g_ddr_clock_divider)
port map (
areset_n_i => areset_n_i,
clk_10m_ext_i => clk_10m_ext_i,
......@@ -342,10 +342,10 @@ begin -- architecture struct
sfp_tx_fault_i => sfp_tx_fault_i,
sfp_los_i => sfp_los_i,
sfp_tx_disable_o => sfp_tx_disable_o,
clk_pll_aux_o => clk_pll_aux,
clk_62m5_sys_o => clk_pll_62m5,
clk_125m_ref_o => clk_pll_125m,
clk_62m5_dmtd_o => clk_pll_dmtd,
clk_ddr_o => clk_pll_ddr,
pll_locked_o => pll_locked,
clk_10m_ext_o => clk_10m_ext,
phy8_o => phy8_to_wrc,
......@@ -357,7 +357,7 @@ begin -- architecture struct
clk_sys_62m5_o <= clk_pll_62m5;
clk_ref_125m_o <= clk_pll_125m;
clk_pll_aux_o <= clk_pll_aux;
clk_ddr_o <= clk_pll_ddr;
-----------------------------------------------------------------------------
-- Reset logic
......@@ -375,29 +375,29 @@ begin -- architecture struct
data_i => areset_edge_n_i,
ppulse_o => areset_edge_ppulse);
-- logic AND of all async reset sources (active high)
rstlogic_arst <= (not pll_locked) and (not areset_n_i) and areset_edge_ppulse;
-- logic AND of all async reset sources (active low)
rstlogic_arst_n <= pll_locked and areset_n_i and (not areset_edge_ppulse);
-- concatenation of all clocks required to have synced resets
rstlogic_clk_in(0) <= clk_pll_62m5;
rstlogic_clk_in(1) <= clk_pll_125m;
rstlogic_clk_in(2) <= clk_pll_aux;
cmp_rstlogic_reset : gc_reset_multi_aasd
cmp_rstlogic_reset : gc_reset
generic map (
g_CLOCKS => 3, -- 62.5MHz, 125MHz, plus aux clk
g_RST_LEN => 16) -- 16 clock cycles
g_clocks => 2, -- 62.5MHz, 125MHz
g_logdelay => 4, -- 16 clock cycles
g_syncdepth => 3) -- length of sync chains
port map (
arst_i => rstlogic_arst,
clks_i => rstlogic_clk_in,
rst_n_o => rstlogic_rst_out);
free_clk_i => clk_125m_pllref_buf,
locked_i => rstlogic_arst_n,
clks_i => rstlogic_clk_in,
rstn_o => rstlogic_rst_out);
-- distribution of resets (already synchronized to their clock domains)
rst_62m5_n <= rstlogic_rst_out(0);
rst_sys_62m5_n_o <= rst_62m5_n;
rst_ref_125m_n_o <= rstlogic_rst_out(1);
rst_pll_aux_n_o <= rstlogic_rst_out(2);
-----------------------------------------------------------------------------
-- 2x SPI DAC
......
board/svec/wr_svec_pkg.vhd
View file @ b84246f9
......@@ -7,10 +7,10 @@
-- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-02-16
-- Last update: 2018-11-28
-- Last update: 2018-03-20
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Copyright (c) 2017-2018 CERN
-- Copyright (c) 2017 CERN
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--
......@@ -41,7 +41,6 @@ use work.wrcore_pkg.all;
use work.wr_fabric_pkg.all;
use work.endpoint_pkg.all;
use work.wr_board_pkg.all;
use work.wr_xilinx_pkg.all;
use work.streamers_pkg.all;
package wr_svec_pkg is
......@@ -51,7 +50,6 @@ package wr_svec_pkg is
g_simulation : integer := 0;
g_with_external_clock_input : boolean := TRUE;
g_aux_clks : integer := 0;
g_aux_pll_config : t_px_pll_cfg := c_PX_DEFAULT_PLL_CFG;
g_fabric_iface : t_board_fabric_iface := plain;
g_streamers_op_mode : t_streamers_op_mode := TX_AND_RX;
g_tx_streamer_params : t_tx_streamer_params := c_tx_streamer_params_defaut;
......@@ -74,10 +72,8 @@ package wr_svec_pkg is
pps_ext_i : in std_logic := '0';
clk_sys_62m5_o : out std_logic;
clk_ref_125m_o : out std_logic;
clk_pll_aux_o : out std_logic;
rst_sys_62m5_n_o : out std_logic;
rst_ref_125m_n_o : out std_logic;
rst_pll_aux_n_o : out std_logic;
pll20dac_din_o : out std_logic;
pll20dac_sclk_o : out std_logic;
pll20dac_sync_n_o : out std_logic;
......
board/svec/xwrc_board_svec.vhd
View file @ b84246f9
......@@ -7,14 +7,14 @@
-- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-02-16
-- Last update: 2018-11-28
-- Last update: 2018-06-22
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
-- needed to operate the core on the SVEC board.
-- http://www.ohwr.org/projects/svec/
-------------------------------------------------------------------------------
-- Copyright (c) 2017-2018 CERN
-- Copyright (c) 2017 CERN
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--
......@@ -61,16 +61,14 @@ entity xwrc_board_svec is
g_with_external_clock_input : boolean := TRUE;
-- Number of aux clocks syntonized by WRPC to WR timebase
g_aux_clks : integer := 0;
-- Config for the auxiliary PLL output
g_aux_pll_config : t_px_pll_cfg := c_PX_DEFAULT_PLL_CFG;
-- plain = expose WRC fabric interface
-- streamers = attach WRC streamers to fabric interface
-- etherbone = attach Etherbone slave to fabric interface
g_fabric_iface : t_board_fabric_iface := plain;
-- parameters configuration when g_fabric_iface = "streamers" (otherwise ignored)
g_streamers_op_mode : t_streamers_op_mode := TX_AND_RX;
g_tx_streamer_params : t_tx_streamer_params := c_tx_streamer_params_defaut;
g_rx_streamer_params : t_rx_streamer_params := c_rx_streamer_params_defaut;
g_tx_streamer_params : t_tx_streamer_params := c_tx_streamer_params_defaut;
g_rx_streamer_params : t_rx_streamer_params := c_rx_streamer_params_defaut;
-- memory initialisation file for embedded CPU
g_dpram_initf : string := "default_xilinx";
-- identification (id and ver) of the layout of words in the generic diag interface
......@@ -105,13 +103,9 @@ entity xwrc_board_svec is
clk_sys_62m5_o : out std_logic;
-- 125MHz ref clock output
clk_ref_125m_o : out std_logic;
-- Auxiliary clock output from PLL, configured through g_aux_pll_config.
-- Not to be confused with clk_aux_i and/or g_aux_clks parameter.
clk_pll_aux_o : out std_logic;
-- active low reset outputs, synchronous to their respective clocks
-- active low reset outputs, synchronous to 62m5 and 125m clocks
rst_sys_62m5_n_o : out std_logic;
rst_ref_125m_n_o : out std_logic;
rst_pll_aux_n_o : out std_logic;
---------------------------------------------------------------------------
-- SPI interfaces to DACs
......@@ -274,14 +268,13 @@ architecture struct of xwrc_board_svec is
signal clk_pll_dmtd : std_logic;
signal pll_locked : std_logic;
signal clk_10m_ext : std_logic;
signal clk_pll_aux : std_logic;
-- Reset logic
signal areset_edge_ppulse : std_logic;
signal rst_62m5_n : std_logic;
signal rstlogic_arst : std_logic;
signal rstlogic_clk_in : std_logic_vector(2 downto 0);
signal rstlogic_rst_out : std_logic_vector(2 downto 0);
signal rstlogic_arst_n : std_logic;
signal rstlogic_clk_in : std_logic_vector(1 downto 0);
signal rstlogic_rst_out : std_logic_vector(1 downto 0);
-- PLL DAC ARB
signal dac_sync_n : std_logic_vector(1 downto 0);
......@@ -327,7 +320,6 @@ begin -- architecture struct
g_fpga_family => "spartan6",
g_with_external_clock_input => g_with_external_clock_input,
g_use_default_plls => TRUE,
g_aux_pll_config => g_aux_pll_config,
g_simulation => g_simulation)
port map (
areset_n_i => areset_n_i,
......@@ -343,7 +335,6 @@ begin -- architecture struct
sfp_tx_fault_i => sfp_tx_fault_i,
sfp_los_i => sfp_los_i,
sfp_tx_disable_o => sfp_tx_disable_o,
clk_pll_aux_o => clk_pll_aux,
clk_62m5_sys_o => clk_pll_62m5,
clk_125m_ref_o => clk_pll_125m,
clk_62m5_dmtd_o => clk_pll_dmtd,
......@@ -358,14 +349,13 @@ begin -- architecture struct
clk_sys_62m5_o <= clk_pll_62m5;
clk_ref_125m_o <= clk_pll_125m;
clk_pll_aux_o <= clk_pll_aux;
-----------------------------------------------------------------------------
-- Reset logic
-----------------------------------------------------------------------------
-- Detect when areset_edge_n_i goes high (end of reset) and use this edge to
-- generate rstlogic_arst_n. This is needed to connect optional reset like PCIe
-- reset. When board runs standalone, we need to ignore PCIe reset being
-- reset. When baord runs standalone, we need to ignore PCIe reset being
-- constantly low.
cmp_arst_edge : gc_sync_ffs
generic map (
......@@ -382,12 +372,11 @@ begin -- architecture struct
-- concatenation of all clocks required to have synced resets
rstlogic_clk_in(0) <= clk_pll_62m5;
rstlogic_clk_in(1) <= clk_pll_125m;
rstlogic_clk_in(2) <= clk_pll_aux;
cmp_rstlogic_reset : gc_reset_multi_aasd
generic map (
g_CLOCKS => 3, -- 62.5MHz, 125MHz, plus aux clk
g_RST_LEN => 16) -- 16 clock cycles
g_CLOCKS => 2, -- 62.5MHz, 125MHz
g_RST_LEN => 16) -- 16 clock cycles
port map (
arst_i => rstlogic_arst,
clks_i => rstlogic_clk_in,
......@@ -398,7 +387,6 @@ begin -- architecture struct
rst_sys_62m5_n_o <= rst_62m5_n;
rst_ref_125m_n_o <= rstlogic_rst_out(1);
rst_pll_aux_n_o <= rstlogic_rst_out(2);
-----------------------------------------------------------------------------
-- 2x SPI DAC
......
platform/xilinx/wr_xilinx_pkg.vhd
View file @ b84246f9
......@@ -10,7 +10,7 @@
-- Standard : VHDL'93
-------------------------------------------------------------------------------
--
-- Copyright (c) 2016-2018 CERN / BE-CO-HT
-- Copyright (c) 2016-2017 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
......@@ -38,25 +38,11 @@ use work.endpoint_pkg.all;
package wr_xilinx_pkg is
-- Configuration of a PLL clock output
type t_px_pll_cfg is
record
enabled : boolean;
divide : integer;
multiply : integer;
end record t_px_pll_cfg;
constant c_PX_DEFAULT_PLL_CFG : t_px_pll_cfg := (
enabled => FALSE,
divide => 1,
multiply => 2);
component xwrc_platform_xilinx is
generic (
g_fpga_family : string := "spartan6";
g_with_external_clock_input : boolean := FALSE;
g_use_default_plls : boolean := TRUE;
g_aux_pll_config : t_px_pll_cfg := c_PX_DEFAULT_PLL_CFG;
g_gtp_enable_ch0 : integer := 0;
g_gtp_enable_ch1 : integer := 1;
g_gtp_mux_enable : boolean := FALSE;
......@@ -81,6 +67,7 @@ package wr_xilinx_pkg is
clk_ext_locked_i : in std_logic := '1';
clk_ext_stopped_i : in std_logic := '0';
clk_ext_rst_o : out std_logic;
clk_ddr_o : out std_logic;
sfp_txn_o : out std_logic;
sfp_txp_o : out std_logic;
sfp_rxn_i : in std_logic;
......@@ -96,7 +83,6 @@ package wr_xilinx_pkg is
sfp1_tx_fault_i : in std_logic := '0';
sfp1_los_i : in std_logic := '0';
sfp1_tx_disable_o : out std_logic;
clk_pll_aux_o : out std_logic;
clk_62m5_sys_o : out std_logic;
clk_125m_ref_o : out std_logic;
clk_ref_locked_o : out std_logic;
......
platform/xilinx/xwrc_platform_xilinx.vhd
View file @ b84246f9
......@@ -19,7 +19,7 @@
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2016-2018 CERN / BE-CO-HT
-- Copyright (c) 2016-2017 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
......@@ -60,8 +60,6 @@ entity xwrc_platform_xilinx is
g_with_external_clock_input : boolean := FALSE;
-- Set to FALSE if you want to instantiate your own PLLs
g_use_default_plls : boolean := TRUE;
-- Config for the auxiliary PLL output (for now only used in Spartan-6)
g_aux_pll_config : t_px_pll_cfg := c_PX_DEFAULT_PLL_CFG;
-- Select GTP channel to use
g_gtp_enable_ch0 : integer := 0;
g_gtp_enable_ch1 : integer := 1;
......@@ -137,10 +135,7 @@ entity xwrc_platform_xilinx is
sfp1_tx_fault_i : in std_logic := '0';
sfp1_los_i : in std_logic := '0';
sfp1_tx_disable_o : out std_logic;
---------------------------------------------------------------------------
--Auxiliary PLL output
---------------------------------------------------------------------------
clk_pll_aux_o : out std_logic;
---------------------------------------------------------------------------
--Interface to WR PTP Core (WRPC)
---------------------------------------------------------------------------
......@@ -149,6 +144,7 @@ entity xwrc_platform_xilinx is
clk_125m_ref_o : out std_logic;
clk_ref_locked_o : out std_logic;
clk_62m5_dmtd_o : out std_logic;
clk_ddr_o : out std_logic;
pll_locked_o : out std_logic;
clk_10m_ext_o : out std_logic;
-- PHY - CH0
......@@ -224,62 +220,61 @@ begin -- architecture rtl
gen_default_plls : if (g_use_default_plls = TRUE) generate
-- Default PLL setup consists of two DCMs.
-- Default PLL setup consists of two PLLs.
-- One takes a 125MHz clock signal as input and produces the
-- 62.5MHz WR PTP core main system clock and the 125MHz reference clock.
-- The other DCM takes a 20MHz clock signal as input and produces the
-- The other PLL takes a 20MHz clock signal as input and produces the
-- 62.5MHz DMTD clock.
--
-- A third DCM is instantiated if also g_with_external_clock_input = TRUE.
-- A third PLL is instantiated if also g_with_external_clock_input = TRUE.
-- In that case, a 10MHz external reference is multiplied to generate a
-- 125MHz reference clock
gen_spartan6_default_plls : if (g_fpga_family = "spartan6") generate
signal clk_sys : std_logic;
signal clk_sys_out : std_logic;
signal clk_sys_fb : std_logic;
signal pll_sys_locked : std_logic;
signal clk_dmtd : std_logic;
signal clk_dmtd_fb : std_logic;
signal pll_dmtd_locked : std_logic;
signal clk_20m_vcxo_buf : std_logic;
signal clk_pll_aux : std_logic;
signal clk_ddr : std_logic;
signal clk_125m_pllref_buf_int1 : std_logic;
signal clk_125m_pllref_buf_int2 : std_logic;
begin --gen_spartan6_default_plls
-- System DCM
cmp_sys_clk_dcm : DCM_SP
-- System PLL
cmp_sys_clk_pll : PLL_BASE
generic map (
CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => g_aux_pll_config.divide,
CLKFX_MULTIPLY => g_aux_pll_config.multiply,
CLKIN_DIVIDE_BY_2 => FALSE,
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 8,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 16,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 8,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 3,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 8.0,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clk_125m_pllref_buf_int1,
CLKFB => clk_125m_pllref_buf,
-- Output clocks
CLK0 => clk_125m_pllref_buf_int2,
CLKDV => clk_sys,
CLKFX => clk_pll_aux,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => pll_sys_locked,
STATUS => open,
RST => pll_arst,
-- Unused pin, tie low
DSSEN => '0');
REF_JITTER => 0.016)
port map (
CLKFBOUT => clk_sys_fb,
CLKOUT0 => clk_sys,
CLKOUT1 => clk_125m_pllref_buf_int2,
CLKOUT2 => clk_ddr,
LOCKED => pll_sys_locked,
RST => pll_arst,
CLKFBIN => clk_sys_fb,
CLKIN => clk_125m_pllref_buf_int1);
-- System PLL input clock buffer
cmp_clk_sys_buf_i : BUFG
......@@ -287,6 +282,12 @@ begin -- architecture rtl
O => clk_125m_pllref_buf_int1,
I => clk_125m_pllref_i);
-- DDR PLL global clock buffer
cmp_ddr_clk_buf_o : BUFG
port map (
O => clk_ddr_o,
I => clk_ddr);
-- System PLL output clock buffer
cmp_clk_sys_buf_o : BUFG
port map (
......@@ -304,59 +305,40 @@ begin -- architecture rtl
pll_locked_o <= pll_sys_locked and pll_dmtd_locked;
clk_ref_locked_o <= '1';
-- DMTD DCM
cmp_dmtd_clk_pll : DCM_SP
-- DMTD PLL
cmp_dmtd_clk_pll : PLL_BASE
generic map (
CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 8,
CLKFX_MULTIPLY => 25,
CLKIN_DIVIDE_BY_2 => FALSE,
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 50,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 16,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 50.0,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clk_20m_vcxo_buf,
-- Output clocks
CLKFX => clk_dmtd,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => pll_dmtd_locked,
STATUS => open,
RST => pll_arst,
-- Unused pin, tie low
DSSEN => '0');
REF_JITTER => 0.016)
port map (
CLKFBOUT => clk_dmtd_fb,
CLKOUT0 => clk_dmtd,
LOCKED => pll_dmtd_locked,
RST => pll_arst,
CLKFBIN => clk_dmtd_fb,
CLKIN => clk_20m_vcxo_buf);
-- DMTD DCM input clock buffer
-- DMTD PLL input clock buffer
cmp_clk_dmtd_buf_i : BUFG
port map (
O => clk_20m_vcxo_buf,
I => clk_20m_vcxo_i);
-- DMTD DCM output clock buffer
-- DMTD PLL output clock buffer
cmp_clk_dmtd_buf_o : BUFG
port map (
O => clk_62m5_dmtd_o,
I => clk_dmtd);
-- AUX PLL global clock buffer
gen_used_aux_clk : if g_aux_pll_config.enabled = TRUE generate
cmp_aux_clk_buf_o : BUFG
port map (
O => clk_pll_aux_o,
I => clk_pll_aux);
end generate gen_used_aux_clk;
gen_unused_aux_clk : if g_aux_pll_config.enabled = FALSE generate
clk_pll_aux_o <= '0';
end generate gen_unused_aux_clk;
gen_spartan6_ext_ref_pll : if (g_with_external_clock_input = TRUE) generate
......@@ -526,9 +508,6 @@ begin -- architecture rtl
O => clk_62m5_dmtd_o,
I => clk_dmtd);
-- drive unused auxiliary pll output to zero
clk_pll_aux_o <= '0';
end generate gen_virtex5_default_plls;
---------------------------------------------------------------------------
......@@ -753,9 +732,6 @@ begin -- architecture rtl
end generate gen_kintex7_ext_ref_pll;
-- drive unused auxiliary pll output to zero
clk_pll_aux_o <= '0';
end generate gen_kintex7_default_plls;
---------------------------------------------------------------------------
......@@ -990,9 +966,6 @@ begin -- architecture rtl
end generate gen_artix7_ext_ref_pll;
-- drive unused auxiliary pll output to zero
clk_pll_aux_o <= '0';
end generate gen_artix7_default_plls;
---------------------------------------------------------------------------
......@@ -1021,9 +994,6 @@ begin -- architecture rtl
ext_ref_mul_locked_o <= clk_ext_locked_i;
ext_ref_mul_stopped_o <= clk_ext_stopped_i;
-- drive unused auxiliary pll output to zero
clk_pll_aux_o <= '0';
end generate gen_custom_plls;
-- always pass ext reference reset input to output, even when not used
......
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