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White Rabbit core collection
Commit bcd1f0a3 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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update project files for reference designs

parent 610d5e38
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Showing with 2948 additions and 2921 deletions
syn/spec_ref_design/Makefile
View file @ bcd1f0a3
......@@ -18,7 +18,7 @@ generate_tcl:
echo "process run {Generate Programming File}" >> run.tcl
synthesis:
/home/greg/opt/Xilinx/14.5/ISE_DS/ISE/bin/lin64/xtclsh run.tcl
/home/greg/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xtclsh run.tcl
check_tool:
......@@ -103,6 +103,7 @@ spec_wr_ref.xise \
../../modules/wr_streamers/rx_streamer.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd \
../../modules/wr_endpoint/ep_rx_status_reg_insert.vhd \
../../modules/wr_streamers/xtx_streamers_stats.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd \
../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd \
../../modules/wr_endpoint/ep_registers_pkg.vhd \
......@@ -115,11 +116,11 @@ spec_wr_ref.xise \
../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v \
../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CRAM.vhd \
../../modules/wr_streamers/escape_detector.vhd \
../../modules/wr_endpoint/ep_ts_counter.vhd \
../../modules/wr_eca/eca_queue.vhd \
../../modules/wr_eca/eca_auto_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd \
../../modules/wr_streamers/gc_escape_inserter.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_pass_fifo.vhd \
../../modules/wr_mini_nic/wr_mini_nic.vhd \
......@@ -130,7 +131,6 @@ spec_wr_ref.xise \
../../ip_cores/general-cores/modules/common/gc_moving_average.vhd \
../../ip_cores/etherbone-core/hdl/eb_master_core/eb_commit_len_fifo.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd \
../../modules/wrc_core/wb_reset.vhd \
../../modules/wr_eca/eca_tag_channel.vhd \
../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CSR_pack.vhd \
../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd \
......@@ -159,9 +159,9 @@ spec_wr_ref.xise \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd \
../../modules/fabric/xwrf_loopback/lbk_pkg.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd \
../../modules/wr_streamers/xrx_streamers_stats.vhd \
../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd \
../../modules/wr_endpoint/ep_rx_crc_size_check.vhd \
../../modules/wr_streamers/wr_transmission_wb.vhd \
../../modules/wr_softpll_ng/xwr_softpll_ng.vhd \
../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_pkg.vhd \
../../modules/wr_mini_nic/minic_wb_slave.vhd \
......@@ -186,9 +186,9 @@ spec_wr_ref.xise \
../../modules/wr_endpoint/ep_tx_vlan_unit.vhd \
../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd \
../../modules/wrc_core/wrc_diags_wb.vhd \
../../modules/wr_pps_gen/xwr_pps_gen.vhd \
../../modules/wr_softpll_ng/spll_wbgen2_pkg.vhd \
../../modules/wr_streamers/wr_transmission_wbgen2_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_wbm_fifo.vhd \
../../modules/wr_eca/eca.vhd \
......@@ -211,6 +211,7 @@ spec_wr_ref.xise \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd \
../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd \
../../modules/wr_endpoint/ep_1000basex_pcs.vhd \
../../modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd \
../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd \
../../ip_cores/general-cores/modules/common/gc_single_reset_gen.vhd \
../../ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd \
......@@ -219,6 +220,7 @@ spec_wr_ref.xise \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd \
../../modules/wr_endpoint/ep_rx_bypass_queue.vhd \
../../modules/wr_streamers/escape_inserter.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tag_fifo.vhd \
../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd \
../../modules/wr_streamers/tx_streamer.vhd \
......@@ -252,6 +254,7 @@ spec_wr_ref.xise \
../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd \
../../platform/xilinx/xwrc_platform_xilinx.vhd \
../../modules/wr_endpoint/ep_timestamping_unit.vhd \
../../modules/wrc_core/wrc_diags_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd \
../../modules/wr_si57x_interface/si570_if_wb.vhd \
../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd \
......@@ -259,6 +262,7 @@ spec_wr_ref.xise \
../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_SharedComps.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd \
../../modules/wrc_core/xwr_core.vhd \
../../modules/wrc_core/xwrc_diags_wb.vhd \
../../modules/wr_eca/eca_piso_fifo.vhd \
../../modules/wrc_core/wrc_dpram.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd \
......@@ -271,7 +275,6 @@ spec_wr_ref.xise \
../../modules/fabric/xwb_fabric_source.vhd \
../../modules/wr_eca/eca_tlu_auto.vhd \
../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd \
../../modules/wr_streamers/xwr_transmission.vhd \
../../modules/wr_streamers/dropping_buffer.vhd \
../../modules/wr_softpll_ng/wr_softpll_ng.vhd \
../../modules/wr_tbi_phy/disparity_gen_pkg.vhd \
......@@ -298,7 +301,7 @@ spec_wr_ref.xise \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd \
../../ip_cores/general-cores/modules/common/matrix_pkg.vhd \
../../modules/wr_streamers/gc_escape_detector.vhd \
../../modules/wr_streamers/wr_streamers_wb.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd \
../../modules/wr_endpoint/ep_rx_vlan_unit.vhd \
../../ip_cores/general-cores/modules/common/gc_big_adder.vhd \
......@@ -362,10 +365,12 @@ spec_wr_ref.xise \
../../modules/wr_tbi_phy/wr_tbi_phy.vhd \
../../platform/xilinx/chipscope/chipscope_ila.ngc \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v \
../../modules/wr_eca/eca_queue_auto_pkg.vhd \
../../modules/timing/hpll_period_detect.vhd \
../../modules/wr_pps_gen/pps_gen_wb.vhd \
../../platform/xilinx/wr_gtp_phy/gtp_phase_align_virtex6.vhd \
../../modules/wr_endpoint/xwr_endpoint.vhd \
../../modules/wr_streamers/streamers_priv_pkg.vhd \
../../modules/wr_endpoint/ep_tx_packet_injection.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v \
......@@ -396,7 +401,7 @@ spec_wr_ref.xise \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd \
../../modules/wr_eca/eca_tdp.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd \
../../modules/wr_eca/eca_queue_auto_pkg.vhd \
../../modules/wr_streamers/xwr_streamers.vhd \
../../modules/wr_softpll_ng/softpll_pkg.vhd \
../../modules/wr_eca/eca_wr_time.vhd \
../../modules/wr_streamers/xrx_streamer.vhd \
......
syn/spec_ref_design/spec_wr_ref.xise
View file @ bcd1f0a3
This source diff could not be displayed because it is too large. You can view the blob instead.
syn/svec_ref_design/Makefile
View file @ bcd1f0a3
......@@ -18,7 +18,7 @@ generate_tcl:
echo "process run {Generate Programming File}" >> run.tcl
synthesis:
/home/greg/opt/Xilinx/14.5/ISE_DS/ISE/bin/lin64/xtclsh run.tcl
/home/greg/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xtclsh run.tcl
check_tool:
......@@ -101,6 +101,7 @@ FILES := ../../modules/wr_pps_gen/wr_pps_gen.vhd \
../../modules/wr_streamers/rx_streamer.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd \
../../modules/wr_endpoint/ep_rx_status_reg_insert.vhd \
../../modules/wr_streamers/xtx_streamers_stats.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd \
../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd \
../../modules/wr_endpoint/ep_registers_pkg.vhd \
......@@ -113,11 +114,11 @@ FILES := ../../modules/wr_pps_gen/wr_pps_gen.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v \
../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CRAM.vhd \
../../modules/wr_streamers/escape_detector.vhd \
../../modules/wr_endpoint/ep_ts_counter.vhd \
../../modules/wr_eca/eca_queue.vhd \
../../modules/wr_eca/eca_auto_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd \
../../modules/wr_streamers/gc_escape_inserter.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_pass_fifo.vhd \
../../modules/wr_mini_nic/wr_mini_nic.vhd \
......@@ -128,7 +129,6 @@ FILES := ../../modules/wr_pps_gen/wr_pps_gen.vhd \
../../ip_cores/general-cores/modules/common/gc_moving_average.vhd \
../../ip_cores/etherbone-core/hdl/eb_master_core/eb_commit_len_fifo.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd \
../../modules/wrc_core/wb_reset.vhd \
../../modules/wr_eca/eca_tag_channel.vhd \
../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CSR_pack.vhd \
../../board/svec/wr_svec_pkg.vhd \
......@@ -157,9 +157,9 @@ FILES := ../../modules/wr_pps_gen/wr_pps_gen.vhd \
../../modules/fabric/xwrf_loopback/lbk_pkg.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd \
../../modules/wr_streamers/xrx_streamers_stats.vhd \
../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd \
../../modules/wr_endpoint/ep_rx_crc_size_check.vhd \
../../modules/wr_streamers/wr_transmission_wb.vhd \
../../modules/wr_softpll_ng/xwr_softpll_ng.vhd \
../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_pkg.vhd \
../../modules/wr_mini_nic/minic_wb_slave.vhd \
......@@ -184,9 +184,9 @@ FILES := ../../modules/wr_pps_gen/wr_pps_gen.vhd \
../../modules/wr_endpoint/ep_tx_vlan_unit.vhd \
../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd \
../../modules/wrc_core/wrc_diags_wb.vhd \
../../modules/wr_pps_gen/xwr_pps_gen.vhd \
../../modules/wr_softpll_ng/spll_wbgen2_pkg.vhd \
../../modules/wr_streamers/wr_transmission_wbgen2_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd \
../../board/svec/xwrc_board_svec.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_wbm_fifo.vhd \
......@@ -211,6 +211,7 @@ svec_wr_ref.xise \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd \
../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd \
../../modules/wr_endpoint/ep_1000basex_pcs.vhd \
../../modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd \
../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd \
../../ip_cores/general-cores/modules/common/gc_single_reset_gen.vhd \
../../ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd \
......@@ -219,6 +220,7 @@ svec_wr_ref.xise \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd \
../../modules/wr_endpoint/ep_rx_bypass_queue.vhd \
../../modules/wr_streamers/escape_inserter.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tag_fifo.vhd \
../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd \
../../modules/wr_streamers/tx_streamer.vhd \
......@@ -252,6 +254,7 @@ svec_wr_ref.xise \
../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd \
../../platform/xilinx/xwrc_platform_xilinx.vhd \
../../modules/wr_endpoint/ep_timestamping_unit.vhd \
../../modules/wrc_core/wrc_diags_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd \
../../modules/wr_si57x_interface/si570_if_wb.vhd \
../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd \
......@@ -259,6 +262,7 @@ svec_wr_ref.xise \
../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_SharedComps.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd \
../../modules/wrc_core/xwr_core.vhd \
../../modules/wrc_core/xwrc_diags_wb.vhd \
../../modules/wr_eca/eca_piso_fifo.vhd \
../../modules/wrc_core/wrc_dpram.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd \
......@@ -270,7 +274,6 @@ svec_wr_ref.xise \
../../modules/fabric/xwb_fabric_source.vhd \
../../modules/wr_eca/eca_tlu_auto.vhd \
../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd \
../../modules/wr_streamers/xwr_transmission.vhd \
../../modules/wr_streamers/dropping_buffer.vhd \
../../modules/wr_softpll_ng/wr_softpll_ng.vhd \
../../modules/wr_tbi_phy/disparity_gen_pkg.vhd \
......@@ -298,7 +301,7 @@ svec_wr_ref.xise \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd \
../../ip_cores/general-cores/modules/common/matrix_pkg.vhd \
../../modules/wr_streamers/gc_escape_detector.vhd \
../../modules/wr_streamers/wr_streamers_wb.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd \
../../modules/wr_endpoint/ep_rx_vlan_unit.vhd \
../../ip_cores/general-cores/modules/common/gc_big_adder.vhd \
......@@ -362,10 +365,12 @@ svec_wr_ref.xise \
../../modules/wr_tbi_phy/wr_tbi_phy.vhd \
../../platform/xilinx/chipscope/chipscope_ila.ngc \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v \
../../modules/wr_eca/eca_queue_auto_pkg.vhd \
../../modules/timing/hpll_period_detect.vhd \
../../modules/wr_pps_gen/pps_gen_wb.vhd \
../../platform/xilinx/wr_gtp_phy/gtp_phase_align_virtex6.vhd \
../../modules/wr_endpoint/xwr_endpoint.vhd \
../../modules/wr_streamers/streamers_priv_pkg.vhd \
../../modules/wr_endpoint/ep_tx_packet_injection.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v \
......@@ -396,7 +401,7 @@ run.tcl \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd \
../../modules/wr_eca/eca_tdp.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd \
../../modules/wr_eca/eca_queue_auto_pkg.vhd \
../../modules/wr_streamers/xwr_streamers.vhd \
../../modules/wr_softpll_ng/softpll_pkg.vhd \
../../modules/wr_eca/eca_wr_time.vhd \
../../modules/wr_streamers/xrx_streamer.vhd \
......
syn/svec_ref_design/svec_wr_ref.xise
View file @ bcd1f0a3
This source diff could not be displayed because it is too large. You can view the blob instead.
syn/vfchd_ref_design/Makefile
View file @ bcd1f0a3
......@@ -13,7 +13,7 @@ synthesis:
echo "load_package flow" > run.tcl
echo "project_open $(PROJECT)" >> run.tcl
echo "execute_flow -compile" >> run.tcl
/opt/altera/16.0/quartus/bin/quartus_sh -t run.tcl
/home/greg/opt/altera/16.0/quartus/bin/quartus_sh -t run.tcl
check_tool:
......
syn/vfchd_ref_design/vfchd_wr_ref.qsf
View file @ bcd1f0a3
......@@ -464,17 +464,21 @@ set_location_assignment PIN_AG21 -to vfchd_gpio2_o
set_instance_assignment -name IO_STANDARD "2.5 V" -to vfchd_gpio2_o
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to vfchd_gpio2_o
set_instance_assignment -name SLEW_RATE 1 -to vfchd_gpio2_o
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VHDL_FILE ../../modules/wr_pps_gen/wr_pps_gen.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_si57x_interface/xwr_si57x_interface.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/xvme64x_core_pkg.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/xvme64x_core_pkg.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_tbi_phy/dec_8b10b.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_sync_detect.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_commit_fifo.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_slave_wrapper.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/altera/altera_async_fifo.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_commit_fifo.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_slave_wrapper.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/genrams/altera/altera_async_fifo.vhd
set_global_assignment -name VHDL_FILE ../../modules/fabric/xwrf_loopback/wrf_loopback.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_tx_inject_ctrl.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_wishbone_controller.vhd
......@@ -482,307 +486,312 @@ set_global_assignment -name VHDL_FILE ../../modules/wr_si57x_interface/si570_if_
set_global_assignment -name VHDL_FILE ../../modules/wr_tbi_phy/enc_8b10b.vhd
set_global_assignment -name VHDL_FILE ../../modules/wrc_core/wrc_syscon_pkg.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_tlu_fsm.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_master_core/eb_record_gen.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_wb_if.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/platform/altera/networks/altera_networks_pkg.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/etherbone-core/hdl/eb_master_core/eb_record_gen.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_wb_if.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/platform/altera/networks/altera_networks_pkg.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_free.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_rtu_header_extract.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_tx_path.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_tx_pcs_16bit.vhd
set_global_assignment -name VHDL_FILE ../../modules/wrc_core/wrc_periph.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_pkg.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd
set_global_assignment -name VHDL_FILE ../../top/vfchd_ref_design/vfchd_wr_ref_top.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_rx_oob_insert.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_moving_average.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/altera/gc_shiftreg.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/common/gc_moving_average.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/genrams/altera/gc_shiftreg.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_msi.vhd
set_global_assignment -name VHDL_FILE ../../modules/wrc_core/wr_core.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_reset.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/common/gc_reset.vhd
set_global_assignment -name VHDL_FILE ../../modules/timing/multi_dmtd_with_deglitcher.vhd
set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v"
set_global_assignment -name VERILOG_FILE ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v
set_global_assignment -name VHDL_FILE ../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Am_Match.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_mini_nic/xwr_mini_nic.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_SharedComps.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_SharedComps.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_tx_header_processor.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gencores_pkg.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/altera/generic_spram.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_register_link.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/common/gencores_pkg.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/genrams/altera/generic_spram.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_register_link.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_channel.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/wr_eca.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_altera.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_altera.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_offset.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_crc32_pkg.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_rx_pcs_8bit.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_softpll_ng/spll_wbgen2_pkg.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_wb_event.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_tlu/tlu_fsm.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/altera/altera_sync_fifo.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/genrams/altera/altera_sync_fifo.vhd
set_global_assignment -name VHDL_FILE ../../modules/fabric/xwrf_loopback/lbk_pkg.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_dacs/spec_serial_dac_arb.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_streamers/xrx_streamers_stats.vhd
set_global_assignment -name VHDL_FILE ../../modules/wrc_core/wrc_diags_pkg.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_auto.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_rx_crc_size_check.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_streamers/wr_transmission_wb.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME64xCore_Top.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME64xCore_Top.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_tlu/tlu_pkg.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_64to32.vhd"
set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v"
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_64to32.vhd
set_global_assignment -name VERILOG_FILE ../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_ac_wbm_auto.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_softpll_ng/xwr_softpll_ng.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_tlu.vhd
set_global_assignment -name VHDL_FILE ../../modules/wrc_core/xwr_syscon_wb.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_pkg.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_pkg.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_mini_nic/minic_wb_slave.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd
set_global_assignment -name VHDL_FILE ../../modules/fabric/wr_fabric_pkg.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_sdp.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CR_pack.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CR_pack.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_scan.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_streamers/xrtx_streamers_stats.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_rx_path.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_streamers/dropping_buffer.vhd
set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v"
set_global_assignment -name VERILOG_FILE ../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v
set_global_assignment -name VHDL_FILE ../../modules/fabric/xwrf_reg.vhd
set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd"
set_global_assignment -name VERILOG_FILE ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_ac_wbm_auto_pkg.vhd
set_global_assignment -name VHDL_FILE ../../modules/timing/dmtd_phase_meas.vhd
set_global_assignment -name VHDL_FILE ../../platform/altera/xwrc_platform_altera.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_rx_pcs_16bit.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_scubus_channel.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd
set_global_assignment -name VHDL_FILE ../../modules/timing/pulse_stamper.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_streamers/streamers_pkg.vhd
set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v"
set_global_assignment -name VERILOG_FILE ../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/endpoint_pkg.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_streamers/rx_streamer.vhd
set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/altera/jtag_tap.v"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd"
set_global_assignment -name VERILOG_FILE ../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/altera/jtag_tap.v
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd
set_global_assignment -name VHDL_FILE ../../modules/timing/dmtd_with_deglitcher.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/xvme64x_core.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Access_Decode.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Funct_Match.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/xvme64x_core.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Access_Decode.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Funct_Match.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_timestamping_unit.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_bus.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_bus.vhd
set_global_assignment -name VHDL_FILE ../../modules/fabric/xwb_fabric_sink.vhd
set_global_assignment -name VHDL_FILE ../../platform/altera/wr_arria5_phy/wr_arria5_phy.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_sync_detect_16bit.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_si57x_interface/si570_if_wb.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_rx_wb_master.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd
set_global_assignment -name VHDL_FILE ../../modules/wrc_core/wrcore_pkg.vhd
set_global_assignment -name VERILOG_FILE ../../top/vfchd_ref_design/vfchd_i2cmux/SfpIdReader.v
set_global_assignment -name VHDL_FILE ../../platform/altera/wr_altera_pkg.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_adder.vhd
set_global_assignment -name VHDL_FILE ../../top/vfchd_ref_design/vfchd_i2cmux/vfchd_i2cmux_pkg.vhd
set_global_assignment -name SDC_FILE vfchd_wr_ref.sdc
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd
set_global_assignment -name VHDL_FILE ../../modules/fabric/xwrf_mux.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_single_reset_gen.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd
set_global_assignment -name VHDL_FILE ../../modules/wrc_core/xwrc_diags_wb.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/common/gc_single_reset_gen.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_tlu/tlu.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/platform/altera/flash/altera_spi.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_streamers/escape_detector.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/platform/altera/flash/altera_spi.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_piso_fifo.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_top.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_top.vhd
set_global_assignment -name VHDL_FILE ../../modules/wrc_core/wrc_syscon_wb.vhd
set_global_assignment -name VHDL_FILE ../../modules/wrc_core/wrc_dpram.vhd
set_global_assignment -name VHDL_FILE ../../modules/wrc_core/xwr_core.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_word_packer.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/common/gc_word_packer.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_rmw.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_tx_pcs_8bit.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/vme64x_pack.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/vme64x_pack.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_tx_vlan_unit.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_raw_slave.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_raw_slave.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_dacs/spec_serial_dac.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Am_Match.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wrc_core/wrc_diags_wb.vhd
set_global_assignment -name VERILOG_FILE ../../top/vfchd_ref_design/vfchd_i2cmux/I2cMuxAndExpMaster.v
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_IRQ_Controller.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_IRQ_Controller.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_pps_gen/xwr_pps_gen.vhd
set_global_assignment -name VHDL_FILE ../../board/common/xwrc_board_common.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_async_signals_input_stage.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/common/gc_async_signals_input_stage.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd
set_global_assignment -name VHDL_FILE ../../modules/fabric/xwb_fabric_source.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_tlu_auto.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_tlu_auto_pkg.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_tbi_phy/wr_tbi_phy.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_streamers/gc_escape_inserter.vhd
set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v"
set_global_assignment -name VHDL_FILE ../../modules/wr_streamers/xwr_transmission.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_streamers/wr_transmission_wbgen2_pkg.vhd
set_global_assignment -name VERILOG_FILE ../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_streamers/xwr_streamers.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_softpll_ng/spll_wb_slave.vhd
set_global_assignment -name VHDL_FILE ../../modules/timing/hpll_period_detect.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_tbi_phy/disparity_gen_pkg.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_pps_gen/pps_gen_wb.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_rx_status_reg_insert.vhd
set_global_assignment -name VHDL_FILE ../../board/vfchd/sfp_i2c_adapter.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_streamers/xtx_streamers_stats.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/xwr_endpoint.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_streamers/streamers_priv_pkg.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_registers_pkg.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_autonegotiation.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/altera/generic_simple_dpram.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/genrams/altera/generic_simple_dpram.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_tx_packet_injection.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/endpoint_private_pkg.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_wbm_fifo.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd"
set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v"
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_wbm_fifo.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd
set_global_assignment -name VERILOG_FILE ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_clock_alignment_fifo.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_tlp.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_tlp.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_tx_crc_inserter.vhd
set_global_assignment -name VHDL_FILE ../../board/vfchd/wrc_board_vfchd.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_tx.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_tx.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd
set_global_assignment -name VHDL_FILE ../../board/common/wr_board_pkg.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd"
set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v"
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd
set_global_assignment -name VERILOG_FILE ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_rx_early_address_match.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_si57x_interface/wr_si57x_interface.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_softpll_ng/spll_aligner.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Init.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CRAM.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_fifos.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Init.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CRAM.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_fifos.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/wr_endpoint.vhd
set_global_assignment -name VHDL_FILE ../../board/vfchd/wr_vfchd_pkg.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_softpll_ng/spll_period_detect.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_wr_time.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_ts_counter.vhd
set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd"
set_global_assignment -name VERILOG_FILE ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_ac_wbm.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_data.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd
set_global_assignment -name VHDL_FILE ../../board/vfchd/xwrc_board_vfchd.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_queue.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_mini_nic/minic_wbgen2_pkg.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_auto_pkg.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_crossbar/wb_skidpad.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_crossbar/wb_skidpad.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd
set_global_assignment -name VHDL_FILE ../../modules/fabric/xwrf_loopback/xwrf_loopback.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_rx_buffer.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_mini_nic/minic_packet_buffer.vhd
set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd"
set_global_assignment -name VERILOG_FILE ../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_internals_pkg.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_streamers/xtx_streamer.vhd
set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_32to64.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd"
set_global_assignment -name VERILOG_FILE ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_32to64.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd
set_global_assignment -name VHDL_FILE ../../modules/fabric/xwrf_loopback/lbk_wishbone_controller.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_pass_fifo.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_pass_fifo.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_mini_nic/wr_mini_nic.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_master_core/eb_commit_len_fifo.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_wb.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_master_core/eb_framer.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/platform/altera/flash/flash_top.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/altera/generic_dpram.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_sync_register.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/matrix_pkg.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wr_streamers/gc_escape_detector.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/etherbone-core/hdl/eb_master_core/eb_commit_len_fifo.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_wb.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/etherbone-core/hdl/eb_master_core/eb_framer.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/platform/altera/flash/flash_top.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/genrams/altera/generic_dpram.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/common/gc_sync_register.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/common/matrix_pkg.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd
set_global_assignment -name VHDL_FILE ../../modules/timing/pulse_gen.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_rx_vlan_unit.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_big_adder.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/common/gc_big_adder.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_softpll_ng/wr_softpll_ng.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_ethernet_slave.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/altera/generic_dpram_mixed.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_ethernet_slave.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/genrams/altera/generic_dpram_mixed.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_1000basex_pcs.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_swapper.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd"
set_global_assignment -name VERILOG_FILE "../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v"
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/platform/altera/flash/altera_flash_pkg.vhd"
set_global_assignment -name VHDL_FILE ../../modules/wrc_core/wb_reset.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_swapper.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_streamers/wr_streamers_wb.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd
set_global_assignment -name VERILOG_FILE ../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v
set_global_assignment -name VHDL_FILE ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/platform/altera/flash/altera_flash_pkg.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_tag_channel.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_tdp.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Wb_master.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CSR_pack.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Wb_master.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CSR_pack.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_search.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_queue_auto_pkg.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_wb_pkg.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_eth_tx.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/platform/altera/wb_pcie/pcie_wb_pkg.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_eth_tx.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_queue_auto.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_streamers/tx_streamer.vhd
set_global_assignment -name VERILOG_FILE ../../top/vfchd_ref_design/vfchd_i2cmux/I2cMuxAndExpReqArbiter.v
set_global_assignment -name VHDL_FILE ../../modules/wr_streamers/xrx_streamer.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_rx_bypass_queue.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tag_fifo.vhd"
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_streamers/escape_inserter.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tag_fifo.vhd
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_leds_controller.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_eca/eca_walker.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_softpll_ng/softpll_pkg.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/general-cores/modules/wishbone/wbgenplus/wbgenplus_pkg.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/general-cores/modules/wishbone/wbgenplus/wbgenplus_pkg.vhd
set_global_assignment -name VHDL_FILE ../../modules/wr_endpoint/ep_packet_filter.vhd
set_global_assignment -name VHDL_FILE "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd"
set_global_assignment -name VHDL_FILE ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:quartus_preflow.tcl"
......
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