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bd46dc5b
Commit
bd46dc5b
authored
Oct 26, 2011
by
Grzegorz Daniluk
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pps_gen: adding wb slave adapter, timecode output and pps valid
parent
77dd337a
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Showing
3 changed files
with
150 additions
and
19 deletions
+150
-19
pps_gen_wb.vhd
modules/wrsw_pps_gen/pps_gen_wb.vhd
+61
-4
wrsw_pps_gen.vhd
modules/wrsw_pps_gen/wrsw_pps_gen.vhd
+66
-15
wrsw_pps_gen.wb
modules/wrsw_pps_gen/wrsw_pps_gen.wb
+23
-0
No files found.
modules/wrsw_pps_gen/pps_gen_wb.vhd
View file @
bd46dc5b
...
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : pps_gen_wb.vhd
-- Author : auto-generated by wbgen2 from wrsw_pps_gen.wb
-- Created :
Mon May 9 00:28:48
2011
-- Created :
Thu Oct 27 00:59:03
2011
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_pps_gen.wb
...
...
@@ -57,7 +57,11 @@ entity pps_gen_wb is
-- Ports for asynchronous (clock: refclk_i) RW/RW BIT field: 'Sync to external PPS input' in reg: 'External sync control register'
ppsg_escr_sync_o
:
out
std_logic
;
ppsg_escr_sync_i
:
in
std_logic
;
ppsg_escr_sync_load_o
:
out
std_logic
ppsg_escr_sync_load_o
:
out
std_logic
;
-- Port for asynchronous (clock: refclk_i) BIT field: 'PPS output valid' in reg: 'External sync control register'
ppsg_escr_pps_val_o
:
out
std_logic
;
-- Port for asynchronous (clock: refclk_i) BIT field: 'Timecode output(UTC+nanosec) valid' in reg: 'External sync control register'
ppsg_escr_tc_val_o
:
out
std_logic
);
end
pps_gen_wb
;
...
...
@@ -121,6 +125,12 @@ signal ppsg_escr_sync_lw_s0 : std_logic ;
signal
ppsg_escr_sync_lw_s1
:
std_logic
;
signal
ppsg_escr_sync_lw_s2
:
std_logic
;
signal
ppsg_escr_sync_rwsel
:
std_logic
;
signal
ppsg_escr_pps_val_int
:
std_logic
;
signal
ppsg_escr_pps_val_sync0
:
std_logic
;
signal
ppsg_escr_pps_val_sync1
:
std_logic
;
signal
ppsg_escr_tc_val_int
:
std_logic
;
signal
ppsg_escr_tc_val_sync0
:
std_logic
;
signal
ppsg_escr_tc_val_sync1
:
std_logic
;
signal
ack_sreg
:
std_logic_vector
(
9
downto
0
);
signal
rddata_reg
:
std_logic_vector
(
31
downto
0
);
signal
wrdata_reg
:
std_logic_vector
(
31
downto
0
);
...
...
@@ -180,6 +190,8 @@ begin
ppsg_escr_sync_lw_read_in_progress
<=
'0'
;
ppsg_escr_sync_rwsel
<=
'0'
;
ppsg_escr_sync_int_write
<=
'0'
;
ppsg_escr_pps_val_int
<=
'0'
;
ppsg_escr_tc_val_int
<=
'0'
;
elsif
rising_edge
(
bus_clock_int
)
then
-- advance the ACK generator shift register
ack_sreg
(
8
downto
0
)
<=
ack_sreg
(
9
downto
1
);
...
...
@@ -236,25 +248,32 @@ begin
case
rwaddr_reg
(
2
downto
0
)
is
when
"000"
=>
if
(
wb_we_i
=
'1'
)
then
rddata_reg
(
0
)
<=
'X'
;
ppsg_cr_cnt_rst_int
<=
wrdata_reg
(
0
);
ppsg_cr_cnt_rst_int_delay
<=
wrdata_reg
(
0
);
ppsg_cr_cnt_en_int
<=
wrdata_reg
(
1
);
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
ppsg_cr_cnt_adj_int_write
<=
wrdata_reg
(
2
);
ppsg_cr_cnt_adj_lw
<=
'1'
;
ppsg_cr_cnt_adj_lw_delay
<=
'1'
;
ppsg_cr_cnt_adj_lw_read_in_progress
<=
'0'
;
ppsg_cr_cnt_adj_rwsel
<=
'1'
;
rddata_reg
(
3
)
<=
'X'
;
ppsg_cr_cnt_set_int
<=
wrdata_reg
(
3
);
ppsg_cr_cnt_set_int_delay
<=
wrdata_reg
(
3
);
ppsg_cr_pwidth_int
<=
wrdata_reg
(
31
downto
4
);
ppsg_cr_pwidth_swb
<=
'1'
;
ppsg_cr_pwidth_swb_delay
<=
'1'
;
else
rddata_reg
(
0
)
<=
'X'
;
rddata_reg
(
1
)
<=
ppsg_cr_cnt_en_int
;
rddata_reg
(
2
)
<=
'X'
;
ppsg_cr_cnt_adj_lw
<=
'1'
;
ppsg_cr_cnt_adj_lw_delay
<=
'1'
;
ppsg_cr_cnt_adj_lw_read_in_progress
<=
'1'
;
ppsg_cr_cnt_adj_rwsel
<=
'0'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
31
downto
4
)
<=
ppsg_cr_pwidth_int
;
end
if
;
ack_sreg
(
5
)
<=
'1'
;
...
...
@@ -433,18 +452,24 @@ begin
ack_in_progress
<=
'1'
;
when
"111"
=>
if
(
wb_we_i
=
'1'
)
then
rddata_reg
(
0
)
<=
'X'
;
ppsg_escr_sync_int_write
<=
wrdata_reg
(
0
);
ppsg_escr_sync_lw
<=
'1'
;
ppsg_escr_sync_lw_delay
<=
'1'
;
ppsg_escr_sync_lw_read_in_progress
<=
'0'
;
ppsg_escr_sync_rwsel
<=
'1'
;
ppsg_escr_pps_val_int
<=
wrdata_reg
(
1
);
rddata_reg
(
1
)
<=
'X'
;
ppsg_escr_tc_val_int
<=
wrdata_reg
(
2
);
rddata_reg
(
2
)
<=
'X'
;
else
rddata_reg
(
0
)
<=
'X'
;
ppsg_escr_sync_lw
<=
'1'
;
ppsg_escr_sync_lw_delay
<=
'1'
;
ppsg_escr_sync_lw_read_in_progress
<=
'1'
;
ppsg_escr_sync_rwsel
<=
'0'
;
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
1
)
<=
ppsg_escr_pps_val_int
;
rddata_reg
(
2
)
<=
ppsg_escr_tc_val_int
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
...
...
@@ -689,6 +714,38 @@ begin
end
process
;
-- PPS output valid
-- synchronizer chain for field : PPS output valid (type RW/RO, bus_clock_int <-> refclk_i)
process
(
refclk_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
'0'
)
then
ppsg_escr_pps_val_o
<=
'0'
;
ppsg_escr_pps_val_sync0
<=
'0'
;
ppsg_escr_pps_val_sync1
<=
'0'
;
elsif
rising_edge
(
refclk_i
)
then
ppsg_escr_pps_val_sync0
<=
ppsg_escr_pps_val_int
;
ppsg_escr_pps_val_sync1
<=
ppsg_escr_pps_val_sync0
;
ppsg_escr_pps_val_o
<=
ppsg_escr_pps_val_sync1
;
end
if
;
end
process
;
-- Timecode output(UTC+nanosec) valid
-- synchronizer chain for field : Timecode output(UTC+nanosec) valid (type RW/RO, bus_clock_int <-> refclk_i)
process
(
refclk_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
'0'
)
then
ppsg_escr_tc_val_o
<=
'0'
;
ppsg_escr_tc_val_sync0
<=
'0'
;
ppsg_escr_tc_val_sync1
<=
'0'
;
elsif
rising_edge
(
refclk_i
)
then
ppsg_escr_tc_val_sync0
<=
ppsg_escr_tc_val_int
;
ppsg_escr_tc_val_sync1
<=
ppsg_escr_tc_val_sync0
;
ppsg_escr_tc_val_o
<=
ppsg_escr_tc_val_sync1
;
end
if
;
end
process
;
rwaddr_reg
<=
wb_addr_i
;
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o
<=
ack_sreg
(
0
);
...
...
modules/wrsw_pps_gen/wrsw_pps_gen.vhd
View file @
bd46dc5b
...
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-09-02
-- Last update: 2011-
05-11
-- Last update: 2011-
10-26
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
...
...
@@ -18,6 +18,7 @@
-- Date Version Author Description
-- 2010-09-02 1.0 twlostow Created
-- 2011-05-09 1.1 twlostow Added external PPS input
-- 2011-10-26 1.2 greg.d Added wb slave adapter
-------------------------------------------------------------------------------
library
ieee
;
...
...
@@ -26,8 +27,13 @@ use ieee.numeric_std.all;
library
work
;
use
work
.
gencores_pkg
.
all
;
use
work
.
wishbone_pkg
.
all
;
entity
wrsw_pps_gen
is
generic
(
g_interface_mode
:
t_wishbone_interface_mode
:
=
CLASSIC
;
g_address_granularity
:
t_wishbone_address_granularity
:
=
WORD
);
port
(
clk_ref_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
...
...
@@ -42,13 +48,18 @@ entity wrsw_pps_gen is
wb_stb_i
:
in
std_logic
;
wb_we_i
:
in
std_logic
;
wb_ack_o
:
out
std_logic
;
wb_stall_o
:
out
std_logic
;
pps_in_i
:
in
std_logic
;
-- Single-pulse PPS output for synchronizing endpoints to
pps_csync_o
:
out
std_logic
;
pps_out_o
:
out
std_logic
pps_out_o
:
out
std_logic
;
pps_val_o
:
out
std_logic
;
tc_utc_o
:
out
std_logic_vector
(
39
downto
0
);
tc_nsec_o
:
out
std_logic_vector
(
27
downto
0
);
tc_val_o
:
out
std_logic
);
end
wrsw_pps_gen
;
...
...
@@ -87,7 +98,9 @@ architecture behavioral of wrsw_pps_gen is
ppsg_adj_utchi_wr_o
:
out
std_logic
;
ppsg_escr_sync_o
:
out
std_logic
;
ppsg_escr_sync_i
:
in
std_logic
;
ppsg_escr_sync_load_o
:
out
std_logic
);
ppsg_escr_sync_load_o
:
out
std_logic
;
ppsg_escr_pps_val_o
:
out
std_logic
;
ppsg_escr_tc_val_o
:
out
std_logic
);
end
component
;
...
...
@@ -111,12 +124,13 @@ architecture behavioral of wrsw_pps_gen is
signal
ppsg_adj_utclo
:
std_logic_vector
(
31
downto
0
);
signal
ppsg_adj_utclo_wr
:
std_logic
;
signal
ppsg_adj_utchi
:
std_logic_vector
(
7
downto
0
);
signal
ppsg_adj_utchi_wr
:
std_logic
;
signal
ppsg_escr_sync_load
:
std_logic
;
signal
ppsg_adj_utchi_wr
:
std_logic
;
signal
ppsg_escr_sync_load
:
std_logic
;
signal
ppsg_escr_sync_in
:
std_logic
;
signal
ppsg_escr_sync_out
:
std_logic
;
signal
ppsg_escr_pps_val
:
std_logic
;
signal
ppsg_escr_tc_val
:
std_logic
;
signal
cntr_nsec
:
unsigned
(
27
downto
0
);
signal
cntr_utc
:
unsigned
(
39
downto
0
);
...
...
@@ -139,9 +153,39 @@ architecture behavioral of wrsw_pps_gen is
signal
pps_in_p
:
std_logic
;
signal
sync_in_progress
:
std_logic
;
signal
ext_sync_p
:
std_logic
;
signal
resized_addr
:
std_logic_vector
(
c_wishbone_address_width
-1
downto
0
);
signal
wb_out
:
t_wishbone_slave_out
;
signal
wb_in
:
t_wishbone_slave_in
;
begin
-- behavioral
resized_addr
(
3
downto
0
)
<=
wb_addr_i
;
resized_addr
(
c_wishbone_address_width
-1
downto
4
)
<=
(
others
=>
'0'
);
U_Adapter
:
wb_slave_adapter
generic
map
(
g_master_use_struct
=>
true
,
g_master_mode
=>
CLASSIC
,
g_master_granularity
=>
WORD
,
g_slave_use_struct
=>
false
,
g_slave_mode
=>
g_interface_mode
,
g_slave_granularity
=>
g_address_granularity
)
port
map
(
clk_sys_i
=>
clk_sys_i
,
rst_n_i
=>
rst_n_i
,
master_i
=>
wb_out
,
master_o
=>
wb_in
,
sl_adr_i
=>
resized_addr
,
sl_dat_i
=>
wb_data_i
,
sl_sel_i
=>
wb_sel_i
,
sl_cyc_i
=>
wb_cyc_i
,
sl_stb_i
=>
wb_stb_i
,
sl_we_i
=>
wb_we_i
,
sl_dat_o
=>
wb_data_o
,
sl_ack_o
=>
wb_ack_o
,
sl_stall_o
=>
wb_stall_o
);
sync_reset_refclk
:
gc_sync_ffs
generic
map
(
...
...
@@ -308,14 +352,14 @@ begin -- behavioral
port
map
(
rst_n_i
=>
rst_n_i
,
wb_clk_i
=>
clk_sys_i
,
wb_addr_i
=>
wb_
addr_i
(
2
downto
0
),
wb_data_i
=>
wb_
data_i
,
wb_data_o
=>
wb_
data_o
,
wb_cyc_i
=>
wb_
cyc_i
,
wb_sel_i
=>
wb_
sel_i
,
wb_stb_i
=>
wb_
stb_i
,
wb_we_i
=>
wb_
we_i
,
wb_ack_o
=>
wb_
ack_o
,
wb_addr_i
=>
wb_
in
.
adr
(
2
downto
0
),
wb_data_i
=>
wb_
in
.
dat
,
wb_data_o
=>
wb_
out
.
dat
,
wb_cyc_i
=>
wb_
in
.
cyc
,
wb_sel_i
=>
wb_
in
.
sel
,
wb_stb_i
=>
wb_
in
.
stb
,
wb_we_i
=>
wb_
in
.
we
,
wb_ack_o
=>
wb_
out
.
ack
,
refclk_i
=>
clk_ref_i
,
ppsg_cr_cnt_rst_o
=>
ppsg_cr_cnt_rst
,
ppsg_cr_cnt_en_o
=>
ppsg_cr_cnt_en
,
...
...
@@ -335,7 +379,9 @@ begin -- behavioral
ppsg_adj_utclo_o
=>
ppsg_adj_utclo
,
ppsg_adj_utclo_wr_o
=>
ppsg_adj_utclo_wr
,
ppsg_adj_utchi_o
=>
ppsg_adj_utchi
,
ppsg_adj_utchi_wr_o
=>
ppsg_adj_utchi_wr
);
ppsg_adj_utchi_wr_o
=>
ppsg_adj_utchi_wr
,
ppsg_escr_pps_val_o
=>
ppsg_escr_pps_val
,
ppsg_escr_tc_val_o
=>
ppsg_escr_tc_val
);
-- start the adjustment upon write of 1 to CNT_ADJ bit
cntr_adjust_p
<=
ppsg_cr_cnt_adj_load
and
ppsg_cr_cnt_adj_o
;
...
...
@@ -377,5 +423,10 @@ begin -- behavioral
end
if
;
end
if
;
end
process
;
tc_utc_o
<=
std_logic_vector
(
cntr_utc
);
tc_nsec_o
<=
std_logic_vector
(
cntr_nsec
);
tc_val_o
<=
ppsg_escr_tc_val
;
pps_val_o
<=
ppsg_escr_pps_val
;
end
behavioral
;
modules/wrsw_pps_gen/wrsw_pps_gen.wb
View file @
bd46dc5b
...
...
@@ -169,6 +169,29 @@ peripheral {
load = LOAD_EXT;
clock = "refclk_i";
};
field {
name = "PPS output valid";
description = "write 1: PPS output provides reliable 1-PPS signal\
write 0: PPS output is invalid";
prefix = "PPS_VAL";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "refclk_i";
};
field {
name = "Timecode output(UTC+nanosec) valid";
description = "write 1: Timecode output provides valid time\
write 0: Timecode output does not provide valid time";
prefix = "TC_VAL";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "refclk_i";
};
};
};
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